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authorFabio Estevam <festevam@gmail.com>2020-07-13 10:05:09 -0300
committerShawn Guo <shawnguo@kernel.org>2020-07-20 10:22:12 +0800
commit198cf42cd82f4563baa34fa90aebdf6cfda60a9d (patch)
treef2fdb4e4c870c836f1fe332425b32f3569f6c5d6
parentARM: dts: imx6q-tbs2910: Add an mdio node (diff)
downloadlinux-dev-198cf42cd82f4563baa34fa90aebdf6cfda60a9d.tar.xz
linux-dev-198cf42cd82f4563baa34fa90aebdf6cfda60a9d.zip
ARM: dts: imx6q-tbs2910: Pass reset-assert-us
According to the AR8035 datasheet: "When using crystal, the clock is generated internally after power is stable. For a reliable power on reset, suggest to keep asserting the reset low long enough (10ms) to ensure the clock is stable and clock-to-reset 1ms requirement is satisfied." Pass the 'reset-assert-us' property to describe such requirement. While at it, use the 'reset-gpios' property inside the the mdio node instead of the deprecated usage of 'phy-reset-gpios'. Signed-off-by: Fabio Estevam <festevam@gmail.com> Reviewed-by: Soeren Moch <smoch@web.de> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
-rw-r--r--arch/arm/boot/dts/imx6q-tbs2910.dts3
1 files changed, 2 insertions, 1 deletions
diff --git a/arch/arm/boot/dts/imx6q-tbs2910.dts b/arch/arm/boot/dts/imx6q-tbs2910.dts
index 1f34028c6397..861e05d53157 100644
--- a/arch/arm/boot/dts/imx6q-tbs2910.dts
+++ b/arch/arm/boot/dts/imx6q-tbs2910.dts
@@ -99,7 +99,6 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet>;
phy-mode = "rgmii-id";
- phy-reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>;
phy-handle = <&phy>;
status = "okay";
@@ -110,6 +109,8 @@
phy: ethernet-phy@4 {
reg = <4>;
qca,clk-out-frequency = <125000000>;
+ reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>;
+ reset-assert-us = <10000>;
};
};
};