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authorEvan Quan <evan.quan@amd.com>2020-07-02 15:59:03 +0800
committerAlex Deucher <alexander.deucher@amd.com>2020-07-15 12:44:40 -0400
commit1e1964b777ce0934ff07d6654e77f070d5ba8f07 (patch)
tree2d5201f1e2a9cdf16a2138aac6a7dfa431e551bc
parentdrm/amd/powerplay: sort the call flow on temperature ranges retrieving (diff)
downloadlinux-dev-1e1964b777ce0934ff07d6654e77f070d5ba8f07.tar.xz
linux-dev-1e1964b777ce0934ff07d6654e77f070d5ba8f07.zip
drm/amd/powerplay: maximum the code sharing on thermal irq setting
Put the common code in smu_v11_0.c instead of having one copy each. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
-rw-r--r--drivers/gpu/drm/amd/powerplay/smu_v11_0.c16
1 files changed, 12 insertions, 4 deletions
diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
index 6f4278abc9ac..6f5c07e8851e 100644
--- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
@@ -1091,10 +1091,6 @@ int smu_v11_0_enable_thermal_alert(struct smu_context *smu)
struct amdgpu_device *adev = smu->adev;
if (smu->smu_table.thermal_controller_type) {
- ret = smu_set_thermal_range(smu, smu->thermal_range);
- if (ret)
- return ret;
-
ret = amdgpu_irq_get(adev, &smu->irq_source, 0);
if (ret)
return ret;
@@ -1349,6 +1345,8 @@ static int smu_v11_0_set_irq_state(struct amdgpu_device *adev,
unsigned tyep,
enum amdgpu_interrupt_state state)
{
+ struct smu_context *smu = &adev->smu;
+ uint32_t low, high;
uint32_t val = 0;
switch (state) {
@@ -1369,9 +1367,19 @@ static int smu_v11_0_set_irq_state(struct amdgpu_device *adev,
break;
case AMDGPU_IRQ_STATE_ENABLE:
/* For THM irqs */
+ low = max(SMU_THERMAL_MINIMUM_ALERT_TEMP,
+ smu->thermal_range.min / SMU_TEMPERATURE_UNITS_PER_CENTIGRADES);
+ high = min(SMU_THERMAL_MAXIMUM_ALERT_TEMP,
+ smu->thermal_range.software_shutdown_temp);
+
val = RREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL);
+ val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, MAX_IH_CREDIT, 5);
+ val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_IH_HW_ENA, 1);
val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTH_MASK, 0);
val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTL_MASK, 0);
+ val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTH, (high & 0xff));
+ val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTL, (low & 0xff));
+ val = val & (~THM_THERMAL_INT_CTRL__THERM_TRIGGER_MASK_MASK);
WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL, val);
val = (1 << THM_THERMAL_INT_ENA__THERM_INTH_CLR__SHIFT);