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authorMugunthan V N <mugunthanvnm@ti.com>2016-10-18 16:50:20 +0530
committerDavid S. Miller <davem@davemloft.net>2016-10-18 10:42:16 -0400
commit1f0655444201ff770efb66078808ecefbc54dfe9 (patch)
tree80b1e194a98522bab1a3e71e8e34f11b505d9d6c
parentARM: dts: dra72-evm-revc: add phy impedance settings (diff)
downloadlinux-dev-1f0655444201ff770efb66078808ecefbc54dfe9.tar.xz
linux-dev-1f0655444201ff770efb66078808ecefbc54dfe9.zip
ARM: dts: dra72-evm-revc: fix correct phy delay
The current delay settings of the phy are not the optimal value, fix it with correct values. Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> Signed-off-by: David S. Miller <davem@davemloft.net>
-rw-r--r--arch/arm/boot/dts/dra72-evm-revc.dts8
1 files changed, 4 insertions, 4 deletions
diff --git a/arch/arm/boot/dts/dra72-evm-revc.dts b/arch/arm/boot/dts/dra72-evm-revc.dts
index 54503673e15f..3b23b32e1b30 100644
--- a/arch/arm/boot/dts/dra72-evm-revc.dts
+++ b/arch/arm/boot/dts/dra72-evm-revc.dts
@@ -59,16 +59,16 @@
&davinci_mdio {
dp83867_0: ethernet-phy@2 {
reg = <2>;
- ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
- ti,tx-internal-delay = <DP83867_RGMIIDCTL_1_NS>;
+ ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
+ ti,tx-internal-delay = <DP83867_RGMIIDCTL_250_PS>;
ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_8_B_NIB>;
ti,min-output-impedance;
};
dp83867_1: ethernet-phy@3 {
reg = <3>;
- ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
- ti,tx-internal-delay = <DP83867_RGMIIDCTL_1_NS>;
+ ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
+ ti,tx-internal-delay = <DP83867_RGMIIDCTL_250_PS>;
ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_8_B_NIB>;
ti,min-output-imepdance;
};