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| author |   Maciej W. Rozycki <macro@linux-mips.org> | 2015-04-03 23:25:14 +0100 |
|---|---|---|
| committer |   Ralf Baechle <ralf@linux-mips.org> | 2015-04-08 01:09:20 +0200 |
| commit | 1f6d2c29b08bbd29a3d3b8476e9a26546e03104e (patch) | |
| tree | 5ad47f59ed30972d70b1dcaf5a7a4b89454462ae | |
| parent | MIPS: Normalise code flow in the CpU exception handler (diff) | |
| download | linux-dev-1f6d2c29b08bbd29a3d3b8476e9a26546e03104e.tar.xz linux-dev-1f6d2c29b08bbd29a3d3b8476e9a26546e03104e.zip | |
MIPS: Use `FPU_CSR_ALL_X' in `__build_clear_fpe'
Replace a hardcoded numeric bitmask for FCSR cause bits with
`FPU_CSR_ALL_X' in `__build_clear_fpe'.
Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/9684/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| -rw-r--r-- | arch/mips/kernel/genex.S | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/mips/kernel/genex.S b/arch/mips/kernel/genex.S index 2ebaabe3af15..07c4a25b16ea 100644 --- a/arch/mips/kernel/genex.S +++ b/arch/mips/kernel/genex.S @@ -360,7 +360,7 @@ NESTED(nmi_handler, PT_SIZE, sp) .set mips1 SET_HARDFLOAT cfc1 a1, fcr31 - li a2, ~(0x3f << 12) + li a2, ~FPU_CSR_ALL_X and a2, a1 ctc1 a2, fcr31 .set pop |