diff options
| author |   Stephan Gerhold <stephan@gerhold.net> | 2020-04-26 16:06:40 +0200 |
|---|---|---|
| committer |   Bjorn Andersson <bjorn.andersson@linaro.org> | 2020-05-12 11:22:10 -0700 |
| commit | 246d19d2c22e06b9ed31e44cf2dcd82000b207e8 (patch) | |
| tree | a9a70034b8e14ef604929c0f1dbbb740298360df | |
| parent | arm64: dts: qcom: msm8916: Add blsp_i2c1 (diff) | |
arm64: dts: qcom: msm8916: Add blsp_i2c5
MSM8916 has another I2C QUP controller that can be enabled on
GPIO 18 and 19.
Add blsp_i2c5 to msm8916.dtsi and disable it by default.
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
Link: https://lore.kernel.org/r/20200426140642.204395-3-stephan@gerhold.net
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
| -rw-r--r-- | arch/arm64/boot/dts/qcom/msm8916-pins.dtsi | 24 | ||||
| -rw-r--r-- | arch/arm64/boot/dts/qcom/msm8916.dtsi | 15 |
2 files changed, 39 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/qcom/msm8916-pins.dtsi b/arch/arm64/boot/dts/qcom/msm8916-pins.dtsi index b45fd12856ea..31886860766a 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-pins.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916-pins.dtsi @@ -334,6 +334,30 @@ }; }; + i2c5_default: i2c5_default { + pinmux { + function = "blsp_i2c5"; + pins = "gpio18", "gpio19"; + }; + pinconf { + pins = "gpio18", "gpio19"; + drive-strength = <2>; + bias-disable; + }; + }; + + i2c5_sleep: i2c5_sleep { + pinmux { + function = "gpio"; + pins = "gpio18", "gpio19"; + }; + pinconf { + pins = "gpio18", "gpio19"; + drive-strength = <2>; + bias-disable; + }; + }; + i2c6_default: i2c6_default { pinmux { function = "blsp_i2c6"; diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi index 6ab7cabde370..57ab5573a2d2 100644 --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi @@ -657,6 +657,21 @@ status = "disabled"; }; + blsp_i2c5: i2c@78b9000 { + compatible = "qcom,i2c-qup-v2.2.1"; + reg = <0x078b9000 0x500>; + interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc GCC_BLSP1_AHB_CLK>, + <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>; + clock-names = "iface", "core"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&i2c5_default>; + pinctrl-1 = <&i2c5_sleep>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + blsp_i2c6: i2c@78ba000 { compatible = "qcom,i2c-qup-v2.2.1"; reg = <0x078ba000 0x500>; |