diff options
| author |   Andy Shevchenko <andriy.shevchenko@linux.intel.com> | 2015-07-13 17:07:43 +0300 |
|---|---|---|
| committer |   Stephen Boyd <sboyd@codeaurora.org> | 2015-07-28 11:59:16 -0700 |
| commit | 25d4d341d31b349836e1b12d10be34b9b575c12b (patch) | |
| tree | b30d9d7137682cac25f68504e0524b644526fd87 | |
| parent | clk: pxa: fix core frequency reporting unit (diff) | |
| download | linux-dev-25d4d341d31b349836e1b12d10be34b9b575c12b.tar.xz linux-dev-25d4d341d31b349836e1b12d10be34b9b575c12b.zip | |
clk: socfpga: switch to GENMASK()
Convert the code to use GENMASK() helper instead of div_mask() macro.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
| -rw-r--r-- | drivers/clk/socfpga/clk-gate-a10.c | 2 | ||||
| -rw-r--r-- | drivers/clk/socfpga/clk-gate.c | 2 | ||||
| -rw-r--r-- | drivers/clk/socfpga/clk-periph-a10.c | 2 | ||||
| -rw-r--r-- | drivers/clk/socfpga/clk-periph.c | 2 | ||||
| -rw-r--r-- | drivers/clk/socfpga/clk.h | 1 |
5 files changed, 4 insertions, 5 deletions
diff --git a/drivers/clk/socfpga/clk-gate-a10.c b/drivers/clk/socfpga/clk-gate-a10.c index 538ca504dea1..1cebf253e8fd 100644 --- a/drivers/clk/socfpga/clk-gate-a10.c +++ b/drivers/clk/socfpga/clk-gate-a10.c @@ -39,7 +39,7 @@ static unsigned long socfpga_gate_clk_recalc_rate(struct clk_hw *hwclk, div = socfpgaclk->fixed_div; else if (socfpgaclk->div_reg) { val = readl(socfpgaclk->div_reg) >> socfpgaclk->shift; - val &= div_mask(socfpgaclk->width); + val &= GENMASK(socfpgaclk->width - 1, 0); div = (1 << val); } diff --git a/drivers/clk/socfpga/clk-gate.c b/drivers/clk/socfpga/clk-gate.c index 37e0bb60ac68..aa7a6e6a15b6 100644 --- a/drivers/clk/socfpga/clk-gate.c +++ b/drivers/clk/socfpga/clk-gate.c @@ -105,7 +105,7 @@ static unsigned long socfpga_clk_recalc_rate(struct clk_hw *hwclk, div = socfpgaclk->fixed_div; else if (socfpgaclk->div_reg) { val = readl(socfpgaclk->div_reg) >> socfpgaclk->shift; - val &= div_mask(socfpgaclk->width); + val &= GENMASK(socfpgaclk->width - 1, 0); /* Check for GPIO_DB_CLK by its offset */ if ((int) socfpgaclk->div_reg & SOCFPGA_GPIO_DB_CLK_OFFSET) div = val + 1; diff --git a/drivers/clk/socfpga/clk-periph-a10.c b/drivers/clk/socfpga/clk-periph-a10.c index 64f93acbbd25..1f397cb72e89 100644 --- a/drivers/clk/socfpga/clk-periph-a10.c +++ b/drivers/clk/socfpga/clk-periph-a10.c @@ -38,7 +38,7 @@ static unsigned long clk_periclk_recalc_rate(struct clk_hw *hwclk, div = socfpgaclk->fixed_div; } else if (socfpgaclk->div_reg) { div = readl(socfpgaclk->div_reg) >> socfpgaclk->shift; - div &= div_mask(socfpgaclk->width); + div &= GENMASK(socfpgaclk->width - 1, 0); div += 1; } else { div = ((readl(socfpgaclk->hw.reg) & 0x7ff) + 1); diff --git a/drivers/clk/socfpga/clk-periph.c b/drivers/clk/socfpga/clk-periph.c index ab9c8164a98f..0c6686331493 100644 --- a/drivers/clk/socfpga/clk-periph.c +++ b/drivers/clk/socfpga/clk-periph.c @@ -35,7 +35,7 @@ static unsigned long clk_periclk_recalc_rate(struct clk_hw *hwclk, } else { if (socfpgaclk->div_reg) { val = readl(socfpgaclk->div_reg) >> socfpgaclk->shift; - val &= div_mask(socfpgaclk->width); + val &= GENMASK(socfpgaclk->width - 1, 0); parent_rate /= (val + 1); } div = ((readl(socfpgaclk->hw.reg) & 0x1ff) + 1); diff --git a/drivers/clk/socfpga/clk.h b/drivers/clk/socfpga/clk.h index f4219202844a..aa2741dbe81a 100644 --- a/drivers/clk/socfpga/clk.h +++ b/drivers/clk/socfpga/clk.h @@ -26,7 +26,6 @@ #define CLKMGR_PERPLL_SRC 0xAC #define SOCFPGA_MAX_PARENTS 5 -#define div_mask(width) ((1 << (width)) - 1) #define streq(a, b) (strcmp((a), (b)) == 0) #define SYSMGR_SDMMC_CTRL_SET(smplsel, drvsel) \ |