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authorHuacai Chen <chenhc@lemote.com>2018-09-15 14:01:12 +0800
committerPaul Burton <paul.burton@mips.com>2018-09-18 15:56:48 -0700
commit2794f688b2c336e0da85e9f91fed33febbd9f54a (patch)
tree7b8fa987b19001f5f0d713247eac4a26c4ab9bf5
parentmips: switch to NO_BOOTMEM (diff)
downloadlinux-dev-2794f688b2c336e0da85e9f91fed33febbd9f54a.tar.xz
linux-dev-2794f688b2c336e0da85e9f91fed33febbd9f54a.zip
MIPS/PCI: Call pcie_bus_configure_settings() to set MPS/MRRS
Call pcie_bus_configure_settings() on MIPS, like for other platforms. The function pcie_bus_configure_settings() makes sure the MPS (Max Payload Size) across the bus is uniform and provides the ability to tune the MRSS (Max Read Request Size) and MPS (Max Payload Size) to higher performance values. Some devices will not operate properly if these aren't set correctly because the firmware doesn't always do it. Signed-off-by: Huacai Chen <chenhc@lemote.com> Signed-off-by: Paul Burton <paul.burton@mips.com> Patchwork: https://patchwork.linux-mips.org/patch/20649/ Cc: Ralf Baechle <ralf@linux-mips.org> Cc: James Hogan <jhogan@kernel.org> Cc: linux-mips@linux-mips.org Cc: Fuxin Zhang <zhangfx@lemote.com> Cc: Zhangjin Wu <wuzhangjin@gmail.com> Cc: Huacai Chen <chenhuacai@gmail.com>
-rw-r--r--arch/mips/pci/pci-legacy.c4
1 files changed, 4 insertions, 0 deletions
diff --git a/arch/mips/pci/pci-legacy.c b/arch/mips/pci/pci-legacy.c
index f1e92bf743c2..3c3b1e6abb53 100644
--- a/arch/mips/pci/pci-legacy.c
+++ b/arch/mips/pci/pci-legacy.c
@@ -127,8 +127,12 @@ static void pcibios_scanbus(struct pci_controller *hose)
if (pci_has_flag(PCI_PROBE_ONLY)) {
pci_bus_claim_resources(bus);
} else {
+ struct pci_bus *child;
+
pci_bus_size_bridges(bus);
pci_bus_assign_resources(bus);
+ list_for_each_entry(child, &bus->children, node)
+ pcie_bus_configure_settings(child);
}
pci_bus_add_devices(bus);
}