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| author |   Miquel Raynal <miquel.raynal@bootlin.com> | 2019-10-04 16:27:28 +0200 |
|---|---|---|
| committer |   Gregory CLEMENT <gregory.clement@bootlin.com> | 2019-10-09 09:36:41 +0200 |
| commit | 2bc26088ba37d4f2a4b8bd813ee757992522d082 (patch) | |
| tree | 43c2968b441730febf43925793b7c59f43feb136 | |
| parent | arm64: dts: marvell: Add AP807-quad cache description (diff) | |
arm64: dts: marvell: Fix CP110 NAND controller node multi-line comment alignment
Fix this tiny typo before renaming/changing this file.
Fixes: 72a3713fadfd ("arm64: dts: marvell: de-duplicate CP110 description")
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
| -rw-r--r-- | arch/arm64/boot/dts/marvell/armada-cp110.dtsi | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/arch/arm64/boot/dts/marvell/armada-cp110.dtsi b/arch/arm64/boot/dts/marvell/armada-cp110.dtsi index d81944902650..8259fc8f86f2 100644 --- a/arch/arm64/boot/dts/marvell/armada-cp110.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-cp110.dtsi @@ -438,10 +438,10 @@ CP110_LABEL(nand_controller): nand@720000 { /* - * Due to the limitation of the pins available - * this controller is only usable on the CPM - * for A7K and on the CPS for A8K. - */ + * Due to the limitation of the pins available + * this controller is only usable on the CPM + * for A7K and on the CPS for A8K. + */ compatible = "marvell,armada-8k-nand-controller", "marvell,armada370-nand-controller"; reg = <0x720000 0x54>; |