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| author |   Marc Zyngier <maz@kernel.org> | 2022-04-05 19:23:24 +0100 |
|---|---|---|
| committer | Marc Zyngier <maz@kernel.org> | 2022-05-04 14:09:52 +0100 |
| commit | 34453c2e9f799d02f5f379519495208bbd96a935 (patch) | |
| tree | 47f9e509f80b9199f9ba9e9565fe412ea22b4c55 | |
| parent | Linux 5.18-rc3 (diff) | |
| download | linux-dev-34453c2e9f799d02f5f379519495208bbd96a935.tar.xz linux-dev-34453c2e9f799d02f5f379519495208bbd96a935.zip | |
irqchip/gic-v3: Exposes bit values for GICR_CTLR.{IR, CES}
As we're about to expose GICR_CTLR.{IR,CES} to guests, populate
the include file with the architectural values.
Signed-off-by: Marc Zyngier <maz@kernel.org>
Reviewed-by: Oliver Upton <oupton@google.com>
Link: https://lore.kernel.org/r/20220405182327.205520-2-maz@kernel.org
| -rw-r--r-- | include/linux/irqchip/arm-gic-v3.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/include/linux/irqchip/arm-gic-v3.h b/include/linux/irqchip/arm-gic-v3.h index 12d91f0dedf9..728691365464 100644 --- a/include/linux/irqchip/arm-gic-v3.h +++ b/include/linux/irqchip/arm-gic-v3.h @@ -127,6 +127,8 @@ #define GICR_PIDR2 GICD_PIDR2 #define GICR_CTLR_ENABLE_LPIS (1UL << 0) +#define GICR_CTLR_CES (1UL << 1) +#define GICR_CTLR_IR (1UL << 2) #define GICR_CTLR_RWP (1UL << 3) #define GICR_TYPER_CPU_NUMBER(r) (((r) >> 8) & 0xffff) |