diff options
| author | 2022-05-08 18:56:13 +0100 | |
|---|---|---|
| committer | 2022-06-14 11:53:14 +0100 | |
| commit | 3a828f204a110dc9f253c4cf3c1103d00a0681da (patch) | |
| tree | 2b7c31c49afab707a5ff81cfea41cec0e4965558 | |
| parent | iio: adc: ti-adc128s052: Fix alignment for DMA safety (diff) | |
iio: adc: ti-adc161s626: Fix alignment for DMA safety
____cacheline_aligned is an insufficient guarantee for non-coherent DMA
on platforms with 128 byte cachelines above L1. Switch to the updated
IIO_DMA_MINALIGN definition.
Fixes: 4d671b71beef ("iio: adc: ti-adc161s626: add support for TI 1-channel differential ADCs")
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Cc: Matt Ranostay <mranostay@gmail.com>
Acked-by: Nuno Sá <nuno.sa@analog.com>
Link: https://lore.kernel.org/r/20220508175712.647246-34-jic23@kernel.org
| -rw-r--r-- | drivers/iio/adc/ti-adc161s626.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/iio/adc/ti-adc161s626.c b/drivers/iio/adc/ti-adc161s626.c index 75ca7f1c8726..b789891dcf49 100644 --- a/drivers/iio/adc/ti-adc161s626.c +++ b/drivers/iio/adc/ti-adc161s626.c @@ -71,7 +71,7 @@ struct ti_adc_data { u8 read_size; u8 shift; - u8 buffer[16] ____cacheline_aligned; + u8 buffer[16] __aligned(IIO_DMA_MINALIGN); }; static int ti_adc_read_measurement(struct ti_adc_data *data, |
