diff options
| author |   Linus Torvalds <torvalds@linux-foundation.org> | 2019-09-19 14:19:33 -0700 |
|---|---|---|
| committer | Linus Torvalds <torvalds@linux-foundation.org> | 2019-09-19 14:19:33 -0700 |
| commit | 3c2edc36a77420d8be05d656019dbc8c31535992 (patch) | |
| tree | 70d8c9abb04c89e82c79c46efd2f7cb1bf836ef5 | |
| parent | Merge tag 'tag-chrome-platform-for-v5.4' of git://git.kernel.org/pub/scm/linux/kernel/git/chrome-platform/linux (diff) | |
| parent | pinctrl: meson-gxbb: Fix wrong pinning definition for uart_c (diff) | |
| download | linux-dev-3c2edc36a77420d8be05d656019dbc8c31535992.tar.xz linux-dev-3c2edc36a77420d8be05d656019dbc8c31535992.zip | |
Merge tag 'pinctrl-v5.4-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl
Pull pin control updates from Linus Walleij:
"This is the bulk of pin control changes for the v5.4 kernel cycle:
Core changes:
- Fix errors in example code in the documentation.
New drivers:
- Add support for JZ4760, JZ4760B, X1000, X1000E and X1500 to the
Ingenic driver.
- Support Cirrus Logic Madera CS47L92 and CS47L15.
- Support Allwinner Sunxi V3S.
- Support Aspeed 2600 BMC.
- Support Qualcomm SC7180.
- Support Marvell MVEBU CS115.
Driver improvements:
- Clean up a few drivers to use the devm_platform_ioremap_resource()
helper.
- Pass the irqchip when registering the gpio_chip in some pin
controllers that are also GPIO controllers.
- Support suspend/resume in the Tegra driver.
- Support pull-up on the Broadcom BCM2711.
- The Intel driver can now request locked pads.
- Fix the UFS reset pin in the Qualcomm SDM845 driver"
* tag 'pinctrl-v5.4-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (112 commits)
pinctrl: meson-gxbb: Fix wrong pinning definition for uart_c
pinctrl: sh-pfc: Unlock on error in sh_pfc_func_set_mux()
pinctrl: bcm: remove redundant assignment to pointer log
pinctrl: iproc: Add 'get_direction' support
pinctrl: iproc-gpio: Handle interrupts for multiple instances
pinctrl: iproc-gpio: Fix incorrect pinconf configurations
pinctrl: intel: mark intel_pin_to_gpio __maybe_unused
pinctrl: qcom: sdm845: Fix UFS_RESET pin
pinctrl: mvebu: add additional variant for standalone CP115
pinctrl: mvebu: Add CP110 missing pin functionality
dt-bindings: cp110: document the new CP115 pinctrl compatible
pinctrl: bcm2835: Pass irqchip when adding gpiochip
pinctrl: meson: meson: Add of_node_put() before return
pinctrl/gpio: Take MUX usage into account
dt-bindings: pinctrl: qcom-pmic-gpio: Add pm8150l support
dt-bindings: pinctrl: qcom-pmic-gpio: Add pm8150b support
dt-bindings: pinctrl: qcom-pmic-gpio: Add pm8150 support
pinctrl: amd: disable spurious-firing GPIO IRQs
pinctrl: rza2: Include the appropriate headers
pinctrl: rza2: Drop driver use of consumer flags
...
96 files changed, 7978 insertions, 2367 deletions
diff --git a/Documentation/devicetree/bindings/arm/marvell/cp110-system-controller.txt b/Documentation/devicetree/bindings/arm/marvell/cp110-system-controller.txt index 4db4119a6d19..f982a8ed9396 100644 --- a/Documentation/devicetree/bindings/arm/marvell/cp110-system-controller.txt +++ b/Documentation/devicetree/bindings/arm/marvell/cp110-system-controller.txt @@ -78,8 +78,8 @@ Documentation/devicetree/bindings/pinctrl/marvell,mvebu-pinctrl.txt. Required properties: -- compatible: "marvell,armada-7k-pinctrl", - "marvell,armada-8k-cpm-pinctrl" or "marvell,armada-8k-cps-pinctrl" +- compatible: "marvell,armada-7k-pinctrl", "marvell,armada-8k-cpm-pinctrl", + "marvell,armada-8k-cps-pinctrl" or "marvell,cp115-standalone-pinctrl" depending on the specific variant of the SoC being used. Available mpp pins/groups and functions: diff --git a/Documentation/devicetree/bindings/mfd/aspeed-scu.txt b/Documentation/devicetree/bindings/mfd/aspeed-scu.txt index ce8cf0ec6279..4d92c0bb6687 100644 --- a/Documentation/devicetree/bindings/mfd/aspeed-scu.txt +++ b/Documentation/devicetree/bindings/mfd/aspeed-scu.txt @@ -4,9 +4,7 @@ configuring elements such as clocks, pinmux, and reset. Required properties: - compatible: One of: "aspeed,ast2400-scu", "syscon", "simple-mfd" - "aspeed,g4-scu", "syscon", "simple-mfd" "aspeed,ast2500-scu", "syscon", "simple-mfd" - "aspeed,g5-scu", "syscon", "simple-mfd" - reg: contains the offset and length of the SCU memory region - #clock-cells: should be set to <1> - the system controller is also a diff --git a/Documentation/devicetree/bindings/misc/aspeed-p2a-ctrl.txt b/Documentation/devicetree/bindings/misc/aspeed-p2a-ctrl.txt index 854bd67ffec6..0e1fa5bc6a30 100644 --- a/Documentation/devicetree/bindings/misc/aspeed-p2a-ctrl.txt +++ b/Documentation/devicetree/bindings/misc/aspeed-p2a-ctrl.txt @@ -26,9 +26,7 @@ property: - compatible : Should be one of the following: "aspeed,ast2400-scu", "syscon", "simple-mfd" - "aspeed,g4-scu", "syscon", "simple-mfd" "aspeed,ast2500-scu", "syscon", "simple-mfd" - "aspeed,g5-scu", "syscon", "simple-mfd" Example =================== diff --git a/Documentation/devicetree/bindings/pinctrl/aspeed,ast2400-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/aspeed,ast2400-pinctrl.yaml index 125599a2dc5e..39ad8657d018 100644 --- a/Documentation/devicetree/bindings/pinctrl/aspeed,ast2400-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/aspeed,ast2400-pinctrl.yaml @@ -15,16 +15,13 @@ description: |+ - compatible: Should be one of the following: "aspeed,ast2400-scu", "syscon", "simple-mfd" - "aspeed,g4-scu", "syscon", "simple-mfd" Refer to the the bindings described in Documentation/devicetree/bindings/mfd/syscon.txt properties: compatible: - enum: - - aspeed,ast2400-pinctrl - - aspeed,g4-pinctrl + const: aspeed,ast2400-pinctrl patternProperties: '^.*$': @@ -35,28 +32,24 @@ patternProperties: "^function|groups$": allOf: - $ref: "/schemas/types.yaml#/definitions/string" - - enum: [ "ACPI", "ADC0", "ADC1", "ADC10", "ADC11", "ADC12", "ADC13", - "ADC14", "ADC15", "ADC2", "ADC3", "ADC4", "ADC5", "ADC6", "ADC7", - "ADC8", "ADC9", "BMCINT", "DDCCLK", "DDCDAT", "EXTRST", "FLACK", - "FLBUSY", "FLWP", "GPID", "GPID0", "GPID2", "GPID4", "GPID6", - "GPIE0", "GPIE2", "GPIE4", "GPIE6", "I2C10", "I2C11", "I2C12", - "I2C13", "I2C14", "I2C3", "I2C4", "I2C5", "I2C6", "I2C7", "I2C8", - "I2C9", "LPCPD", "LPCPME", "LPCRST", "LPCSMI", "MAC1LINK", - "MAC2LINK", "MDIO1", "MDIO2", "NCTS1", "NCTS2", "NCTS3", "NCTS4", - "NDCD1", "NDCD2", "NDCD3", "NDCD4", "NDSR1", "NDSR2", "NDSR3", - "NDSR4", "NDTR1", "NDTR2", "NDTR3", "NDTR4", "NDTS4", "NRI1", - "NRI2", "NRI3", "NRI4", "NRTS1", "NRTS2", "NRTS3", "OSCCLK", - "PWM0", "PWM1", "PWM2", "PWM3", "PWM4", "PWM5", "PWM6", "PWM7", - "RGMII1", "RGMII2", "RMII1", "RMII2", "ROM16", "ROM8", "ROMCS1", - "ROMCS2", "ROMCS3", "ROMCS4", "RXD1", "RXD2", "RXD3", "RXD4", - "SALT1", "SALT2", "SALT3", "SALT4", "SD1", "SD2", "SGPMCK", - "SGPMI", "SGPMLD", "SGPMO", "SGPSCK", "SGPSI0", "SGPSI1", "SGPSLD", - "SIOONCTRL", "SIOPBI", "SIOPBO", "SIOPWREQ", "SIOPWRGD", "SIOS3", - "SIOS5", "SIOSCI", "SPI1", "SPI1DEBUG", "SPI1PASSTHRU", "SPICS1", - "TIMER3", "TIMER4", "TIMER5", "TIMER6", "TIMER7", "TIMER8", "TXD1", - "TXD2", "TXD3", "TXD4", "UART6", "USB11D1", "USB11H2", "USB2D1", - "USB2H1", "USBCKI", "VGABIOS_ROM", "VGAHS", "VGAVS", "VPI18", - "VPI24", "VPI30", "VPO12", "VPO24", "WDTRST1", "WDTRST2" ] + - enum: [ ACPI, ADC0, ADC1, ADC10, ADC11, ADC12, ADC13, ADC14, + ADC15, ADC2, ADC3, ADC4, ADC5, ADC6, ADC7, ADC8, ADC9, BMCINT, + DDCCLK, DDCDAT, EXTRST, FLACK, FLBUSY, FLWP, GPID, GPID0, GPID2, + GPID4, GPID6, GPIE0, GPIE2, GPIE4, GPIE6, I2C10, I2C11, I2C12, + I2C13, I2C14, I2C3, I2C4, I2C5, I2C6, I2C7, I2C8, I2C9, LPCPD, + LPCPME, LPCRST, LPCSMI, MAC1LINK, MAC2LINK, MDIO1, MDIO2, NCTS1, + NCTS2, NCTS3, NCTS4, NDCD1, NDCD2, NDCD3, NDCD4, NDSR1, NDSR2, + NDSR3, NDSR4, NDTR1, NDTR2, NDTR3, NDTR4, NDTS4, NRI1, NRI2, + NRI3, NRI4, NRTS1, NRTS2, NRTS3, OSCCLK, PWM0, PWM1, PWM2, PWM3, + PWM4, PWM5, PWM6, PWM7, RGMII1, RGMII2, RMII1, RMII2, ROM16, + ROM8, ROMCS1, ROMCS2, ROMCS3, ROMCS4, RXD1, RXD2, RXD3, RXD4, + SALT1, SALT2, SALT3, SALT4, SD1, SD2, SGPMCK, SGPMI, SGPMLD, + SGPMO, SGPSCK, SGPSI0, SGPSI1, SGPSLD, SIOONCTRL, SIOPBI, SIOPBO, + SIOPWREQ, SIOPWRGD, SIOS3, SIOS5, SIOSCI, SPI1, SPI1DEBUG, + SPI1PASSTHRU, SPICS1, TIMER3, TIMER4, TIMER5, TIMER6, TIMER7, + TIMER8, TXD1, TXD2, TXD3, TXD4, UART6, USB11D1, USB11H2, USB2D1, + USB2H1, USBCKI, VGABIOS_ROM, VGAHS, VGAVS, VPI18, VPI24, VPI30, + VPO12, VPO24, WDTRST1, WDTRST2 ] required: - compatible diff --git a/Documentation/devicetree/bindings/pinctrl/aspeed,ast2500-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/aspeed,ast2500-pinctrl.yaml index 3e6d85318577..3c6405be07ed 100644 --- a/Documentation/devicetree/bindings/pinctrl/aspeed,ast2500-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/aspeed,ast2500-pinctrl.yaml @@ -22,9 +22,7 @@ description: |+ properties: compatible: - enum: - - aspeed,ast2500-pinctrl - - aspeed,g5-pinctrl + const: aspeed,ast2500-pinctrl aspeed,external-nodes: minItems: 2 maxItems: 2 @@ -44,31 +42,26 @@ patternProperties: "^function|groups$": allOf: - $ref: "/schemas/types.yaml#/definitions/string" - - enum: [ "ACPI", "ADC0", "ADC1", "ADC10", "ADC11", "ADC12", "ADC13", - "ADC14", "ADC15", "ADC2", "ADC3", "ADC4", "ADC5", "ADC6", "ADC7", - "ADC8", "ADC9", "BMCINT", "DDCCLK", "DDCDAT", "ESPI", "FWSPICS1", - "FWSPICS2", "GPID0", "GPID2", "GPID4", "GPID6", "GPIE0", "GPIE2", - "GPIE4", "GPIE6", "I2C10", "I2C11", "I2C12", "I2C13", "I2C14", - "I2C3", "I2C4", "I2C5", "I2C6", "I2C7", "I2C8", "I2C9", "LAD0", - "LAD1", "LAD2", "LAD3", "LCLK", "LFRAME", "LPCHC", "LPCPD", - "LPCPLUS", "LPCPME", "LPCRST", "LPCSMI", "LSIRQ", "MAC1LINK", - "MAC2LINK", "MDIO1", "MDIO2", "NCTS1", "NCTS2", "NCTS3", "NCTS4", - "NDCD1", "NDCD2", "NDCD3", "NDCD4", "NDSR1", "NDSR2", "NDSR3", - "NDSR4", "NDTR1", "NDTR2", "NDTR3", "NDTR4", "NRI1", "NRI2", - "NRI3", "NRI4", "NRTS1", "NRTS2", "NRTS3", "NRTS4", "OSCCLK", - "PEWAKE", "PNOR", "PWM0", "PWM1", "PWM2", "PWM3", "PWM4", "PWM5", - "PWM6", "PWM7", "RGMII1", "RGMII2", "RMII1", "RMII2", "RXD1", - "RXD2", "RXD3", "RXD4", "SALT1", "SALT10", "SALT11", "SALT12", - "SALT13", "SALT14", "SALT2", "SALT3", "SALT4", "SALT5", "SALT6", - "SALT7", "SALT8", "SALT9", "SCL1", "SCL2", "SD1", "SD2", "SDA1", - "SDA2", "SGPS1", "SGPS2", "SIOONCTRL", "SIOPBI", "SIOPBO", - "SIOPWREQ", "SIOPWRGD", "SIOS3", "SIOS5", "SIOSCI", "SPI1", - "SPI1CS1", "SPI1DEBUG", "SPI1PASSTHRU", "SPI2CK", "SPI2CS0", - "SPI2CS1", "SPI2MISO", "SPI2MOSI", "TIMER3", "TIMER4", "TIMER5", - "TIMER6", "TIMER7", "TIMER8", "TXD1", "TXD2", "TXD3", "TXD4", - "UART6", "USB11BHID", "USB2AD", "USB2AH", "USB2BD", "USB2BH", - "USBCKI", "VGABIOSROM", "VGAHS", "VGAVS", "VPI24", "VPO", - "WDTRST1", "WDTRST2", ] + - enum: [ ACPI, ADC0, ADC1, ADC10, ADC11, ADC12, ADC13, ADC14, + ADC15, ADC2, ADC3, ADC4, ADC5, ADC6, ADC7, ADC8, ADC9, BMCINT, + DDCCLK, DDCDAT, ESPI, FWSPICS1, FWSPICS2, GPID0, GPID2, GPID4, + GPID6, GPIE0, GPIE2, GPIE4, GPIE6, I2C10, I2C11, I2C12, I2C13, + I2C14, I2C3, I2C4, I2C5, I2C6, I2C7, I2C8, I2C9, LAD0, LAD1, + LAD2, LAD3, LCLK, LFRAME, LPCHC, LPCPD, LPCPLUS, LPCPME, LPCRST, + LPCSMI, LSIRQ, MAC1LINK, MAC2LINK, MDIO1, MDIO2, NCTS1, NCTS2, + NCTS3, NCTS4, NDCD1, NDCD2, NDCD3, NDCD4, NDSR1, NDSR2, NDSR3, + NDSR4, NDTR1, NDTR2, NDTR3, NDTR4, NRI1, NRI2, NRI3, NRI4, NRTS1, + NRTS2, NRTS3, NRTS4, OSCCLK, PEWAKE, PNOR, PWM0, PWM1, PWM2, + PWM3, PWM4, PWM5, PWM6, PWM7, RGMII1, RGMII2, RMII1, RMII2, RXD1, + RXD2, RXD3, RXD4, SALT1, SALT10, SALT11, SALT12, SALT13, SALT14, + SALT2, SALT3, SALT4, SALT5, SALT6, SALT7, SALT8, SALT9, SCL1, + SCL2, SD1, SD2, SDA1, SDA2, SGPS1, SGPS2, SIOONCTRL, SIOPBI, + SIOPBO, SIOPWREQ, SIOPWRGD, SIOS3, SIOS5, SIOSCI, SPI1, SPI1CS1, + SPI1DEBUG, SPI1PASSTHRU, SPI2CK, SPI2CS0, SPI2CS1, SPI2MISO, + SPI2MOSI, TIMER3, TIMER4, TIMER5, TIMER6, TIMER7, TIMER8, TXD1, + TXD2, TXD3, TXD4, UART6, USB11BHID, USB2AD, USB2AH, USB2BD, + USB2BH, USBCKI, VGABIOSROM, VGAHS, VGAVS, VPI24, VPO, WDTRST1, + WDTRST2, ] required: - compatible diff --git a/Documentation/devicetree/bindings/pinctrl/aspeed,ast2600-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/aspeed,ast2600-pinctrl.yaml new file mode 100644 index 000000000000..f83d888176cc --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/aspeed,ast2600-pinctrl.yaml @@ -0,0 +1,115 @@ +# SPDX-License-Identifier: GPL-2.0+ +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/aspeed,ast2600-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ASPEED AST2600 Pin Controller + +maintainers: + - Andrew Jeffery <andrew@aj.id.au> + +description: |+ + The pin controller node should be the child of a syscon node with the + required property: + + - compatible: Should be one of the following: + "aspeed,ast2600-scu", "syscon", "simple-mfd" + + Refer to the the bindings described in + Documentation/devicetree/bindings/mfd/syscon.txt + +properties: + compatible: + const: aspeed,ast2600-pinctrl + +patternProperties: + '^.*$': + if: + type: object + then: + properties: + function: + allOf: + - $ref: "/schemas/types.yaml#/definitions/string" + - enum: [ ADC0, ADC1, ADC10, ADC11, ADC12, ADC13, ADC14, ADC15, + ADC2, ADC3, ADC4, ADC5, ADC6, ADC7, ADC8, ADC9, BMCINT, ESPI, + ESPIALT, FSI1, FSI2, FWSPIABR, FWSPID, FWSPIWP, GPIT0, GPIT1, + GPIT2, GPIT3, GPIT4, GPIT5, GPIT6, GPIT7, GPIU0, GPIU1, GPIU2, + GPIU3, GPIU4, GPIU5, GPIU6, GPIU7, I2C1, I2C10, I2C11, I2C12, + I2C13, I2C14, I2C15, I2C16, I2C2, I2C3, I2C4, I2C5, I2C6, I2C7, + I2C8, I2C9, I3C3, I3C4, I3C5, I3C6, JTAGM, LHPD, LHSIRQ, LPC, + LPCHC, LPCPD, LPCPME, LPCSMI, LSIRQ, MACLINK1, MACLINK2, + MACLINK3, MACLINK4, MDIO1, MDIO2, MDIO3, MDIO4, NCTS1, NCTS2, + NCTS3, NCTS4, NDCD1, NDCD2, NDCD3, NDCD4, NDSR1, NDSR2, NDSR3, + NDSR4, NDTR1, NDTR2, NDTR3, NDTR4, NRI1, NRI2, NRI3, NRI4, NRTS1, + NRTS2, NRTS3, NRTS4, OSCCLK, PEWAKE, PWM0, PWM1, PWM10, PWM11, + PWM12, PWM13, PWM14, PWM15, PWM2, PWM3, PWM4, PWM5, PWM6, PWM7, + PWM8, PWM9, RGMII1, RGMII2, RGMII3, RGMII4, RMII1, RMII2, RMII3, + RMII4, RXD1, RXD2, RXD3, RXD4, SALT1, SALT10, SALT11, SALT12, + SALT13, SALT14, SALT15, SALT16, SALT2, SALT3, SALT4, SALT5, + SALT6, SALT7, SALT8, SALT9, SD1, SD2, SD3, SD3DAT4, SD3DAT5, + SD3DAT6, SD3DAT7, SGPM1, SGPS1, SIOONCTRL, SIOPBI, SIOPBO, + SIOPWREQ, SIOPWRGD, SIOS3, SIOS5, SIOSCI, SPI1, SPI1ABR, SPI1CS1, + SPI1WP, SPI2, SPI2CS1, SPI2CS2, TACH0, TACH1, TACH10, TACH11, + TACH12, TACH13, TACH14, TACH15, TACH2, TACH3, TACH4, TACH5, + TACH6, TACH7, TACH8, TACH9, THRU0, THRU1, THRU2, THRU3, TXD1, + TXD2, TXD3, TXD4, UART10, UART11, UART12, UART13, UART6, UART7, + UART8, UART9, VB, VGAHS, VGAVS, WDTRST1, WDTRST2, WDTRST3, + WDTRST4, ] + groups: + allOf: + - $ref: "/schemas/types.yaml#/definitions/string" + - enum: [ ADC0, ADC1, ADC10, ADC11, ADC12, ADC13, ADC14, ADC15, + ADC2, ADC3, ADC4, ADC5, ADC6, ADC7, ADC8, ADC9, BMCINT, ESPI, + ESPIALT, FSI1, FSI2, FWSPIABR, FWSPID, FWQSPID, FWSPIWP, GPIT0, + GPIT1, GPIT2, GPIT3, GPIT4, GPIT5, GPIT6, GPIT7, GPIU0, GPIU1, + GPIU2, GPIU3, GPIU4, GPIU5, GPIU6, GPIU7, HVI3C3, HVI3C4, I2C1, + I2C10, I2C11, I2C12, I2C13, I2C14, I2C15, I2C16, I2C2, I2C3, + I2C4, I2C5, I2C6, I2C7, I2C8, I2C9, I3C3, I3C4, I3C5, I3C6, + JTAGM, LHPD, LHSIRQ, LPC, LPCHC, LPCPD, LPCPME, LPCSMI, LSIRQ, + MACLINK1, MACLINK2, MACLINK3, MACLINK4, MDIO1, MDIO2, MDIO3, + MDIO4, NCTS1, NCTS2, NCTS3, NCTS4, NDCD1, NDCD2, NDCD3, NDCD4, + NDSR1, NDSR2, NDSR3, NDSR4, NDTR1, NDTR2, NDTR3, NDTR4, NRI1, + NRI2, NRI3, NRI4, NRTS1, NRTS2, NRTS3, NRTS4, OSCCLK, PEWAKE, + PWM0, PWM1, PWM10G0, PWM10G1, PWM11G0, PWM11G1, PWM12G0, PWM12G1, + PWM13G0, PWM13G1, PWM14G0, PWM14G1, PWM15G0, PWM15G1, PWM2, PWM3, + PWM4, PWM5, PWM6, PWM7, PWM8G0, PWM8G1, PWM9G0, PWM9G1, QSPI1, + QSPI2, RGMII1, RGMII2, RGMII3, RGMII4, RMII1, RMII2, RMII3, + RMII4, RXD1, RXD2, RXD3, RXD4, SALT1, SALT10G0, SALT10G1, + SALT11G0, SALT11G1, SALT12G0, SALT12G1, SALT13G0, SALT13G1, + SALT14G0, SALT14G1, SALT15G0, SALT15G1, SALT16G0, SALT16G1, + SALT2, SALT3, SALT4, SALT5, SALT6, SALT7, SALT8, SALT9G0, + SALT9G1, SD1, SD2, SD3, SD3DAT4, SD3DAT5, SD3DAT6, SD3DAT7, + SGPM1, SGPS1, SIOONCTRL, SIOPBI, SIOPBO, SIOPWREQ, SIOPWRGD, + SIOS3, SIOS5, SIOSCI, SPI1, SPI1ABR, SPI1CS1, SPI1WP, SPI2, + SPI2CS1, SPI2CS2, TACH0, TACH1, TACH10, TACH11, TACH12, TACH13, + TACH14, TACH15, TACH2, TACH3, TACH4, TACH5, TACH6, TACH7, TACH8, + TACH9, THRU0, THRU1, THRU2, THRU3, TXD1, TXD2, TXD3, TXD4, + UART10, UART11, UART12G0, UART12G1, UART13G0, UART13G1, UART6, + UART7, UART8, UART9, VB, VGAHS, VGAVS, WDTRST1, WDTRST2, WDTRST3, + WDTRST4, ] + +required: + - compatible + +examples: + - | + syscon: scu@1e6e2000 { + compatible = "aspeed,ast2600-scu", "syscon", "simple-mfd"; + reg = <0x1e6e2000 0xf6c>; + + pinctrl: pinctrl { + compatible = "aspeed,g6-pinctrl"; + + pinctrl_pwm10g1_default: pwm10g1_default { + function = "PWM10"; + groups = "PWM10G1"; + }; + + pinctrl_gpioh0_unbiased_default: gpioh0 { + pins = "A18"; + bias-disable; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/brcm,bcm2835-gpio.txt b/Documentation/devicetree/bindings/pinctrl/brcm,bcm2835-gpio.txt index ac6d614d74e0..3cab7336a326 100644 --- a/Documentation/devicetree/bindings/pinctrl/brcm,bcm2835-gpio.txt +++ b/Documentation/devicetree/bindings/pinctrl/brcm,bcm2835-gpio.txt @@ -8,6 +8,7 @@ Required properties: - compatible: should be one of: "brcm,bcm2835-gpio" - BCM2835 compatible pinctrl "brcm,bcm7211-gpio" - BCM7211 compatible pinctrl + "brcm,bcm2711-gpio" - BCM2711 compatible pinctrl - reg: Should contain the physical address of the GPIO module's registers. - gpio-controller: Marks the device node as a GPIO controller. - #gpio-cells : Should be two. The first cell is the pin number and the diff --git a/Documentation/devicetree/bindings/pinctrl/ingenic,pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/ingenic,pinctrl.txt index af20b0ec715c..0014d9899797 100644 --- a/Documentation/devicetree/bindings/pinctrl/ingenic,pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/ingenic,pinctrl.txt @@ -1,18 +1,18 @@ -Ingenic jz47xx pin controller +Ingenic XBurst pin controller Please refer to pinctrl-bindings.txt in this directory for details of the common pinctrl bindings used by client devices, including the meaning of the phrase "pin configuration node". -For the jz47xx SoCs, pin control is tightly bound with GPIO ports. All pins may +For the XBurst SoCs, pin control is tightly bound with GPIO ports. All pins may be used as GPIOs, multiplexed device functions are configured within the GPIO port configuration registers and it is typical to refer to pins using the naming scheme "PxN" where x is a character identifying the GPIO port with which the pin is associated and N is an integer from 0 to 31 identifying the pin within that GPIO port. For example PA0 is the first pin in GPIO port A, and -PB31 is the last pin in GPIO port B. The jz4740 contains 4 GPIO ports, PA to -PD, for a total of 128 pins. The jz4780 contains 6 GPIO ports, PA to PF, for a -total of 192 pins. +PB31 is the last pin in GPIO port B. The jz4740 and the x1000 contains 4 GPIO +ports, PA to PD, for a total of 128 pins. The jz4760, the jz4770 and the jz4780 +contains 6 GPIO ports, PA to PF, for a total of 192 pins. Required properties: @@ -21,8 +21,13 @@ Required properties: - compatible: One of: - "ingenic,jz4740-pinctrl" - "ingenic,jz4725b-pinctrl" + - "ingenic,jz4760-pinctrl" + - "ingenic,jz4760b-pinctrl" - "ingenic,jz4770-pinctrl" - "ingenic,jz4780-pinctrl" + - "ingenic,x1000-pinctrl" + - "ingenic,x1000e-pinctrl" + - "ingenic,x1500-pinctrl" - reg: Address range of the pinctrl registers. @@ -31,8 +36,10 @@ Required properties for sub-nodes (GPIO chips): - compatible: Must contain one of: - "ingenic,jz4740-gpio" + - "ingenic,jz4760-gpio" - "ingenic,jz4770-gpio" - "ingenic,jz4780-gpio" + - "ingenic,x1000-gpio" - reg: The GPIO bank number. - interrupt-controller: Marks the device node as an interrupt controller. - interrupts: Interrupt specifier for the controllers interrupt. diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,msm8998-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/qcom,msm8998-pinctrl.txt index cdec1eeb2799..c4de930f2406 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,msm8998-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/qcom,msm8998-pinctrl.txt @@ -132,9 +132,8 @@ to specify in a pin configuration subnode: qlink_request, qua_mi2s, sd_card, sd_write, sdc40, sdc41, sdc42, sdc43, sdc4_clk, sdc4_cmd, sec_mi2s, sp_cmu, spkr_i2s, ssbi1, ssc_irq, ter_mi2s, tgu_ch0, tgu_ch1, - tsense_pwm1, tsense_pwm2, tsif1_clk, tsif1_data, tsif1_en, - tsif1_error, tsif1_sync, tsif2_clk, tsif2_data, tsif2_en, - tsif2_error, tsif2_sync, uim1_clk, uim1_data, uim1_present, + tsense_pwm1, tsense_pwm2, tsif0, tsif1, + uim1_clk, uim1_data, uim1_present, uim1_reset, uim2_clk, uim2_data, uim2_present, uim2_reset, uim_batt, usb_phy, vfr_1, vsense_clkout, vsense_data0, vsense_data1, vsense_mode, wlan1_adc0, wlan1_adc1, diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.txt b/Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.txt index 7f64a7e92c28..c32bf3237545 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.txt +++ b/Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.txt @@ -21,6 +21,8 @@ PMIC's from Qualcomm. "qcom,pmi8994-gpio" "qcom,pmi8998-gpio" "qcom,pms405-gpio" + "qcom,pm8150-gpio" + "qcom,pm8150b-gpio" And must contain either "qcom,spmi-gpio" or "qcom,ssbi-gpio" if the device is on an spmi bus or an ssbi bus respectively @@ -94,6 +96,10 @@ to specify in a pin configuration subnode: gpio1-gpio22 for pma8084 gpio1-gpio10 for pmi8994 gpio1-gpio12 for pms405 (holes on gpio1, gpio9 and gpio10) + gpio1-gpio10 for pm8150 (holes on gpio2, gpio5, gpio7 + and gpio8) + gpio1-gpio12 for pm8150b (holes on gpio3, gpio4, gpio7) + gpio1-gpio12 for pm8150l (hole on gpio7) - function: Usage: required diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sc7180-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/qcom,sc7180-pinctrl.txt new file mode 100644 index 000000000000..b5767ee82ee6 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/qcom,sc7180-pinctrl.txt @@ -0,0 +1,186 @@ +Qualcomm Technologies, Inc. SC7180 TLMM block + +This binding describes the Top Level Mode Multiplexer block found in the +SC7180 platform. + +- compatible: + Usage: required + Value type: <string> + Definition: must be "qcom,sc7180-pinctrl" + +- reg: + Usage: required + Value type: <prop-encoded-array> + Definition: the base address and size of the north, south and west + TLMM tiles + +- reg-names: + Usage: required + Value type: <prop-encoded-array> + Definition: names for the cells of reg, must contain "north", "south" + and "west". + +- interrupts: + Usage: required + Value type: <prop-encoded-array> + Definition: should specify the TLMM summary IRQ. + +- interrupt-controller: + Usage: required + Value type: <none> + Definition: identifies this node as an interrupt controller + +- #interrupt-cells: + Usage: required + Value type: <u32> + Definition: must be 2. Specifying the pin number and flags, as defined + in <dt-bindings/interrupt-controller/irq.h> + +- gpio-controller: + Usage: required + Value type: <none> + Definition: identifies this node as a gpio controller + +- #gpio-cells: + Usage: required + Value type: <u32> + Definition: must be 2. Specifying the pin number and flags, as defined + in <dt-bindings/gpio/gpio.h> + +- gpio-ranges: + Usage: required + Value type: <prop-encoded-array> + Definition: see ../gpio/gpio.txt + +- gpio-reserved-ranges: + Usage: optional + Value type: <prop-encoded-array> + Definition: see ../gpio/gpio.txt + +Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for +a general description of GPIO and interrupt bindings. + +Please refer to pinctrl-bindings.txt in this directory for details of the +common pinctrl bindings used by client devices, including the meaning of the +phrase "pin configuration node". + +The pin configuration nodes act as a container for an arbitrary number of +subnodes. Each of these subnodes represents some desired configuration for a +pin, a group, or a list of pins or groups. This configuration can include the +mux function to select on those pin(s)/group(s), and various pin configuration +parameters, such as pull-up, drive strength, etc. + + +PIN CONFIGURATION NODES: + +The name of each subnode is not important; all subnodes should be enumerated +and processed purely based on their content. + +Each subnode only affects those parameters that are explicitly listed. In +other words, a subnode that lists a mux function but no pin configuration +parameters implies no information about any pin configuration parameters. +Similarly, a pin subnode that describes a pullup parameter implies no +information about e.g. the mux function. + + +The following generic properties as defined in pinctrl-bindings.txt are valid +to specify in a pin configuration subnode: + +- pins: + Usage: required + Value type: <string-array> + Definition: List of gpio pins affected by the properties specified in + this subnode. + + Valid pins are: + gpio0-gpio118 + Supports mux, bias and drive-strength + + sdc1_clk, sdc1_cmd, sdc1_data sdc2_clk, sdc2_cmd, + sdc2_data sdc1_rclk + Supports bias and drive-strength + + ufs_reset + Supports bias and drive-strength + +- function: + Usage: required + Value type: <string> + Definition: Specify the alternative function to be configured for the + specified pins. Functions are only valid for gpio pins. + Valid values are: + + adsp_ext, agera_pll, aoss_cti, atest_char, atest_char0, + atest_char1, atest_char2, atest_char3, atest_tsens, + atest_tsens2, atest_usb1, atest_usb10, atest_usb11, + atest_usb12, atest_usb13, atest_usb2, atest_usb20, + atest_usb21, atest_usb22, atest_usb23, audio_ref, + btfm_slimbus, cam_mclk, cci_async, cci_i2c, cci_timer0, + cci_timer1, cci_timer2, cci_timer3, cci_timer4, + cri_trng, dbg_out, ddr_bist, ddr_pxi0, ddr_pxi1, + ddr_pxi2, ddr_pxi3, dp_hot, edp_lcd, gcc_gp1, gcc_gp2, + gcc_gp3, gpio, gp_pdm0, gp_pdm1, gp_pdm2, gps_tx, + jitter_bist, ldo_en, ldo_update, lpass_ext, mdp_vsync, + mdp_vsync0, mdp_vsync1, mdp_vsync2, mdp_vsync3, mi2s_0, + mi2s_1, mi2s_2, mss_lte, m_voc, pa_indicator, phase_flag, + PLL_BIST, pll_bypassnl, pll_reset, prng_rosc, qdss, + qdss_cti, qlink_enable, qlink_request, qspi_clk, qspi_cs, + qspi_data, qup00, qup01, qup02, qup03, qup04, qup05, + qup10, qup11, qup12, qup13, qup14, qup15, sdc1_tb, + sdc2_tb, sd_write, sp_cmu, tgu_ch0, tgu_ch1, tgu_ch2, + tgu_ch3, tsense_pwm1, tsense_pwm2, uim1, uim2, uim_batt, + usb_phy, vfr_1, _V_GPIO, _V_PPS_IN, _V_PPS_OUT, + vsense_trigger, wlan1_adc0, wlan1_adc1, wlan2_adc0, + wlan2_adc1, + +- bias-disable: + Usage: optional + Value type: <none> + Definition: The specified pins should be configured as no pull. + +- bias-pull-down: + Usage: optional + Value type: <none> + Definition: The specified pins should be configured as pull down. + +- bias-pull-up: + Usage: optional + Value type: <none> + Definition: The specified pins should be configured as pull up. + +- output-high: + Usage: optional + Value type: <none> + Definition: The specified pins are configured in output mode, driven + high. + Not valid for sdc pins. + +- output-low: + Usage: optional + Value type: <none> + Definition: The specified pins are configured in output mode, driven + low. + Not valid for sdc pins. + +- drive-strength: + Usage: optional + Value type: <u32> + Definition: Selects the drive strength for the specified pins, in mA. + Valid values are: 2, 4, 6, 8, 10, 12, 14 and 16 + +Example: + + tlmm: pinctrl@3500000 { + compatible = "qcom,sc7180-pinctrl"; + reg = <0x3500000 0x300000>, + <0x3900000 0x300000>, + <0x3D00000 0x300000>; + reg-names = "west", "north", "south"; + interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&tlmm 0 0 119>; + gpio-reserved-ranges = <0 4>, <106 4>; + interrupt-controller; + #interrupt-cells = <2>; + }; diff --git a/Documentation/driver-api/pinctl.rst b/Documentation/driver-api/pinctl.rst index 2bb1bc484278..3d2deaf48841 100644 --- a/Documentation/driver-api/pinctl.rst +++ b/Documentation/driver-api/pinctl.rst @@ -638,8 +638,8 @@ group of pins would work something like this:: } static int foo_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector, - unsigned ** const pins, - unsigned * const num_pins) + const unsigned ** pins, + unsigned * num_pins) { *pins = (unsigned *) foo_groups[selector].pins; *num_pins = foo_groups[selector].num_pins; @@ -705,7 +705,7 @@ group of pins would work something like this:: { u8 regbit = (1 << selector + group); - writeb((readb(MUX)|regbit), MUX) + writeb((readb(MUX)|regbit), MUX); return 0; } diff --git a/drivers/gpio/gpiolib.c b/drivers/gpio/gpiolib.c index 822988818efc..bdbc1649eafa 100644 --- a/drivers/gpio/gpiolib.c +++ b/drivers/gpio/gpiolib.c @@ -1084,7 +1084,8 @@ static long gpio_ioctl(struct file *filp, unsigned int cmd, unsigned long arg) test_bit(FLAG_IS_HOGGED, &desc->flags) || test_bit(FLAG_USED_AS_IRQ, &desc->flags) || test_bit(FLAG_EXPORT, &desc->flags) || - test_bit(FLAG_SYSFS, &desc->flags)) + test_bit(FLAG_SYSFS, &desc->flags) || + !pinctrl_gpio_can_use_line(chip->base + lineinfo.line_offset)) lineinfo.flags |= GPIOLINE_FLAG_KERNEL; if (test_bit(FLAG_IS_OUT, &desc->flags)) lineinfo.flags |= GPIOLINE_FLAG_IS_OUT; diff --git a/drivers/pinctrl/aspeed/Kconfig b/drivers/pinctrl/aspeed/Kconfig index 4cf54172f8fb..de8b185c4fee 100644 --- a/drivers/pinctrl/aspeed/Kconfig +++ b/drivers/pinctrl/aspeed/Kconfig @@ -23,3 +23,11 @@ config PINCTRL_ASPEED_G5 help Say Y here to enable pin controller support for Aspeed's 5th generation SoCs. GPIO is provided by a separate GPIO driver. + +config PINCTRL_ASPEED_G6 + bool "Aspeed G6 SoC pin control" + depends on (MACH_ASPEED_G6 || COMPILE_TEST) && OF + select PINCTRL_ASPEED + help + Say Y here to enable pin controller support for Aspeed's 6th + generation SoCs. GPIO is provided by a separate GPIO driver. diff --git a/drivers/pinctrl/aspeed/Makefile b/drivers/pinctrl/aspeed/Makefile index ea8962645e49..489ea1778353 100644 --- a/drivers/pinctrl/aspeed/Makefile +++ b/drivers/pinctrl/aspeed/Makefile @@ -5,3 +5,4 @@ ccflags-y += $(call cc-option,-Woverride-init) obj-$(CONFIG_PINCTRL_ASPEED) += pinctrl-aspeed.o pinmux-aspeed.o obj-$(CONFIG_PINCTRL_ASPEED_G4) += pinctrl-aspeed-g4.o obj-$(CONFIG_PINCTRL_ASPEED_G5) += pinctrl-aspeed-g5.o +obj-$(CONFIG_PINCTRL_ASPEED_G6) += pinctrl-aspeed-g6.o diff --git a/drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c b/drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c index 22256576b69a..95ea593fa29d 100644 --- a/drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c +++ b/drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c @@ -21,6 +21,13 @@ #include "pinmux-aspeed.h" #include "pinctrl-aspeed.h" +/* Wrap some of the common macros for clarity */ +#define SIG_EXPR_DECL_SINGLE(sig, func, ...) \ + SIG_EXPR_DECL(sig, func, func, __VA_ARGS__) + +#define SIG_EXPR_LIST_DECL_SINGLE SIG_EXPR_LIST_DECL_SESG +#define SIG_EXPR_LIST_DECL_DUAL SIG_EXPR_LIST_DECL_DESG + /* * The "Multi-function Pins Mapping and Control" table in the SoC datasheet * references registers by the device/offset mnemonic. The register macros @@ -80,16 +87,16 @@ SSSF_PIN_DECL(E6, GPIOA3, TIMER4, SIG_DESC_SET(SCU80, 3)); #define I2C9_DESC SIG_DESC_SET(SCU90, 22) #define C5 4 -SIG_EXPR_LIST_DECL_SINGLE(SCL9, I2C9, I2C9_DESC); -SIG_EXPR_LIST_DECL_SINGLE(TIMER5, TIMER5, SIG_DESC_SET(SCU80, 4)); -MS_PIN_DECL(C5, GPIOA4, SCL9, TIMER5); +SIG_EXPR_LIST_DECL_SINGLE(C5, SCL9, I2C9, I2C9_DESC); +SIG_EXPR_LIST_DECL_SINGLE(C5, TIMER5, TIMER5, SIG_DESC_SET(SCU80, 4)); +PIN_DECL_2(C5, GPIOA4, SCL9, TIMER5); FUNC_GROUP_DECL(TIMER5, C5); #define B4 5 -SIG_EXPR_LIST_DECL_SINGLE(SDA9, I2C9, I2C9_DESC); -SIG_EXPR_LIST_DECL_SINGLE(TIMER6, TIMER6, SIG_DESC_SET(SCU80, 5)); -MS_PIN_DECL(B4, GPIOA5, SDA9, TIMER6); +SIG_EXPR_LIST_DECL_SINGLE(B4, SDA9, I2C9, I2C9_DESC); +SIG_EXPR_LIST_DECL_SINGLE(B4, TIMER6, TIMER6, SIG_DESC_SET(SCU80, 5)); +PIN_DECL_2(B4, GPIOA5, SDA9, TIMER6); FUNC_GROUP_DECL(TIMER6, B4); FUNC_GROUP_DECL(I2C9, C5, B4); @@ -97,16 +104,16 @@ FUNC_GROUP_DECL(I2C9, C5, B4); #define MDIO2_DESC SIG_DESC_SET(SCU90, 2) #define A3 6 -SIG_EXPR_LIST_DECL_SINGLE(MDC2, MDIO2, MDIO2_DESC); -SIG_EXPR_LIST_DECL_SINGLE(TIMER7, TIMER7, SIG_DESC_SET(SCU80, 6)); -MS_PIN_DECL(A3, GPIOA6, MDC2, TIMER7); +SIG_EXPR_LIST_DECL_SINGLE(A3, MDC2, MDIO2, MDIO2_DESC); +SIG_EXPR_LIST_DECL_SINGLE(A3, TIMER7, TIMER7, SIG_DESC_SET(SCU80, 6)); +PIN_DECL_2(A3, GPIOA6, MDC2, TIMER7); FUNC_GROUP_DECL(TIMER7, A3); #define D5 7 -SIG_EXPR_LIST_DECL_SINGLE(MDIO2, MDIO2, MDIO2_DESC); -SIG_EXPR_LIST_DECL_SINGLE(TIMER8, TIMER8, SIG_DESC_SET(SCU80, 7)); -MS_PIN_DECL(D5, GPIOA7, MDIO2, TIMER8); +SIG_EXPR_LIST_DECL_SINGLE(D5, MDIO2, MDIO2, MDIO2_DESC); +SIG_EXPR_LIST_DECL_SINGLE(D5, TIMER8, TIMER8, SIG_DESC_SET(SCU80, 7)); +PIN_DECL_2(D5, GPIOA7, MDIO2, TIMER8); FUNC_GROUP_DECL(TIMER8, D5); FUNC_GROUP_DECL(MDIO2, A3, D5); @@ -124,18 +131,18 @@ SSSF_PIN_DECL(H18, GPIOB2, SALT3, SIG_DESC_SET(SCU80, 10)); SSSF_PIN_DECL(F18, GPIOB3, SALT4, SIG_DESC_SET(SCU80, 11)); #define E19 12 -SIG_EXPR_DECL(LPCRST, LPCRST, SIG_DESC_SET(SCU80, 12)); -SIG_EXPR_DECL(LPCRST, LPCRSTS, SIG_DESC_SET(HW_STRAP1, 14)); -SIG_EXPR_LIST_DECL_DUAL(LPCRST, LPCRST, LPCRSTS); -SS_PIN_DECL(E19, GPIOB4, LPCRST); +SIG_EXPR_DECL_SINGLE(LPCRST, LPCRST, SIG_DESC_SET(SCU80, 12)); +SIG_EXPR_DECL_SINGLE(LPCRST, LPCRSTS, SIG_DESC_SET(HW_STRAP1, 14)); +SIG_EXPR_LIST_DECL_DUAL(E19, LPCRST, LPCRST, LPCRSTS); +PIN_DECL_1(E19, GPIOB4, LPCRST); FUNC_GROUP_DECL(LPCRST, E19); #define H19 13 #define H19_DESC SIG_DESC_SET(SCU80, 13) -SIG_EXPR_LIST_DECL_SINGLE(LPCPD, LPCPD, H19_DESC); -SIG_EXPR_LIST_DECL_SINGLE(LPCSMI, LPCSMI, H19_DESC); -MS_PIN_DECL(H19, GPIOB5, LPCPD, LPCSMI); +SIG_EXPR_LIST_DECL_SINGLE(H19, LPCPD, LPCPD, H19_DESC); +SIG_EXPR_LIST_DECL_SINGLE(H19, LPCSMI, LPCSMI, H19_DESC); +PIN_DECL_2(H19, GPIOB5, LPCPD, LPCSMI); FUNC_GROUP_DECL(LPCPD, H19); FUNC_GROUP_DECL(LPCSMI, H19); @@ -144,14 +151,14 @@ FUNC_GROUP_DECL(LPCSMI, H19); SSSF_PIN_DECL(H20, GPIOB6, LPCPME, SIG_DESC_SET(SCU80, 14)); #define E18 15 -SIG_EXPR_LIST_DECL_SINGLE(EXTRST, EXTRST, +SIG_EXPR_LIST_DECL_SINGLE(E18, EXTRST, EXTRST, SIG_DESC_SET(SCU80, 15), SIG_DESC_BIT(SCU90, 31, 0), SIG_DESC_SET(SCU3C, 3)); -SIG_EXPR_LIST_DECL_SINGLE(SPICS1, SPICS1, +SIG_EXPR_LIST_DECL_SINGLE(E18, SPICS1, SPICS1, SIG_DESC_SET(SCU80, 15), SIG_DESC_SET(SCU90, 31)); -MS_PIN_DECL(E18, GPIOB7, EXTRST, SPICS1); +PIN_DECL_2(E18, GPIOB7, EXTRST, SPICS1); FUNC_GROUP_DECL(EXTRST, E18); FUNC_GROUP_DECL(SPICS1, E18); @@ -160,56 +167,56 @@ FUNC_GROUP_DECL(SPICS1, E18); #define I2C10_DESC SIG_DESC_SET(SCU90, 23) #define C4 16 -SIG_EXPR_LIST_DECL_SINGLE(SD1CLK, SD1, SD1_DESC); -SIG_EXPR_LIST_DECL_SINGLE(SCL10, I2C10, I2C10_DESC); -MS_PIN_DECL(C4, GPIOC0, SD1CLK, SCL10); +SIG_EXPR_LIST_DECL_SINGLE(C4, SD1CLK, SD1, SD1_DESC); +SIG_EXPR_LIST_DECL_SINGLE(C4, SCL10, I2C10, I2C10_DESC); +PIN_DECL_2(C4, GPIOC0, SD1CLK, SCL10); #define B3 17 -SIG_EXPR_LIST_DECL_SINGLE(SD1CMD, SD1, SD1_DESC); -SIG_EXPR_LIST_DECL_SINGLE(SDA10, I2C10, I2C10_DESC); -MS_PIN_DECL(B3, GPIOC1, SD1CMD, SDA10); +SIG_EXPR_LIST_DECL_SINGLE(B3, SD1CMD, SD1, SD1_DESC); +SIG_EXPR_LIST_DECL_SINGLE(B3, SDA10, I2C10, I2C10_DESC); +PIN_DECL_2(B3, GPIOC1, SD1CMD, SDA10); FUNC_GROUP_DECL(I2C10, C4, B3); #define I2C11_DESC SIG_DESC_SET(SCU90, 24) #define A2 18 -SIG_EXPR_LIST_DECL_SINGLE(SD1DAT0, SD1, SD1_DESC); -SIG_EXPR_LIST_DECL_SINGLE(SCL11, I2C11, I2C11_DESC); -MS_PIN_DECL(A2, GPIOC2, SD1DAT0, SCL11); +SIG_EXPR_LIST_DECL_SINGLE(A2, SD1DAT0, SD1, SD1_DESC); +SIG_EXPR_LIST_DECL_SINGLE(A2, SCL11, I2C11, I2C11_DESC); +PIN_DECL_2(A2, GPIOC2, SD1DAT0, SCL11); #define E5 19 -SIG_EXPR_LIST_DECL_SINGLE(SD1DAT1, SD1, SD1_DESC); -SIG_EXPR_LIST_DECL_SINGLE(SDA11, I2C11, I2C11_DESC); -MS_PIN_DECL(E5, GPIOC3, SD1DAT1, SDA11); +SIG_EXPR_LIST_DECL_SINGLE(E5, SD1DAT1, SD1, SD1_DESC); +SIG_EXPR_LIST_DECL_SINGLE(E5, SDA11, I2C11, I2C11_DESC); +PIN_DECL_2(E5, GPIOC3, SD1DAT1, SDA11); FUNC_GROUP_DECL(I2C11, A2, E5); #define I2C12_DESC SIG_DESC_SET(SCU90, 25) #define D4 20 -SIG_EXPR_LIST_DECL_SINGLE(SD1DAT2, SD1, SD1_DESC); -SIG_EXPR_LIST_DECL_SINGLE(SCL12, I2C12, I2C12_DESC); -MS_PIN_DECL(D4, GPIOC4, SD1DAT2, SCL12); +SIG_EXPR_LIST_DECL_SINGLE(D4, SD1DAT2, SD1, SD1_DESC); +SIG_EXPR_LIST_DECL_SINGLE(D4, SCL12, I2C12, I2C12_DESC); +PIN_DECL_2(D4, GPIOC4, SD1DAT2, SCL12); #define C3 21 -SIG_EXPR_LIST_DECL_SINGLE(SD1DAT3, SD1, SD1_DESC); -SIG_EXPR_LIST_DECL_SINGLE(SDA12, I2C12, I2C12_DESC); -MS_PIN_DECL(C3, GPIOC5, SD1DAT3, SDA12); +SIG_EXPR_LIST_DECL_SINGLE(C3, SD1DAT3, SD1, SD1_DESC); +SIG_EXPR_LIST_DECL_SINGLE(C3, SDA12, I2C12, I2C12_DESC); +PIN_DECL_2(C3, GPIOC5, SD1DAT3, SDA12); FUNC_GROUP_DECL(I2C12, D4, C3); #define I2C13_DESC SIG_DESC_SET(SCU90, 26) #define B2 22 -SIG_EXPR_LIST_DECL_SINGLE(SD1CD, SD1, SD1_DESC); -SIG_EXPR_LIST_DECL_SINGLE(SCL13, I2C13, I2C13_DESC); -MS_PIN_DECL(B2, GPIOC6, SD1CD, SCL13); +SIG_EXPR_LIST_DECL_SINGLE(B2, SD1CD, SD1, SD1_DESC); +SIG_EXPR_LIST_DECL_SINGLE(B2, SCL13, I2C13, I2C13_DESC); +PIN_DECL_2(B2, GPIOC6, SD1CD, SCL13); #define A1 23 -SIG_EXPR_LIST_DECL_SINGLE(SD1WP, SD1, SD1_DESC); -SIG_EXPR_LIST_DECL_SINGLE(SDA13, I2C13, I2C13_DESC); -MS_PIN_DECL(A1, GPIOC7, SD1WP, SDA13); +SIG_EXPR_LIST_DECL_SINGLE(A1, SD1WP, SD1, SD1_DESC); +SIG_EXPR_LIST_DECL_SINGLE(A1, SDA13, I2C13, I2C13_DESC); +PIN_DECL_2(A1, GPIOC7, SD1WP, SDA13); FUNC_GROUP_DECL(I2C13, B2, A1); FUNC_GROUP_DECL(SD1, C4, B3, A2, E5, D4, C3, B2, A1); @@ -219,72 +226,72 @@ FUNC_GROUP_DECL(SD1, C4, B3, A2, E5, D4, C3, B2, A1); #define GPID0_DESC SIG_DESC_SET(SCU8C, 8) #define A18 24 -SIG_EXPR_LIST_DECL_SINGLE(SD2CLK, SD2, SD2_DESC); -SIG_EXPR_DECL(GPID0IN, GPID0, GPID0_DESC); -SIG_EXPR_DECL(GPID0IN, GPID, GPID_DESC); -SIG_EXPR_LIST_DECL_DUAL(GPID0IN, GPID0, GPID); -MS_PIN_DECL(A18, GPIOD0, SD2CLK, GPID0IN); +SIG_EXPR_LIST_DECL_SINGLE(A18, SD2CLK, SD2, SD2_DESC); +SIG_EXPR_DECL_SINGLE(GPID0IN, GPID0, GPID0_DESC); +SIG_EXPR_DECL_SINGLE(GPID0IN, GPID, GPID_DESC); +SIG_EXPR_LIST_DECL_DUAL(A18, GPID0IN, GPID0, GPID); +PIN_DECL_2(A18, GPIOD0, SD2CLK, GPID0IN); #define D16 25 -SIG_EXPR_LIST_DECL_SINGLE(SD2CMD, SD2, SD2_DESC); -SIG_EXPR_DECL(GPID0OUT, GPID0, GPID0_DESC); -SIG_EXPR_DECL(GPID0OUT, GPID, GPID_DESC); -SIG_EXPR_LIST_DECL_DUAL(GPID0OUT, GPID0, GPID); -MS_PIN_DECL(D16, GPIOD1, SD2CMD, GPID0OUT); +SIG_EXPR_LIST_DECL_SINGLE(D16, SD2CMD, SD2, SD2_DESC); +SIG_EXPR_DECL_SINGLE(GPID0OUT, GPID0, GPID0_DESC); +SIG_EXPR_DECL_SINGLE(GPID0OUT, GPID, GPID_DESC); +SIG_EXPR_LIST_DECL_DUAL(D16, GPID0OUT, GPID0, GPID); +PIN_DECL_2(D16, GPIOD1, SD2CMD, GPID0OUT); FUNC_GROUP_DECL(GPID0, A18, D16); #define GPID2_DESC SIG_DESC_SET(SCU8C, 9) #define B17 26 -SIG_EXPR_LIST_DECL_SINGLE(SD2DAT0, SD2, SD2_DESC); -SIG_EXPR_DECL(GPID2IN, GPID2, GPID2_DESC); -SIG_EXPR_DECL(GPID2IN, GPID, GPID_DESC); -SIG_EXPR_LIST_DECL_DUAL(GPID2IN, GPID2, GPID); -MS_PIN_DECL(B17, GPIOD2, SD2DAT0, GPID2IN); +SIG_EXPR_LIST_DECL_SINGLE(B17, SD2DAT0, SD2, SD2_DESC); +SIG_EXPR_DECL_SINGLE(GPID2IN, GPID2, GPID2_DESC); +SIG_EXPR_DECL_SINGLE(GPID2IN, GPID, GPID_DESC); +SIG_EXPR_LIST_DECL_DUAL(B17, GPID2IN, GPID2, GPID); +PIN_DECL_2(B17, GPIOD2, SD2DAT0, GPID2IN); #define A17 27 -SIG_EXPR_LIST_DECL_SINGLE(SD2DAT1, SD2, SD2_DESC); -SIG_EXPR_DECL(GPID2OUT, GPID2, GPID2_DESC); -SIG_EXPR_DECL(GPID2OUT, GPID, GPID_DESC); -SIG_EXPR_LIST_DECL_DUAL(GPID2OUT, GPID2, GPID); -MS_PIN_DECL(A17, GPIOD3, SD2DAT1, GPID2OUT); +SIG_EXPR_LIST_DECL_SINGLE(A17, SD2DAT1, SD2, SD2_DESC); +SIG_EXPR_DECL_SINGLE(GPID2OUT, GPID2, GPID2_DESC); +SIG_EXPR_DECL_SINGLE(GPID2OUT, GPID, GPID_DESC); +SIG_EXPR_LIST_DECL_DUAL(A17, GPID2OUT, GPID2, GPID); +PIN_DECL_2(A17, GPIOD3, SD2DAT1, GPID2OUT); FUNC_GROUP_DECL(GPID2, B17, A17); #define GPID4_DESC SIG_DESC_SET(SCU8C, 10) #define C16 28 -SIG_EXPR_LIST_DECL_SINGLE(SD2DAT2, SD2, SD2_DESC); -SIG_EXPR_DECL(GPID4IN, GPID4, GPID4_DESC); -SIG_EXPR_DECL(GPID4IN, GPID, GPID_DESC); -SIG_EXPR_LIST_DECL_DUAL(GPID4IN, GPID4, GPID); -MS_PIN_DECL(C16, GPIOD4, SD2DAT2, GPID4IN); +SIG_EXPR_LIST_DECL_SINGLE(C16, SD2DAT2, SD2, SD2_DESC); +SIG_EXPR_DECL_SINGLE(GPID4IN, GPID4, GPID4_DESC); +SIG_EXPR_DECL_SINGLE(GPID4IN, GPID, GPID_DESC); +SIG_EXPR_LIST_DECL_DUAL(C16, GPID4IN, GPID4, GPID); +PIN_DECL_2(C16, GPIOD4, SD2DAT2, GPID4IN); #define B16 29 -SIG_EXPR_LIST_DECL_SINGLE(SD2DAT3, SD2, SD2_DESC); -SIG_EXPR_DECL(GPID4OUT, GPID4, GPID4_DESC); -SIG_EXPR_DECL(GPID4OUT, GPID, GPID_DESC); -SIG_EXPR_LIST_DECL_DUAL(GPID4OUT, GPID4, GPID); -MS_PIN_DECL(B16, GPIOD5, SD2DAT3, GPID4OUT); +SIG_EXPR_LIST_DECL_SINGLE(B16, SD2DAT3, SD2, SD2_DESC); +SIG_EXPR_DECL_SINGLE(GPID4OUT, GPID4, GPID4_DESC); +SIG_EXPR_DECL_SINGLE(GPID4OUT, GPID, GPID_DESC); +SIG_EXPR_LIST_DECL_DUAL(B16, GPID4OUT, GPID4, GPID); +PIN_DECL_2(B16, GPIOD5, SD2DAT3, GPID4OUT); FUNC_GROUP_DECL(GPID4, C16, B16); #define GPID6_DESC SIG_DESC_SET(SCU8C, 11) #define A16 30 -SIG_EXPR_LIST_DECL_SINGLE(SD2CD, SD2, SD2_DESC); -SIG_EXPR_DECL(GPID6IN, GPID6, GPID6_DESC); -SIG_EXPR_DECL(GPID6IN, GPID, GPID_DESC); -SIG_EXPR_LIST_DECL_DUAL(GPID6IN, GPID6, GPID); -MS_PIN_DECL(A16, GPIOD6, SD2CD, GPID6IN); +SIG_EXPR_LIST_DECL_SINGLE(A16, SD2CD, SD2, SD2_DESC); +SIG_EXPR_DECL_SINGLE(GPID6IN, GPID6, GPID6_DESC); +SIG_EXPR_DECL_SINGLE(GPID6IN, GPID, GPID_DESC); +SIG_EXPR_LIST_DECL_DUAL(A16, GPID6IN, GPID6, GPID); +PIN_DECL_2(A16, GPIOD6, SD2CD, GPID6IN); #define E15 31 -SIG_EXPR_LIST_DECL_SINGLE(SD2WP, SD2, SD2_DESC); -SIG_EXPR_DECL(GPID6OUT, GPID6, GPID6_DESC); -SIG_EXPR_DECL(GPID6OUT, GPID, GPID_DESC); -SIG_EXPR_LIST_DECL_DUAL(GPID6OUT, GPID6, GPID); -MS_PIN_DECL(E15, GPIOD7, SD2WP, GPID6OUT); +SIG_EXPR_LIST_DECL_SINGLE(E15, SD2WP, SD2, SD2_DESC); +SIG_EXPR_DECL_SINGLE(GPID6OUT, GPID6, GPID6_DESC); +SIG_EXPR_DECL_SINGLE(GPID6OUT, GPID, GPID_DESC); +SIG_EXPR_LIST_DECL_DUAL(E15, GPID6OUT, GPID6, GPID); +PIN_DECL_2(E15, GPIOD7, SD2WP, GPID6OUT); FUNC_GROUP_DECL(GPID6, A16, E15); FUNC_GROUP_DECL(SD2, A18, D16, B17, A17, C16, B16, A16, E15); @@ -297,77 +304,77 @@ FUNC_GROUP_DECL(GPID, A18, D16, B17, A17, C16, B16, A16, E15); #define GPIE6_DESC SIG_DESC_SET(SCU8C, 15) #define D15 32 -SIG_EXPR_LIST_DECL_SINGLE(NCTS3, NCTS3, SIG_DESC_SET(SCU80, 16)); -SIG_EXPR_DECL(GPIE0IN, GPIE0, GPIE0_DESC); -SIG_EXPR_DECL(GPIE0IN, GPIE, GPIE_DESC); -SIG_EXPR_LIST_DECL_DUAL(GPIE0IN, GPIE0, GPIE); -MS_PIN_DECL(D15, GPIOE0, NCTS3, GPIE0IN); +SIG_EXPR_LIST_DECL_SINGLE(D15, NCTS3, NCTS3, SIG_DESC_SET(SCU80, 16)); +SIG_EXPR_DECL_SINGLE(GPIE0IN, GPIE0, GPIE0_DESC); +SIG_EXPR_DECL_SINGLE(GPIE0IN, GPIE, GPIE_DESC); +SIG_EXPR_LIST_DECL_DUAL(D15, GPIE0IN, GPIE0, GPIE); +PIN_DECL_2(D15, GPIOE0, NCTS3, GPIE0IN); FUNC_GROUP_DECL(NCTS3, D15); #define C15 33 -SIG_EXPR_LIST_DECL_SINGLE(NDCD3, NDCD3, SIG_DESC_SET(SCU80, 17)); -SIG_EXPR_DECL(GPIE0OUT, GPIE0, GPIE0_DESC); -SIG_EXPR_DECL(GPIE0OUT, GPIE, GPIE_DESC); -SIG_EXPR_LIST_DECL_DUAL(GPIE0OUT, GPIE0, GPIE); -MS_PIN_DECL(C15, GPIOE1, NDCD3, GPIE0OUT); +SIG_EXPR_LIST_DECL_SINGLE(C15, NDCD3, NDCD3, SIG_DESC_SET(SCU80, 17)); +SIG_EXPR_DECL_SINGLE(GPIE0OUT, GPIE0, GPIE0_DESC); +SIG_EXPR_DECL_SINGLE(GPIE0OUT, GPIE, GPIE_DESC); +SIG_EXPR_LIST_DECL_DUAL(C15, GPIE0OUT, GPIE0, GPIE); +PIN_DECL_2(C15, GPIOE1, NDCD3, GPIE0OUT); FUNC_GROUP_DECL(NDCD3, C15); FUNC_GROUP_DECL(GPIE0, D15, C15); #define B15 34 -SIG_EXPR_LIST_DECL_SINGLE(NDSR3, NDSR3, SIG_DESC_SET(SCU80, 18)); -SIG_EXPR_DECL(GPIE2IN, GPIE2, GPIE2_DESC); -SIG_EXPR_DECL(GPIE2IN, GPIE, GPIE_DESC); -SIG_EXPR_LIST_DECL_DUAL(GPIE2IN, GPIE2, GPIE); -MS_PIN_DECL(B15, GPIOE2, NDSR3, GPIE2IN); +SIG_EXPR_LIST_DECL_SINGLE(B15, NDSR3, NDSR3, SIG_DESC_SET(SCU80, 18)); +SIG_EXPR_DECL_SINGLE(GPIE2IN, GPIE2, GPIE2_DESC); +SIG_EXPR_DECL_SINGLE(GPIE2IN, GPIE, GPIE_DESC); +SIG_EXPR_LIST_DECL_DUAL(B15, GPIE2IN, GPIE2, GPIE); +PIN_DECL_2(B15, GPIOE2, NDSR3, GPIE2IN); FUNC_GROUP_DECL(NDSR3, B15); #define A15 35 -SIG_EXPR_LIST_DECL_SINGLE(NRI3, NRI3, SIG_DESC_SET(SCU80, 19)); -SIG_EXPR_DECL(GPIE2OUT, GPIE2, GPIE2_DESC); -SIG_EXPR_DECL(GPIE2OUT, GPIE, GPIE_DESC); -SIG_EXPR_LIST_DECL_DUAL(GPIE2OUT, GPIE2, GPIE); -MS_PIN_DECL(A15, GPIOE3, NRI3, GPIE2OUT); +SIG_EXPR_LIST_DECL_SINGLE(A15, NRI3, NRI3, SIG_DESC_SET(SCU80, 19)); +SIG_EXPR_DECL_SINGLE(GPIE2OUT, GPIE2, GPIE2_DESC); +SIG_EXPR_DECL_SINGLE(GPIE2OUT, GPIE, GPIE_DESC); +SIG_EXPR_LIST_DECL_DUAL(A15, GPIE2OUT, GPIE2, GPIE); +PIN_DECL_2(A15, GPIOE3, NRI3, GPIE2OUT); FUNC_GROUP_DECL(NRI3, A15); FUNC_GROUP_DECL(GPIE2, B15, A15); #define E14 36 -SIG_EXPR_LIST_DECL_SINGLE(NDTR3, NDTR3, SIG_DESC_SET(SCU80, 20)); -SIG_EXPR_DECL(GPIE4IN, GPIE4, GPIE4_DESC); -SIG_EXPR_DECL(GPIE4IN, GPIE, GPIE_DESC); -SIG_EXPR_LIST_DECL_DUAL(GPIE4IN, GPIE4, GPIE); -MS_PIN_DECL(E14, GPIOE4, NDTR3, GPIE4IN); +SIG_EXPR_LIST_DECL_SINGLE(E14, NDTR3, NDTR3, SIG_DESC_SET(SCU80, 20)); +SIG_EXPR_DECL_SINGLE(GPIE4IN, GPIE4, GPIE4_DESC); +SIG_EXPR_DECL_SINGLE(GPIE4IN, GPIE, GPIE_DESC); +SIG_EXPR_LIST_DECL_DUAL(E14, GPIE4IN, GPIE4, GPIE); +PIN_DECL_2(E14, GPIOE4, NDTR3, GPIE4IN); FUNC_GROUP_DECL(NDTR3, E14); #define D14 37 -SIG_EXPR_LIST_DECL_SINGLE(NRTS3, NRTS3, SIG_DESC_SET(SCU80, 21)); -SIG_EXPR_DECL(GPIE4OUT, GPIE4, GPIE4_DESC); -SIG_EXPR_DECL(GPIE4OUT, GPIE, GPIE_DESC); -SIG_EXPR_LIST_DECL_DUAL(GPIE4OUT, GPIE4, GPIE); -MS_PIN_DECL(D14, GPIOE5, NRTS3, GPIE4OUT); +SIG_EXPR_LIST_DECL_SINGLE(D14, NRTS3, NRTS3, SIG_DESC_SET(SCU80, 21)); +SIG_EXPR_DECL_SINGLE(GPIE4OUT, GPIE4, GPIE4_DESC); +SIG_EXPR_DECL_SINGLE(GPIE4OUT, GPIE, GPIE_DESC); +SIG_EXPR_LIST_DECL_DUAL(D14, GPIE4OUT, GPIE4, GPIE); +PIN_DECL_2(D14, GPIOE5, NRTS3, GPIE4OUT); FUNC_GROUP_DECL(NRTS3, D14); FUNC_GROUP_DECL(GPIE4, E14, D14); #define C14 38 -SIG_EXPR_LIST_DECL_SINGLE(TXD3, TXD3, SIG_DESC_SET(SCU80, 22)); -SIG_EXPR_DECL(GPIE6IN, GPIE6, GPIE6_DESC); -SIG_EXPR_DECL(GPIE6IN, GPIE, GPIE_DESC); -SIG_EXPR_LIST_DECL_DUAL(GPIE6IN, GPIE6, GPIE); -MS_PIN_DECL(C14, GPIOE6, TXD3, GPIE6IN); +SIG_EXPR_LIST_DECL_SINGLE(C14, TXD3, TXD3, SIG_DESC_SET(SCU80, 22)); +SIG_EXPR_DECL_SINGLE(GPIE6IN, GPIE6, GPIE6_DESC); +SIG_EXPR_DECL_SINGLE(GPIE6IN, GPIE, GPIE_DESC); +SIG_EXPR_LIST_DECL_DUAL(C14, GPIE6IN, GPIE6, GPIE); +PIN_DECL_2(C14, GPIOE6, TXD3, GPIE6IN); FUNC_GROUP_DECL(TXD3, C14); #define B14 39 -SIG_EXPR_LIST_DECL_SINGLE(RXD3, RXD3, SIG_DESC_SET(SCU80, 23)); -SIG_EXPR_DECL(GPIE6OUT, GPIE6, GPIE6_DESC); -SIG_EXPR_DECL(GPIE6OUT, GPIE, GPIE_DESC); -SIG_EXPR_LIST_DECL_DUAL(GPIE6OUT, GPIE6, GPIE); -MS_PIN_DECL(B14, GPIOE7, RXD3, GPIE6OUT); +SIG_EXPR_LIST_DECL_SINGLE(B14, RXD3, RXD3, SIG_DESC_SET(SCU80, 23)); +SIG_EXPR_DECL_SINGLE(GPIE6OUT, GPIE6, GPIE6_DESC); +SIG_EXPR_DECL_SINGLE(GPIE6OUT, GPIE, GPIE_DESC); +SIG_EXPR_LIST_DECL_DUAL(B14, GPIE6OUT, GPIE6, GPIE); +PIN_DECL_2(B14, GPIOE7, RXD3, GPIE6OUT); FUNC_GROUP_DECL(RXD3, B14); FUNC_GROUP_DECL(GPIE6, C14, B14); @@ -378,29 +385,29 @@ SSSF_PIN_DECL(D18, GPIOF0, NCTS4, SIG_DESC_SET(SCU80, 24)); #define ACPI_DESC SIG_DESC_BIT(HW_STRAP1, 19, 0) #define B19 41 -SIG_EXPR_LIST_DECL_SINGLE(NDCD4, NDCD4, SIG_DESC_SET(SCU80, 25)); -SIG_EXPR_DECL(SIOPBI, SIOPBI, SIG_DESC_SET(SCUA4, 12)); -SIG_EXPR_DECL(SIOPBI, ACPI, ACPI_DESC); -SIG_EXPR_LIST_DECL_DUAL(SIOPBI, SIOPBI, ACPI); -MS_PIN_DECL(B19, GPIOF1, NDCD4, SIOPBI); +SIG_EXPR_LIST_DECL_SINGLE(B19, NDCD4, NDCD4, SIG_DESC_SET(SCU80, 25)); +SIG_EXPR_DECL_SINGLE(SIOPBI, SIOPBI, SIG_DESC_SET(SCUA4, 12)); +SIG_EXPR_DECL_SINGLE(SIOPBI, ACPI, ACPI_DESC); +SIG_EXPR_LIST_DECL_DUAL(B19, SIOPBI, SIOPBI, ACPI); +PIN_DECL_2(B19, GPIOF1, NDCD4, SIOPBI); FUNC_GROUP_DECL(NDCD4, B19); FUNC_GROUP_DECL(SIOPBI, B19); #define A20 42 -SIG_EXPR_LIST_DECL_SINGLE(NDSR4, NDSR4, SIG_DESC_SET(SCU80, 26)); -SIG_EXPR_DECL(SIOPWRGD, SIOPWRGD, SIG_DESC_SET(SCUA4, 12)); -SIG_EXPR_DECL(SIOPWRGD, ACPI, ACPI_DESC); -SIG_EXPR_LIST_DECL_DUAL(SIOPWRGD, SIOPWRGD, ACPI); -MS_PIN_DECL(A20, GPIOF2, NDSR4, SIOPWRGD); +SIG_EXPR_LIST_DECL_SINGLE(A20, NDSR4, NDSR4, SIG_DESC_SET(SCU80, 26)); +SIG_EXPR_DECL_SINGLE(SIOPWRGD, SIOPWRGD, SIG_DESC_SET(SCUA4, 12)); +SIG_EXPR_DECL_SINGLE(SIOPWRGD, ACPI, ACPI_DESC); +SIG_EXPR_LIST_DECL_DUAL(A20, SIOPWRGD, SIOPWRGD, ACPI); +PIN_DECL_2(A20, GPIOF2, NDSR4, SIOPWRGD); FUNC_GROUP_DECL(NDSR4, A20); FUNC_GROUP_DECL(SIOPWRGD, A20); #define D17 43 -SIG_EXPR_LIST_DECL_SINGLE(NRI4, NRI4, SIG_DESC_SET(SCU80, 27)); -SIG_EXPR_DECL(SIOPBO, SIOPBO, SIG_DESC_SET(SCUA4, 14)); -SIG_EXPR_DECL(SIOPBO, ACPI, ACPI_DESC); -SIG_EXPR_LIST_DECL_DUAL(SIOPBO, SIOPBO, ACPI); -MS_PIN_DECL(D17, GPIOF3, NRI4, SIOPBO); +SIG_EXPR_LIST_DECL_SINGLE(D17, NRI4, NRI4, SIG_DESC_SET(SCU80, 27)); +SIG_EXPR_DECL_SINGLE(SIOPBO, SIOPBO, SIG_DESC_SET(SCUA4, 14)); +SIG_EXPR_DECL_SINGLE(SIOPBO, ACPI, ACPI_DESC); +SIG_EXPR_LIST_DECL_DUAL(D17, SIOPBO, SIOPBO, ACPI); +PIN_DECL_2(D17, GPIOF3, NRI4, SIOPBO); FUNC_GROUP_DECL(NRI4, D17); FUNC_GROUP_DECL(SIOPBO, D17); @@ -408,11 +415,11 @@ FUNC_GROUP_DECL(SIOPBO, D17); SSSF_PIN_DECL(B18, GPIOF4, NDTR4, SIG_DESC_SET(SCU80, 28)); #define A19 45 -SIG_EXPR_LIST_DECL_SINGLE(NDTS4, NDTS4, SIG_DESC_SET(SCU80, 29)); -SIG_EXPR_DECL(SIOSCI, SIOSCI, SIG_DESC_SET(SCUA4, 15)); -SIG_EXPR_DECL(SIOSCI, ACPI, ACPI_DESC); -SIG_EXPR_LIST_DECL_DUAL(SIOSCI, SIOSCI, ACPI); -MS_PIN_DECL(A19, GPIOF5, NDTS4, SIOSCI); +SIG_EXPR_LIST_DECL_SINGLE(A19, NDTS4, NDTS4, SIG_DESC_SET(SCU80, 29)); +SIG_EXPR_DECL_SINGLE(SIOSCI, SIOSCI, SIG_DESC_SET(SCUA4, 15)); +SIG_EXPR_DECL_SINGLE(SIOSCI, ACPI, ACPI_DESC); +SIG_EXPR_LIST_DECL_DUAL(A19, SIOSCI, SIOSCI, ACPI); +PIN_DECL_2(A19, GPIOF5, NDTS4, SIOSCI); FUNC_GROUP_DECL(NDTS4, A19); FUNC_GROUP_DECL(SIOSCI, A19); @@ -435,17 +442,17 @@ SSSF_PIN_DECL(D13, GPIOG2, SGPSI0, SIG_DESC_SET(SCU84, 2)); SSSF_PIN_DECL(C13, GPIOG3, SGPSI1, SIG_DESC_SET(SCU84, 3)); #define B13 52 -SIG_EXPR_LIST_DECL_SINGLE(OSCCLK, OSCCLK, SIG_DESC_SET(SCU2C, 1)); -SIG_EXPR_LIST_DECL_SINGLE(WDTRST1, WDTRST1, SIG_DESC_SET(SCU84, 4)); -MS_PIN_DECL(B13, GPIOG4, OSCCLK, WDTRST1); +SIG_EXPR_LIST_DECL_SINGLE(B13, OSCCLK, OSCCLK, SIG_DESC_SET(SCU2C, 1)); +SIG_EXPR_LIST_DECL_SINGLE(B13, WDTRST1, WDTRST1, SIG_DESC_SET(SCU84, 4)); +PIN_DECL_2(B13, GPIOG4, OSCCLK, WDTRST1); FUNC_GROUP_DECL(OSCCLK, B13); FUNC_GROUP_DECL(WDTRST1, B13); #define Y21 53 -SIG_EXPR_LIST_DECL_SINGLE(USBCKI, USBCKI, SIG_DESC_SET(HW_STRAP1, 23)); -SIG_EXPR_LIST_DECL_SINGLE(WDTRST2, WDTRST2, SIG_DESC_SET(SCU84, 5)); -MS_PIN_DECL(Y21, GPIOG5, USBCKI, WDTRST2); +SIG_EXPR_LIST_DECL_SINGLE(Y21, USBCKI, USBCKI, SIG_DESC_SET(HW_STRAP1, 23)); +SIG_EXPR_LIST_DECL_SINGLE(Y21, WDTRST2, WDTRST2, SIG_DESC_SET(SCU84, 5)); +PIN_DECL_2(Y21, GPIOG5, USBCKI, WDTRST2); FUNC_GROUP_DECL(USBCKI, Y21); FUNC_GROUP_DECL(WDTRST2, Y21); @@ -462,60 +469,60 @@ SSSF_PIN_DECL(U18, GPIOG7, FLWP, SIG_DESC_SET(SCU84, 7)); #define BOOT_SRC_NOR { ASPEED_IP_SCU, HW_STRAP1, GENMASK(1, 0), 0, 0 } #define A8 56 -SIG_EXPR_DECL(ROMD8, ROM16, ROM16_DESC); -SIG_EXPR_DECL(ROMD8, ROM16S, FLASH_WIDE, BOOT_SRC_NOR); -SIG_EXPR_LIST_DECL_DUAL(ROMD8, ROM16, ROM16S); -SIG_EXPR_LIST_DECL_SINGLE(NCTS6, NCTS6, UART6_DESC); -MS_PIN_DECL(A8, GPIOH0, ROMD8, NCTS6); +SIG_EXPR_DECL_SINGLE(ROMD8, ROM16, ROM16_DESC); +SIG_EXPR_DECL_SINGLE(ROMD8, ROM16S, FLASH_WIDE, BOOT_SRC_NOR); +SIG_EXPR_LIST_DECL_DUAL(A8, ROMD8, ROM16, ROM16S); +SIG_EXPR_LIST_DECL_SINGLE(A8, NCTS6, NCTS6, UART6_DESC); +PIN_DECL_2(A8, GPIOH0, ROMD8, NCTS6); #define C7 57 -SIG_EXPR_DECL(ROMD9, ROM16, ROM16_DESC); -SIG_EXPR_DECL(ROMD9, ROM16S, FLASH_WIDE, BOOT_SRC_NOR); -SIG_EXPR_LIST_DECL_DUAL(ROMD9, ROM16, ROM16S); -SIG_EXPR_LIST_DECL_SINGLE(NDCD6, NDCD6, UART6_DESC); -MS_PIN_DECL(C7, GPIOH1, ROMD9, NDCD6); +SIG_EXPR_DECL_SINGLE(ROMD9, ROM16, ROM16_DESC); +SIG_EXPR_DECL_SINGLE(ROMD9, ROM16S, FLASH_WIDE, BOOT_SRC_NOR); +SIG_EXPR_LIST_DECL_DUAL(C7, ROMD9, ROM16, ROM16S); +SIG_EXPR_LIST_DECL_SINGLE(C7, NDCD6, NDCD6, UART6_DESC); +PIN_DECL_2(C7, GPIOH1, ROMD9, NDCD6); #define B7 58 -SIG_EXPR_DECL(ROMD10, ROM16, ROM16_DESC); -SIG_EXPR_DECL(ROMD10, ROM16S, FLASH_WIDE, BOOT_SRC_NOR); -SIG_EXPR_LIST_DECL_DUAL(ROMD10, ROM16, ROM16S); -SIG_EXPR_LIST_DECL_SINGLE(NDSR6, NDSR6, UART6_DESC); -MS_PIN_DECL(B7, GPIOH2, ROMD10, NDSR6); +SIG_EXPR_DECL_SINGLE(ROMD10, ROM16, ROM16_DESC); +SIG_EXPR_DECL_SINGLE(ROMD10, ROM16S, FLASH_WIDE, BOOT_SRC_NOR); +SIG_EXPR_LIST_DECL_DUAL(B7, ROMD10, ROM16, ROM16S); +SIG_EXPR_LIST_DECL_SINGLE(B7, NDSR6, NDSR6, UART6_DESC); +PIN_DECL_2(B7, GPIOH2, ROMD10, NDSR6); #define A7 59 -SIG_EXPR_DECL(ROMD11, ROM16, ROM16_DESC); -SIG_EXPR_DECL(ROMD11, ROM16S, FLASH_WIDE, BOOT_SRC_NOR); -SIG_EXPR_LIST_DECL_DUAL(ROMD11, ROM16, ROM16S); -SIG_EXPR_LIST_DECL_SINGLE(NRI6, NRI6, UART6_DESC); -MS_PIN_DECL(A7, GPIOH3, ROMD11, NRI6); +SIG_EXPR_DECL_SINGLE(ROMD11, ROM16, ROM16_DESC); +SIG_EXPR_DECL_SINGLE(ROMD11, ROM16S, FLASH_WIDE, BOOT_SRC_NOR); +SIG_EXPR_LIST_DECL_DUAL(A7, ROMD11, ROM16, ROM16S); +SIG_EXPR_LIST_DECL_SINGLE(A7, NRI6, NRI6, UART6_DESC); +PIN_DECL_2(A7, GPIOH3, ROMD11, NRI6); #define D7 60 -SIG_EXPR_DECL(ROMD12, ROM16, ROM16_DESC); -SIG_EXPR_DECL(ROMD12, ROM16S, FLASH_WIDE, BOOT_SRC_NOR); -SIG_EXPR_LIST_DECL_DUAL(ROMD12, ROM16, ROM16S); -SIG_EXPR_LIST_DECL_SINGLE(NDTR6, NDTR6, UART6_DESC); -MS_PIN_DECL(D7, GPIOH4, ROMD12, NDTR6); +SIG_EXPR_DECL_SINGLE(ROMD12, ROM16, ROM16_DESC); +SIG_EXPR_DECL_SINGLE(ROMD12, ROM16S, FLASH_WIDE, BOOT_SRC_NOR); +SIG_EXPR_LIST_DECL_DUAL(D7, ROMD12, ROM16, ROM16S); +SIG_EXPR_LIST_DECL_SINGLE(D7, NDTR6, NDTR6, UART6_DESC); +PIN_DECL_2(D7, GPIOH4, ROMD12, NDTR6); #define B6 61 -SIG_EXPR_DECL(ROMD13, ROM16, ROM16_DESC); -SIG_EXPR_DECL(ROMD13, ROM16S, FLASH_WIDE, BOOT_SRC_NOR); -SIG_EXPR_LIST_DECL_DUAL(ROMD13, ROM16, ROM16S); -SIG_EXPR_LIST_DECL_SINGLE(NRTS6, NRTS6, UART6_DESC); -MS_PIN_DECL(B6, GPIOH5, ROMD13, NRTS6); +SIG_EXPR_DECL_SINGLE(ROMD13, ROM16, ROM16_DESC); +SIG_EXPR_DECL_SINGLE(ROMD13, ROM16S, FLASH_WIDE, BOOT_SRC_NOR); +SIG_EXPR_LIST_DECL_DUAL(B6, ROMD13, ROM16, ROM16S); +SIG_EXPR_LIST_DECL_SINGLE(B6, NRTS6, NRTS6, UART6_DESC); +PIN_DECL_2(B6, GPIOH5, ROMD13, NRTS6); #define A6 62 -SIG_EXPR_DECL(ROMD14, ROM16, ROM16_DESC); -SIG_EXPR_DECL(ROMD14, ROM16S, FLASH_WIDE, BOOT_SRC_NOR); -SIG_EXPR_LIST_DECL_DUAL(ROMD14, ROM16, ROM16S); -SIG_EXPR_LIST_DECL_SINGLE(TXD6, TXD6, UART6_DESC); -MS_PIN_DECL(A6, GPIOH6, ROMD14, TXD6); +SIG_EXPR_DECL_SINGLE(ROMD14, ROM16, ROM16_DESC); +SIG_EXPR_DECL_SINGLE(ROMD14, ROM16S, FLASH_WIDE, BOOT_SRC_NOR); +SIG_EXPR_LIST_DECL_DUAL(A6, ROMD14, ROM16, ROM16S); +SIG_EXPR_LIST_DECL_SINGLE(A6, TXD6, TXD6, UART6_DESC); +PIN_DECL_2(A6, GPIOH6, ROMD14, TXD6); #define E7 63 -SIG_EXPR_DECL(ROMD15, ROM16, ROM16_DESC); -SIG_EXPR_DECL(ROMD15, ROM16S, FLASH_WIDE, BOOT_SRC_NOR); -SIG_EXPR_LIST_DECL_DUAL(ROMD15, ROM16, ROM16S); -SIG_EXPR_LIST_DECL_SINGLE(RXD6, RXD6, UART6_DESC); -MS_PIN_DECL(E7, GPIOH7, ROMD15, RXD6); +SIG_EXPR_DECL_SINGLE(ROMD15, ROM16, ROM16_DESC); +SIG_EXPR_DECL_SINGLE(ROMD15, ROM16S, FLASH_WIDE, BOOT_SRC_NOR); +SIG_EXPR_LIST_DECL_DUAL(E7, ROMD15, ROM16, ROM16S); +SIG_EXPR_LIST_DECL_SINGLE(E7, RXD6, RXD6, UART6_DESC); +PIN_DECL_2(E7, GPIOH7, ROMD15, RXD6); FUNC_GROUP_DECL(UART6, A8, C7, B7, A7, D7, B6, A6, E7); @@ -527,70 +534,78 @@ FUNC_GROUP_DECL(UART6, A8, C7, B7, A7, D7, B6, A6, E7); { ASPEED_IP_SCU, HW_STRAP1, GENMASK(13, 12), 3, 0 } #define C22 64 -SIG_EXPR_DECL(SYSCS, SPI1DEBUG, SPI1DEBUG_DESC); -SIG_EXPR_DECL(SYSCS, SPI1PASSTHRU, SPI1PASSTHRU_DESC); -SIG_EXPR_LIST_DECL_DUAL(SYSCS, SPI1DEBUG, SPI1PASSTHRU); -SS_PIN_DECL(C22, GPIOI0, SYSCS); +SIG_EXPR_DECL_SINGLE(SYSCS, SPI1DEBUG, SPI1DEBUG_DESC); +SIG_EXPR_DECL_SINGLE(SYSCS, SPI1PASSTHRU, SPI1PASSTHRU_DESC); +SIG_EXPR_LIST_DECL_DUAL(C22, SYSCS, SPI1DEBUG, SPI1PASSTHRU); +PIN_DECL_1(C22, GPIOI0, SYSCS); #define G18 65 -SIG_EXPR_DECL(SYSCK, SPI1DEBUG, SPI1DEBUG_DESC); -SIG_EXPR_DECL(SYSCK, SPI1PASSTHRU, SPI1PASSTHRU_DESC); -SIG_EXPR_LIST_DECL_DUAL(SYSCK, SPI1DEBUG, SPI1PASSTHRU); -SS_PIN_DECL(G18, GPIOI1, SYSCK); +SIG_EXPR_DECL_SINGLE(SYSCK, SPI1DEBUG, SPI1DEBUG_DESC); +SIG_EXPR_DECL_SINGLE(SYSCK, SPI1PASSTHRU, SPI1PASSTHRU_DESC); +SIG_EXPR_LIST_DECL_DUAL(G18, SYSCK, SPI1DEBUG, SPI1PASSTHRU); +PIN_DECL_1(G18, GPIOI1, SYSCK); #define D19 66 -SIG_EXPR_DECL(SYSDO, SPI1DEBUG, SPI1DEBUG_DESC); -SIG_EXPR_DECL(SYSDO, SPI1PASSTHRU, SPI1PASSTHRU_DESC); -SIG_EXPR_LIST_DECL_DUAL(SYSDO, SPI1DEBUG, SPI1PASSTHRU); -SS_PIN_DECL(D19, GPIOI2, SYSDO); +SIG_EXPR_DECL_SINGLE(SYSDO, SPI1DEBUG, SPI1DEBUG_DESC); +SIG_EXPR_DECL_SINGLE(SYSDO, SPI1PASSTHRU, SPI1PASSTHRU_DESC); +SIG_EXPR_LIST_DECL_DUAL(D19, SYSDO, SPI1DEBUG, SPI1PASSTHRU); +PIN_DECL_1(D19, GPIOI2, SYSDO); #define C20 67 -SIG_EXPR_DECL(SYSDI, SPI1DEBUG, SPI1DEBUG_DESC); -SIG_EXPR_DECL(SYSDI, SPI1PASSTHRU, SPI1PASSTHRU_DESC); -SIG_EXPR_LIST_DECL_DUAL(SYSDI, SPI1DEBUG, SPI1PASSTHRU); -SS_PIN_DECL(C20, GPIOI3, SYSDI); +SIG_EXPR_DECL_SINGLE(SYSDI, SPI1DEBUG, SPI1DEBUG_DESC); +SIG_EXPR_DECL_SINGLE(SYSDI, SPI1PASSTHRU, SPI1PASSTHRU_DESC); +SIG_EXPR_LIST_DECL_DUAL(C20, SYSDI, SPI1DEBUG, SPI1PASSTHRU); +PIN_DECL_1(C20, GPIOI3, SYSDI); #define VB_DESC SIG_DESC_SET(HW_STRAP1, 5) #define B22 68 -SIG_EXPR_DECL(SPI1CS0, SPI1, SPI1_DESC); -SIG_EXPR_DECL(SPI1CS0, SPI1DEBUG, SPI1DEBUG_DESC); -SIG_EXPR_DECL(SPI1CS0, SPI1PASSTHRU, SPI1PASSTHRU_DESC); -SIG_EXPR_LIST_DECL(SPI1CS0, SIG_EXPR_PTR(SPI1CS0, SPI1), +SIG_EXPR_DECL_SINGLE(SPI1CS0, SPI1, SPI1_DESC); +SIG_EXPR_DECL_SINGLE(SPI1CS0, SPI1DEBUG, SPI1DEBUG_DESC); +SIG_EXPR_DECL_SINGLE(SPI1CS0, SPI1PASSTHRU, SPI1PASSTHRU_DESC); +SIG_EXPR_LIST_DECL(SPI1CS0, SPI1, + SIG_EXPR_PTR(SPI1CS0, SPI1), SIG_EXPR_PTR(SPI1CS0, SPI1DEBUG), SIG_EXPR_PTR(SPI1CS0, SPI1PASSTHRU)); -SIG_EXPR_LIST_DECL_SINGLE(VBCS, VGABIOS_ROM, VB_DESC); -MS_PIN_DECL(B22, GPIOI4, SPI1CS0, VBCS); +SIG_EXPR_LIST_ALIAS(B22, SPI1CS0, SPI1); +SIG_EXPR_LIST_DECL_SINGLE(B22, VBCS, VGABIOS_ROM, VB_DESC); +PIN_DECL_2(B22, GPIOI4, SPI1CS0, VBCS); #define G19 69 -SIG_EXPR_DECL(SPI1CK, SPI1, SPI1_DESC); -SIG_EXPR_DECL(SPI1CK, SPI1DEBUG, SPI1DEBUG_DESC); -SIG_EXPR_DECL(SPI1CK, SPI1PASSTHRU, SPI1PASSTHRU_DESC); -SIG_EXPR_LIST_DECL(SPI1CK, SIG_EXPR_PTR(SPI1CK, SPI1), +SIG_EXPR_DECL_SINGLE(SPI1CK, SPI1, SPI1_DESC); +SIG_EXPR_DECL_SINGLE(SPI1CK, SPI1DEBUG, SPI1DEBUG_DESC); +SIG_EXPR_DECL_SINGLE(SPI1CK, SPI1PASSTHRU, SPI1PASSTHRU_DESC); +SIG_EXPR_LIST_DECL(SPI1CK, SPI1, + SIG_EXPR_PTR(SPI1CK, SPI1), SIG_EXPR_PTR(SPI1CK, SPI1DEBUG), SIG_EXPR_PTR(SPI1CK, SPI1PASSTHRU)); -SIG_EXPR_LIST_DECL_SINGLE(VBCK, VGABIOS_ROM, VB_DESC); -MS_PIN_DECL(G19, GPIOI5, SPI1CK, VBCK); +SIG_EXPR_LIST_ALIAS(G19, SPI1CK, SPI1); +SIG_EXPR_LIST_DECL_SINGLE(G19, VBCK, VGABIOS_ROM, VB_DESC); +PIN_DECL_2(G19, GPIOI5, SPI1CK, VBCK); #define C18 70 -SIG_EXPR_DECL(SPI1DO, SPI1, SPI1_DESC); -SIG_EXPR_DECL(SPI1DO, SPI1DEBUG, SPI1DEBUG_DESC); -SIG_EXPR_DECL(SPI1DO, SPI1PASSTHRU, SPI1PASSTHRU_DESC); -SIG_EXPR_LIST_DECL(SPI1DO, SIG_EXPR_PTR(SPI1DO, SPI1), +SIG_EXPR_DECL_SINGLE(SPI1DO, SPI1, SPI1_DESC); +SIG_EXPR_DECL_SINGLE(SPI1DO, SPI1DEBUG, SPI1DEBUG_DESC); +SIG_EXPR_DECL_SINGLE(SPI1DO, SPI1PASSTHRU, SPI1PASSTHRU_DESC); +SIG_EXPR_LIST_DECL(SPI1DO, SPI1, + SIG_EXPR_PTR(SPI1DO, SPI1), SIG_EXPR_PTR(SPI1DO, SPI1DEBUG), SIG_EXPR_PTR(SPI1DO, SPI1PASSTHRU)); -SIG_EXPR_LIST_DECL_SINGLE(VBDO, VGABIOS_ROM, VB_DESC); -MS_PIN_DECL(C18, GPIOI6, SPI1DO, VBDO); +SIG_EXPR_LIST_ALIAS(C18, SPI1DO, SPI1); +SIG_EXPR_LIST_DECL_SINGLE(C18, VBDO, VGABIOS_ROM, VB_DESC); +PIN_DECL_2(C18, GPIOI6, SPI1DO, VBDO); #define E20 71 -SIG_EXPR_DECL(SPI1DI, SPI1, SPI1_DESC); -SIG_EXPR_DECL(SPI1DI, SPI1DEBUG, SPI1DEBUG_DESC); -SIG_EXPR_DECL(SPI1DI, SPI1PASSTHRU, SPI1PASSTHRU_DESC); -SIG_EXPR_LIST_DECL(SPI1DI, SIG_EXPR_PTR(SPI1DI, SPI1), +SIG_EXPR_DECL_SINGLE(SPI1DI, SPI1, SPI1_DESC); +SIG_EXPR_DECL_SINGLE(SPI1DI, SPI1DEBUG, SPI1DEBUG_DESC); +SIG_EXPR_DECL_SINGLE(SPI1DI, SPI1PASSTHRU, SPI1PASSTHRU_DESC); +SIG_EXPR_LIST_DECL(SPI1DI, SPI1, + SIG_EXPR_PTR(SPI1DI, SPI1), SIG_EXPR_PTR(SPI1DI, SPI1DEBUG), SIG_EXPR_PTR(SPI1DI, SPI1PASSTHRU)); -SIG_EXPR_LIST_DECL_SINGLE(VBDI, VGABIOS_ROM, VB_DESC); -MS_PIN_DECL(E20, GPIOI7, SPI1DI, VBDI); +SIG_EXPR_LIST_ALIAS(E20, SPI1DI, SPI1); +SIG_EXPR_LIST_DECL_SINGLE(E20, VBDI, VGABIOS_ROM, VB_DESC); +PIN_DECL_2(E20, GPIOI7, SPI1DI, VBDI); FUNC_GROUP_DECL(SPI1, B22, G19, C18, E20); FUNC_GROUP_DECL(SPI1DEBUG, C22, G18, D19, C20, B22, G19, C18, E20); @@ -624,48 +639,48 @@ SSSF_PIN_DECL(T1, GPIOJ7, DDCDAT, SIG_DESC_SET(SCU84, 15)); #define I2C5_DESC SIG_DESC_SET(SCU90, 18) #define E3 80 -SIG_EXPR_LIST_DECL_SINGLE(SCL5, I2C5, I2C5_DESC); -SS_PIN_DECL(E3, GPIOK0, SCL5); +SIG_EXPR_LIST_DECL_SINGLE(E3, SCL5, I2C5, I2C5_DESC); +PIN_DECL_1(E3, GPIOK0, SCL5); #define D2 81 -SIG_EXPR_LIST_DECL_SINGLE(SDA5, I2C5, I2C5_DESC); -SS_PIN_DECL(D2, GPIOK1, SDA5); +SIG_EXPR_LIST_DECL_SINGLE(D2, SDA5, I2C5, I2C5_DESC); +PIN_DECL_1(D2, GPIOK1, SDA5); FUNC_GROUP_DECL(I2C5, E3, D2); #define I2C6_DESC SIG_DESC_SET(SCU90, 19) #define C1 82 -SIG_EXPR_LIST_DECL_SINGLE(SCL6, I2C6, I2C6_DESC); -SS_PIN_DECL(C1, GPIOK2, SCL6); +SIG_EXPR_LIST_DECL_SINGLE(C1, SCL6, I2C6, I2C6_DESC); +PIN_DECL_1(C1, GPIOK2, SCL6); #define F4 83 -SIG_EXPR_LIST_DECL_SINGLE(SDA6, I2C6, I2C6_DESC); -SS_PIN_DECL(F4, GPIOK3, SDA6); +SIG_EXPR_LIST_DECL_SINGLE(F4, SDA6, I2C6, I2C6_DESC); +PIN_DECL_1(F4, GPIOK3, SDA6); FUNC_GROUP_DECL(I2C6, C1, F4); #define I2C7_DESC SIG_DESC_SET(SCU90, 20) #define E2 84 -SIG_EXPR_LIST_DECL_SINGLE(SCL7, I2C7, I2C7_DESC); -SS_PIN_DECL(E2, GPIOK4, SCL7); +SIG_EXPR_LIST_DECL_SINGLE(E2, SCL7, I2C7, I2C7_DESC); +PIN_DECL_1(E2, GPIOK4, SCL7); #define D1 85 -SIG_EXPR_LIST_DECL_SINGLE(SDA7, I2C7, I2C7_DESC); -SS_PIN_DECL(D1, GPIOK5, SDA7); +SIG_EXPR_LIST_DECL_SINGLE(D1, SDA7, I2C7, I2C7_DESC); +PIN_DECL_1(D1, GPIOK5, SDA7); FUNC_GROUP_DECL(I2C7, E2, D1); #define I2C8_DESC SIG_DESC_SET(SCU90, 21) #define G5 86 -SIG_EXPR_LIST_DECL_SINGLE(SCL8, I2C8, I2C8_DESC); -SS_PIN_DECL(G5, GPIOK6, SCL8); +SIG_EXPR_LIST_DECL_SINGLE(G5, SCL8, I2C8, I2C8_DESC); +PIN_DECL_1(G5, GPIOK6, SCL8); #define F3 87 -SIG_EXPR_LIST_DECL_SINGLE(SDA8, I2C8, I2C8_DESC); -SS_PIN_DECL(F3, GPIOK7, SDA8); +SIG_EXPR_LIST_DECL_SINGLE(F3, SDA8, I2C8, I2C8_DESC); +PIN_DECL_1(F3, GPIOK7, SDA8); FUNC_GROUP_DECL(I2C8, G5, F3); @@ -678,297 +693,341 @@ SSSF_PIN_DECL(U1, GPIOL0, NCTS1, SIG_DESC_SET(SCU84, 16)); #define T5 89 #define T5_DESC SIG_DESC_SET(SCU84, 17) -SIG_EXPR_DECL(VPIDE, VPI18, VPI18_DESC, T5_DESC); -SIG_EXPR_DECL(VPIDE, VPI24, VPI24_DESC, T5_DESC); -SIG_EXPR_DECL(VPIDE, VPI30, VPI30_DESC, T5_DESC); -SIG_EXPR_LIST_DECL(VPIDE, SIG_EXPR_PTR(VPIDE, VPI18), - SIG_EXPR_PTR(VPIDE, VPI24), - SIG_EXPR_PTR(VPIDE, VPI30)); -SIG_EXPR_LIST_DECL_SINGLE(NDCD1, NDCD1, T5_DESC); -MS_PIN_DECL(T5, GPIOL1, VPIDE, NDCD1); +SIG_EXPR_DECL_SINGLE(VPIDE, VPI18, VPI18_DESC, T5_DESC); +SIG_EXPR_DECL_SINGLE(VPIDE, VPI24, VPI24_DESC, T5_DESC); +SIG_EXPR_DECL_SINGLE(VPIDE, VPI30, VPI30_DESC, T5_DESC); +SIG_EXPR_LIST_DECL(VPIDE, VPI, + SIG_EXPR_PTR(VPIDE, VPI18), + SIG_EXPR_PTR(VPIDE, VPI24), + SIG_EXPR_PTR(VPIDE, VPI30)); +SIG_EXPR_LIST_ALIAS(T5, VPIDE, VPI); +SIG_EXPR_LIST_DECL_SINGLE(T5, NDCD1, NDCD1, T5_DESC); +PIN_DECL_2(T5, GPIOL1, VPIDE, NDCD1); FUNC_GROUP_DECL(NDCD1, T5); #define U3 90 #define U3_DESC SIG_DESC_SET(SCU84, 18) -SIG_EXPR_DECL(VPIODD, VPI18, VPI18_DESC, U3_DESC); -SIG_EXPR_DECL(VPIODD, VPI24, VPI24_DESC, U3_DESC); -SIG_EXPR_DECL(VPIODD, VPI30, VPI30_DESC, U3_DESC); -SIG_EXPR_LIST_DECL(VPIODD, SIG_EXPR_PTR(VPIODD, VPI18), +SIG_EXPR_DECL_SINGLE(VPIODD, VPI18, VPI18_DESC, U3_DESC); +SIG_EXPR_DECL_SINGLE(VPIODD, VPI24, VPI24_DESC, U3_DESC); +SIG_EXPR_DECL_SINGLE(VPIODD, VPI30, VPI30_DESC, U3_DESC); +SIG_EXPR_LIST_DECL(VPIODD, VPI, + SIG_EXPR_PTR(VPIODD, VPI18), SIG_EXPR_PTR(VPIODD, VPI24), SIG_EXPR_PTR(VPIODD, VPI30)); -SIG_EXPR_LIST_DECL_SINGLE(NDSR1, NDSR1, U3_DESC); -MS_PIN_DECL(U3, GPIOL2, VPIODD, NDSR1); +SIG_EXPR_LIST_ALIAS(U3, VPIODD, VPI); +SIG_EXPR_LIST_DECL_SINGLE(U3, NDSR1, NDSR1, U3_DESC); +PIN_DECL_2(U3, GPIOL2, VPIODD, NDSR1); FUNC_GROUP_DECL(NDSR1, U3); #define V1 91 #define V1_DESC SIG_DESC_SET(SCU84, 19) -SIG_EXPR_DECL(VPIHS, VPI18, VPI18_DESC, V1_DESC); -SIG_EXPR_DECL(VPIHS, VPI24, VPI24_DESC, V1_DESC); -SIG_EXPR_DECL(VPIHS, VPI30, VPI30_DESC, V1_DESC); -SIG_EXPR_LIST_DECL(VPIHS, SIG_EXPR_PTR(VPIHS, VPI18), +SIG_EXPR_DECL_SINGLE(VPIHS, VPI18, VPI18_DESC, V1_DESC); +SIG_EXPR_DECL_SINGLE(VPIHS, VPI24, VPI24_DESC, V1_DESC); +SIG_EXPR_DECL_SINGLE(VPIHS, VPI30, VPI30_DESC, V1_DESC); +SIG_EXPR_LIST_DECL(VPIHS, VPI, + SIG_EXPR_PTR(VPIHS, VPI18), SIG_EXPR_PTR(VPIHS, VPI24), SIG_EXPR_PTR(VPIHS, VPI30)); -SIG_EXPR_LIST_DECL_SINGLE(NRI1, NRI1, V1_DESC); -MS_PIN_DECL(V1, GPIOL3, VPIHS, NRI1); +SIG_EXPR_LIST_ALIAS(V1, VPIHS, VPI); +SIG_EXPR_LIST_DECL_SINGLE(V1, NRI1, NRI1, V1_DESC); +PIN_DECL_2(V1, GPIOL3, VPIHS, NRI1); FUNC_GROUP_DECL(NRI1, V1); #define U4 92 #define U4_DESC SIG_DESC_SET(SCU84, 20) -SIG_EXPR_DECL(VPIVS, VPI18, VPI18_DESC, U4_DESC); -SIG_EXPR_DECL(VPIVS, VPI24, VPI24_DESC, U4_DESC); -SIG_EXPR_DECL(VPIVS, VPI30, VPI30_DESC, U4_DESC); -SIG_EXPR_LIST_DECL(VPIVS, SIG_EXPR_PTR(VPIVS, VPI18), +SIG_EXPR_DECL_SINGLE(VPIVS, VPI18, VPI18_DESC, U4_DESC); +SIG_EXPR_DECL_SINGLE(VPIVS, VPI24, VPI24_DESC, U4_DESC); +SIG_EXPR_DECL_SINGLE(VPIVS, VPI30, VPI30_DESC, U4_DESC); +SIG_EXPR_LIST_DECL(VPIVS, VPI, + SIG_EXPR_PTR(VPIVS, VPI18), SIG_EXPR_PTR(VPIVS, VPI24), SIG_EXPR_PTR(VPIVS, VPI30)); -SIG_EXPR_LIST_DECL_SINGLE(NDTR1, NDTR1, U4_DESC); -MS_PIN_DECL(U4, GPIOL4, VPIVS, NDTR1); +SIG_EXPR_LIST_ALIAS(U4, VPIVS, VPI); +SIG_EXPR_LIST_DECL_SINGLE(U4, NDTR1, NDTR1, U4_DESC); +PIN_DECL_2(U4, GPIOL4, VPIVS, NDTR1); FUNC_GROUP_DECL(NDTR1, U4); #define V2 93 #define V2_DESC SIG_DESC_SET(SCU84, 21) -SIG_EXPR_DECL(VPICLK, VPI18, VPI18_DESC, V2_DESC); -SIG_EXPR_DECL(VPICLK, VPI24, VPI24_DESC, V2_DESC); -SIG_EXPR_DECL(VPICLK, VPI30, VPI30_DESC, V2_DESC); -SIG_EXPR_LIST_DECL(VPICLK, SIG_EXPR_PTR(VPICLK, VPI18), +SIG_EXPR_DECL_SINGLE(VPICLK, VPI18, VPI18_DESC, V2_DESC); +SIG_EXPR_DECL_SINGLE(VPICLK, VPI24, VPI24_DESC, V2_DESC); +SIG_EXPR_DECL_SINGLE(VPICLK, VPI30, VPI30_DESC, V2_DESC); +SIG_EXPR_LIST_DECL(VPICLK, VPI, + SIG_EXPR_PTR(VPICLK, VPI18), SIG_EXPR_PTR(VPICLK, VPI24), SIG_EXPR_PTR(VPICLK, VPI30)); -SIG_EXPR_LIST_DECL_SINGLE(NRTS1, NRTS1, V2_DESC); -MS_PIN_DECL(V2, GPIOL5, VPICLK, NRTS1); +SIG_EXPR_LIST_ALIAS(V2, VPICLK, VPI); +SIG_EXPR_LIST_DECL_SINGLE(V2, NRTS1, NRTS1, V2_DESC); +PIN_DECL_2(V2, GPIOL5, VPICLK, NRTS1); FUNC_GROUP_DECL(NRTS1, V2); #define W1 94 #define W1_DESC SIG_DESC_SET(SCU84, 22) -SIG_EXPR_LIST_DECL_SINGLE(VPIB0, VPI30, VPI30_DESC, W1_DESC); -SIG_EXPR_LIST_DECL_SINGLE(TXD1, TXD1, W1_DESC); -MS_PIN_DECL(W1, GPIOL6, VPIB0, TXD1); +SIG_EXPR_LIST_DECL_SINGLE(W1, VPIB0, VPI30, VPI30_DESC, W1_DESC); +SIG_EXPR_LIST_DECL_SINGLE(W1, TXD1, TXD1, W1_DESC); +PIN_DECL_2(W1, GPIOL6, VPIB0, TXD1); FUNC_GROUP_DECL(TXD1, W1); #define U5 95 #define U5_DESC SIG_DESC_SET(SCU84, 23) -SIG_EXPR_LIST_DECL_SINGLE(VPIB1, VPI30, VPI30_DESC, U5_DESC); -SIG_EXPR_LIST_DECL_SINGLE(RXD1, RXD1, U5_DESC); -MS_PIN_DECL(U5, GPIOL7, VPIB1, RXD1); +SIG_EXPR_LIST_DECL_SINGLE(U5, VPIB1, VPI30, VPI30_DESC, U5_DESC); +SIG_EXPR_LIST_DECL_SINGLE(U5, RXD1, RXD1, U5_DESC); +PIN_DECL_2(U5, GPIOL7, VPIB1, RXD1); FUNC_GROUP_DECL(RXD1, U5); #define V3 96 #define V3_DESC SIG_DESC_SET(SCU84, 24) -SIG_EXPR_DECL(VPIOB2, VPI18, VPI18_DESC, V3_DESC); -SIG_EXPR_DECL(VPIOB2, VPI24, VPI24_DESC, V3_DESC); -SIG_EXPR_DECL(VPIOB2, VPI30, VPI30_DESC, V3_DESC); -SIG_EXPR_LIST_DECL(VPIOB2, SIG_EXPR_PTR(VPIOB2, VPI18), +SIG_EXPR_DECL_SINGLE(VPIOB2, VPI18, VPI18_DESC, V3_DESC); +SIG_EXPR_DECL_SINGLE(VPIOB2, VPI24, VPI24_DESC, V3_DESC); +SIG_EXPR_DECL_SINGLE(VPIOB2, VPI30, VPI30_DESC, V3_DESC); +SIG_EXPR_LIST_DECL(VPIOB2, VPI, + SIG_EXPR_PTR(VPIOB2, VPI18), SIG_EXPR_PTR(VPIOB2, VPI24), SIG_EXPR_PTR(VPIOB2, VPI30)); -SIG_EXPR_LIST_DECL_SINGLE(NCTS2, NCTS2, V3_DESC); -MS_PIN_DECL(V3, GPIOM0, VPIOB2, NCTS2); +SIG_EXPR_LIST_ALIAS(V3, VPIOB2, VPI); +SIG_EXPR_LIST_DECL_SINGLE(V3, NCTS2, NCTS2, V3_DESC); +PIN_DECL_2(V3, GPIOM0, VPIOB2, NCTS2); FUNC_GROUP_DECL(NCTS2, V3); #define W2 97 #define W2_DESC SIG_DESC_SET(SCU84, 25) -SIG_EXPR_DECL(VPIOB3, VPI18, VPI18_DESC, W2_DESC); -SIG_EXPR_DECL(VPIOB3, VPI24, VPI24_DESC, W2_DESC); -SIG_EXPR_DECL(VPIOB3, VPI30, VPI30_DESC, W2_DESC); -SIG_EXPR_LIST_DECL(VPIOB3, SIG_EXPR_PTR(VPIOB3, VPI18), +SIG_EXPR_DECL_SINGLE(VPIOB3, VPI18, VPI18_DESC, W2_DESC); +SIG_EXPR_DECL_SINGLE(VPIOB3, VPI24, VPI24_DESC, W2_DESC); +SIG_EXPR_DECL_SINGLE(VPIOB3, VPI30, VPI30_DESC, W2_DESC); +SIG_EXPR_LIST_DECL(VPIOB3, VPI, + SIG_EXPR_PTR(VPIOB3, VPI18), SIG_EXPR_PTR(VPIOB3, VPI24), SIG_EXPR_PTR(VPIOB3, VPI30)); -SIG_EXPR_LIST_DECL_SINGLE(NDCD2, NDCD2, W2_DESC); -MS_PIN_DECL(W2, GPIOM1, VPIOB3, NDCD2); +SIG_EXPR_LIST_ALIAS(W2, VPIOB3, VPI); +SIG_EXPR_LIST_DECL_SINGLE(W2, NDCD2, NDCD2, W2_DESC); +PIN_DECL_2(W2, GPIOM1, VPIOB3, NDCD2); FUNC_GROUP_DECL(NDCD2, W2); #define Y1 98 #define Y1_DESC SIG_DESC_SET(SCU84, 26) -SIG_EXPR_DECL(VPIOB4, VPI18, VPI18_DESC, Y1_DESC); -SIG_EXPR_DECL(VPIOB4, VPI24, VPI24_DESC, Y1_DESC); -SIG_EXPR_DECL(VPIOB4, VPI30, VPI30_DESC, Y1_DESC); -SIG_EXPR_LIST_DECL(VPIOB4, SIG_EXPR_PTR(VPIOB4, VPI18), +SIG_EXPR_DECL_SINGLE(VPIOB4, VPI18, VPI18_DESC, Y1_DESC); +SIG_EXPR_DECL_SINGLE(VPIOB4, VPI24, VPI24_DESC, Y1_DESC); +SIG_EXPR_DECL_SINGLE(VPIOB4, VPI30, VPI30_DESC, Y1_DESC); +SIG_EXPR_LIST_DECL(VPIOB4, VPI, + SIG_EXPR_PTR(VPIOB4, VPI18), SIG_EXPR_PTR(VPIOB4, VPI24), SIG_EXPR_PTR(VPIOB4, VPI30)); -SIG_EXPR_LIST_DECL_SINGLE(NDSR2, NDSR2, Y1_DESC); -MS_PIN_DECL(Y1, GPIOM2, VPIOB4, NDSR2); +SIG_EXPR_LIST_ALIAS(Y1, VPIOB4, VPI); +SIG_EXPR_LIST_DECL_SINGLE(Y1, NDSR2, NDSR2, Y1_DESC); +PIN_DECL_2(Y1, GPIOM2, VPIOB4, NDSR2); FUNC_GROUP_DECL(NDSR2, Y1); #define V4 99 #define V4_DESC SIG_DESC_SET(SCU84, 27) -SIG_EXPR_DECL(VPIOB5, VPI18, VPI18_DESC, V4_DESC); -SIG_EXPR_DECL(VPIOB5, VPI24, VPI24_DESC, V4_DESC); -SIG_EXPR_DECL(VPIOB5, VPI30, VPI30_DESC, V4_DESC); -SIG_EXPR_LIST_DECL(VPIOB5, SIG_EXPR_PTR(VPIOB5, VPI18), +SIG_EXPR_DECL_SINGLE(VPIOB5, VPI18, VPI18_DESC, V4_DESC); +SIG_EXPR_DECL_SINGLE(VPIOB5, VPI24, VPI24_DESC, V4_DESC); +SIG_EXPR_DECL_SINGLE(VPIOB5, VPI30, VPI30_DESC, V4_DESC); +SIG_EXPR_LIST_DECL(VPIOB5, VPI, + SIG_EXPR_PTR(VPIOB5, VPI18), SIG_EXPR_PTR(VPIOB5, VPI24), SIG_EXPR_PTR(VPIOB5, VPI30)); -SIG_EXPR_LIST_DECL_SINGLE(NRI2, NRI2, V4_DESC); -MS_PIN_DECL(V4, GPIOM3, VPIOB5, NRI2); +SIG_EXPR_LIST_ALIAS(V4, VPIOB5, VPI); +SIG_EXPR_LIST_DECL_SINGLE(V4, NRI2, NRI2, V4_DESC); +PIN_DECL_2(V4, GPIOM3, VPIOB5, NRI2); FUNC_GROUP_DECL(NRI2, V4); #define W3 100 #define W3_DESC SIG_DESC_SET(SCU84, 28) -SIG_EXPR_DECL(VPIOB6, VPI18, VPI18_DESC, W3_DESC); -SIG_EXPR_DECL(VPIOB6, VPI24, VPI24_DESC, W3_DESC); -SIG_EXPR_DECL(VPIOB6, VPI30, VPI30_DESC, W3_DESC); -SIG_EXPR_LIST_DECL(VPIOB6, SIG_EXPR_PTR(VPIOB6, VPI18), +SIG_EXPR_DECL_SINGLE(VPIOB6, VPI18, VPI18_DESC, W3_DESC); +SIG_EXPR_DECL_SINGLE(VPIOB6, VPI24, VPI24_DESC, W3_DESC); +SIG_EXPR_DECL_SINGLE(VPIOB6, VPI30, VPI30_DESC, W3_DESC); +SIG_EXPR_LIST_DECL(VPIOB6, VPI, + SIG_EXPR_PTR(VPIOB6, VPI18), SIG_EXPR_PTR(VPIOB6, VPI24), SIG_EXPR_PTR(VPIOB6, VPI30)); -SIG_EXPR_LIST_DECL_SINGLE(NDTR2, NDTR2, W3_DESC); -MS_PIN_DECL(W3, GPIOM4, VPIOB6, NDTR2); +SIG_EXPR_LIST_ALIAS(W3, VPIOB6, VPI); +SIG_EXPR_LIST_DECL_SINGLE(W3, NDTR2, NDTR2, W3_DESC); +PIN_DECL_2(W3, GPIOM4, VPIOB6, NDTR2); FUNC_GROUP_DECL(NDTR2, W3); #define Y2 101 #define Y2_DESC SIG_DESC_SET(SCU84, 29) -SIG_EXPR_DECL(VPIOB7, VPI18, VPI18_DESC, Y2_DESC); -SIG_EXPR_DECL(VPIOB7, VPI24, VPI24_DESC, Y2_DESC); -SIG_EXPR_DECL(VPIOB7, VPI30, VPI30_DESC, Y2_DESC); -SIG_EXPR_LIST_DECL(VPIOB7, SIG_EXPR_PTR(VPIOB7, VPI18), +SIG_EXPR_DECL_SINGLE(VPIOB7, VPI18, VPI18_DESC, Y2_DESC); +SIG_EXPR_DECL_SINGLE(VPIOB7, VPI24, VPI24_DESC, Y2_DESC); +SIG_EXPR_DECL_SINGLE(VPIOB7, VPI30, VPI30_DESC, Y2_DESC); +SIG_EXPR_LIST_DECL(VPIOB7, VPI, + SIG_EXPR_PTR(VPIOB7, VPI18), SIG_EXPR_PTR(VPIOB7, VPI24), SIG_EXPR_PTR(VPIOB7, VPI30)); -SIG_EXPR_LIST_DECL_SINGLE(NRTS2, NRTS2, Y2_DESC); -MS_PIN_DECL(Y2, GPIOM5, VPIOB7, NRTS2); +SIG_EXPR_LIST_ALIAS(Y2, VPIOB7, VPI); +SIG_EXPR_LIST_DECL_SINGLE(Y2, NRTS2, NRTS2, Y2_DESC); +PIN_DECL_2(Y2, GPIOM5, VPIOB7, NRTS2); FUNC_GROUP_DECL(NRTS2, Y2); #define AA1 102 #define AA1_DESC SIG_DESC_SET(SCU84, 30) -SIG_EXPR_DECL(VPIOB8, VPI18, VPI18_DESC, AA1_DESC); -SIG_EXPR_DECL(VPIOB8, VPI24, VPI24_DESC, AA1_DESC); -SIG_EXPR_DECL(VPIOB8, VPI30, VPI30_DESC, AA1_DESC); -SIG_EXPR_LIST_DECL(VPIOB8, SIG_EXPR_PTR(VPIOB8, VPI18), +SIG_EXPR_DECL_SINGLE(VPIOB8, VPI18, VPI18_DESC, AA1_DESC); +SIG_EXPR_DECL_SINGLE(VPIOB8, VPI24, VPI24_DESC, AA1_DESC); +SIG_EXPR_DECL_SINGLE(VPIOB8, VPI30, VPI30_DESC, AA1_DESC); +SIG_EXPR_LIST_DECL(VPIOB8, VPI, + SIG_EXPR_PTR(VPIOB8, VPI18), SIG_EXPR_PTR(VPIOB8, VPI24), SIG_EXPR_PTR(VPIOB8, VPI30)); -SIG_EXPR_LIST_DECL_SINGLE(TXD2, TXD2, AA1_DESC); -MS_PIN_DECL(AA1, GPIOM6, VPIOB8, TXD2); +SIG_EXPR_LIST_ALIAS(AA1, VPIOB8, VPI); +SIG_EXPR_LIST_DECL_SINGLE(AA1, TXD2, TXD2, AA1_DESC); +PIN_DECL_2(AA1, GPIOM6, VPIOB8, TXD2); FUNC_GROUP_DECL(TXD2, AA1); #define V5 103 #define V5_DESC SIG_DESC_SET(SCU84, 31) -SIG_EXPR_DECL(VPIOB9, VPI18, VPI18_DESC, V5_DESC); -SIG_EXPR_DECL(VPIOB9, VPI24, VPI24_DESC, V5_DESC); -SIG_EXPR_DECL(VPIOB9, VPI30, VPI30_DESC, V5_DESC); -SIG_EXPR_LIST_DECL(VPIOB9, SIG_EXPR_PTR(VPIOB9, VPI18), +SIG_EXPR_DECL_SINGLE(VPIOB9, VPI18, VPI18_DESC, V5_DESC); +SIG_EXPR_DECL_SINGLE(VPIOB9, VPI24, VPI24_DESC, V5_DESC); +SIG_EXPR_DECL_SINGLE(VPIOB9, VPI30, VPI30_DESC, V5_DESC); +SIG_EXPR_LIST_DECL(VPIOB9, VPI, + SIG_EXPR_PTR(VPIOB9, VPI18), SIG_EXPR_PTR(VPIOB9, VPI24), SIG_EXPR_PTR(VPIOB9, VPI30)); -SIG_EXPR_LIST_DECL_SINGLE(RXD2, RXD2, V5_DESC); -MS_PIN_DECL(V5, GPIOM7, VPIOB9, RXD2); +SIG_EXPR_LIST_ALIAS(V5, VPIOB9, VPI); +SIG_EXPR_LIST_DECL_SINGLE(V5, RXD2, RXD2, V5_DESC); +PIN_DECL_2(V5, GPIOM7, VPIOB9, RXD2); FUNC_GROUP_DECL(RXD2, V5); #define W4 104 #define W4_DESC SIG_DESC_SET(SCU88, 0) -SIG_EXPR_LIST_DECL_SINGLE(VPIG0, VPI30, VPI30_DESC, W4_DESC); -SIG_EXPR_LIST_DECL_SINGLE(PWM0, PWM0, W4_DESC); -MS_PIN_DECL(W4, GPION0, VPIG0, PWM0); +SIG_EXPR_LIST_DECL_SINGLE(W4, VPIG0, VPI30, VPI30_DESC, W4_DESC); +SIG_EXPR_LIST_DECL_SINGLE(W4, PWM0, PWM0, W4_DESC); +PIN_DECL_2(W4, GPION0, VPIG0, PWM0); FUNC_GROUP_DECL(PWM0, W4); #define Y3 105 #define Y3_DESC SIG_DESC_SET(SCU88, 1) -SIG_EXPR_LIST_DECL_SINGLE(VPIG1, VPI30, VPI30_DESC, Y3_DESC); -SIG_EXPR_LIST_DECL_SINGLE(PWM1, PWM1, Y3_DESC); -MS_PIN_DECL(Y3, GPION1, VPIG1, PWM1); +SIG_EXPR_LIST_DECL_SINGLE(Y3, VPIG1, VPI30, VPI30_DESC, Y3_DESC); +SIG_EXPR_LIST_DECL_SINGLE(Y3, PWM1, PWM1, Y3_DESC); +PIN_DECL_2(Y3, GPION1, VPIG1, PWM1); FUNC_GROUP_DECL(PWM1, Y3); #define AA2 106 #define AA2_DESC SIG_DESC_SET(SCU88, 2) -SIG_EXPR_DECL(VPIG2, VPI18, VPI18_DESC, AA2_DESC); -SIG_EXPR_DECL(VPIG2, VPI24, VPI24_DESC, AA2_DESC); -SIG_EXPR_DECL(VPIG2, VPI30, VPI30_DESC, AA2_DESC); -SIG_EXPR_LIST_DECL(VPIG2, SIG_EXPR_PTR(VPIG2, VPI18), +SIG_EXPR_DECL_SINGLE(VPIG2, VPI18, VPI18_DESC, AA2_DESC); +SIG_EXPR_DECL_SINGLE(VPIG2, VPI24, VPI24_DESC, AA2_DESC); +SIG_EXPR_DECL_SINGLE(VPIG2, VPI30, VPI30_DESC, AA2_DESC); +SIG_EXPR_LIST_DECL(VPIG2, VPI, + SIG_EXPR_PTR(VPIG2, VPI18), SIG_EXPR_PTR(VPIG2, VPI24), SIG_EXPR_PTR(VPIG2, VPI30)); -SIG_EXPR_LIST_DECL_SINGLE(PWM2, PWM2, AA2_DESC); -MS_PIN_DECL(AA2, GPION2, VPIG2, PWM2); +SIG_EXPR_LIST_ALIAS(AA2, VPIG2, VPI); +SIG_EXPR_LIST_DECL_SINGLE(AA2, PWM2, PWM2, AA2_DESC); +PIN_DECL_2(AA2, GPION2, VPIG2, PWM2); FUNC_GROUP_DECL(PWM2, AA2); #define AB1 107 #define AB1_DESC SIG_DESC_SET(SCU88, 3) -SIG_EXPR_DECL(VPIG3, VPI18, VPI18_DESC, AB1_DESC); -SIG_EXPR_DECL(VPIG3, VPI24, VPI24_DESC, AB1_DESC); -SIG_EXPR_DECL(VPIG3, VPI30, VPI30_DESC, AB1_DESC); -SIG_EXPR_LIST_DECL(VPIG3, SIG_EXPR_PTR(VPIG3, VPI18), +SIG_EXPR_DECL_SINGLE(VPIG3, VPI18, VPI18_DESC, AB1_DESC); +SIG_EXPR_DECL_SINGLE(VPIG3, VPI24, VPI24_DESC, AB1_DESC); +SIG_EXPR_DECL_SINGLE(VPIG3, VPI30, VPI30_DESC, AB1_DESC); +SIG_EXPR_LIST_DECL(VPIG3, VPI, + SIG_EXPR_PTR(VPIG3, VPI18), SIG_EXPR_PTR(VPIG3, VPI24), SIG_EXPR_PTR(VPIG3, VPI30)); -SIG_EXPR_LIST_DECL_SINGLE(PWM3, PWM3, AB1_DESC); -MS_PIN_DECL(AB1, GPION3, VPIG3, PWM3); +SIG_EXPR_LIST_ALIAS(AB1, VPIG3, VPI); +SIG_EXPR_LIST_DECL_SINGLE(AB1, PWM3, PWM3, AB1_DESC); +PIN_DECL_2(AB1, GPION3, VPIG3, PWM3); FUNC_GROUP_DECL(PWM3, AB1); #define W5 108 #define W5_DESC SIG_DESC_SET(SCU88, 4) -SIG_EXPR_DECL(VPIG4, VPI18, VPI18_DESC, W5_DESC); -SIG_EXPR_DECL(VPIG4, VPI24, VPI24_DESC, W5_DESC); -SIG_EXPR_DECL(VPIG4, VPI30, VPI30_DESC, W5_DESC); -SIG_EXPR_LIST_DECL(VPIG4, SIG_EXPR_PTR(VPIG4, VPI18), +SIG_EXPR_DECL_SINGLE(VPIG4, VPI18, VPI18_DESC, W5_DESC); +SIG_EXPR_DECL_SINGLE(VPIG4, VPI24, VPI24_DESC, W5_DESC); +SIG_EXPR_DECL_SINGLE(VPIG4, VPI30, VPI30_DESC, W5_DESC); +SIG_EXPR_LIST_DECL(VPIG4, VPI, + SIG_EXPR_PTR(VPIG4, VPI18), SIG_EXPR_PTR(VPIG4, VPI24), SIG_EXPR_PTR(VPIG4, VPI30)); -SIG_EXPR_LIST_DECL_SINGLE(PWM4, PWM4, W5_DESC); -MS_PIN_DECL(W5, GPION4, VPIG4, PWM4); +SIG_EXPR_LIST_ALIAS(W5, VPIG4, VPI); +SIG_EXPR_LIST_DECL_SINGLE(W5, PWM4, PWM4, W5_DESC); +PIN_DECL_2(W5, GPION4, VPIG4, PWM4); FUNC_GROUP_DECL(PWM4, W5); #define Y4 109 #define Y4_DESC SIG_DESC_SET(SCU88, 5) -SIG_EXPR_DECL(VPIG5, VPI18, VPI18_DESC, Y4_DESC); -SIG_EXPR_DECL(VPIG5, VPI24, VPI24_DESC, Y4_DESC); -SIG_EXPR_DECL(VPIG5, VPI30, VPI30_DESC, Y4_DESC); -SIG_EXPR_LIST_DECL(VPIG5, SIG_EXPR_PTR(VPIG5, VPI18), +SIG_EXPR_DECL_SINGLE(VPIG5, VPI18, VPI18_DESC, Y4_DESC); +SIG_EXPR_DECL_SINGLE(VPIG5, VPI24, VPI24_DESC, Y4_DESC); +SIG_EXPR_DECL_SINGLE(VPIG5, VPI30, VPI30_DESC, Y4_DESC); +SIG_EXPR_LIST_DECL(VPIG5, VPI, + SIG_EXPR_PTR(VPIG5, VPI18), SIG_EXPR_PTR(VPIG5, VPI24), SIG_EXPR_PTR(VPIG5, VPI30)); -SIG_EXPR_LIST_DECL_SINGLE(PWM5, PWM5, Y4_DESC); -MS_PIN_DECL(Y4, GPION5, VPIG5, PWM5); +SIG_EXPR_LIST_ALIAS(Y4, VPIG5, VPI); +SIG_EXPR_LIST_DECL_SINGLE(Y4, PWM5, PWM5, Y4_DESC); +PIN_DECL_2(Y4, GPION5, VPIG5, PWM5); FUNC_GROUP_DECL(PWM5, Y4); #define AA3 110 #define AA3_DESC SIG_DESC_SET(SCU88, 6) -SIG_EXPR_LIST_DECL_SINGLE(VPIG6, VPI30, VPI30_DESC, AA3_DESC); -SIG_EXPR_LIST_DECL_SINGLE(PWM6, PWM6, AA3_DESC); -MS_PIN_DECL(AA3, GPION6, VPIG6, PWM6); +SIG_EXPR_LIST_DECL_SINGLE(AA3, VPIG6, VPI30, VPI30_DESC, AA3_DESC); +SIG_EXPR_LIST_DECL_SINGLE(AA3, PWM6, PWM6, AA3_DESC); +PIN_DECL_2(AA3, GPION6, VPIG6, PWM6); FUNC_GROUP_DECL(PWM6, AA3); #define AB2 111 #define AB2_DESC SIG_DESC_SET(SCU88, 7) -SIG_EXPR_LIST_DECL_SINGLE(VPIG7, VPI30, VPI30_DESC, AB2_DESC); -SIG_EXPR_LIST_DECL_SINGLE(PWM7, PWM7, AB2_DESC); -MS_PIN_DECL(AB2, GPION7, VPIG7, PWM7); +SIG_EXPR_LIST_DECL_SINGLE(AB2, VPIG7, VPI30, VPI30_DESC, AB2_DESC); +SIG_EXPR_LIST_DECL_SINGLE(AB2, PWM7, PWM7, AB2_DESC); +PIN_DECL_2(AB2, GPION7, VPIG7, PWM7); FUNC_GROUP_DECL(PWM7, AB2); #define V6 112 -SIG_EXPR_LIST_DECL_SINGLE(VPIG8, VPI24, VPI24_DESC, SIG_DESC_SET(SCU88, 8)); -SS_PIN_DECL(V6, GPIOO0, VPIG8); +SIG_EXPR_LIST_DECL_SINGLE(V6, VPIG8, VPI24, VPI24_DESC, SIG_DESC_SET(SCU88, 8)); +PIN_DECL_1(V6, GPIOO0, VPIG8); #define Y5 113 -SIG_EXPR_LIST_DECL_SINGLE(VPIG9, VPI24, VPI24_DESC, SIG_DESC_SET(SCU88, 9)); -SS_PIN_DECL(Y5, GPIOO1, VPIG9); +SIG_EXPR_LIST_DECL_SINGLE(Y5, VPIG9, VPI24, VPI24_DESC, SIG_DESC_SET(SCU88, 9)); +PIN_DECL_1(Y5, GPIOO1, VPIG9); #define AA4 114 -SIG_EXPR_LIST_DECL_SINGLE(VPIR0, VPI30, VPI30_DESC, SIG_DESC_SET(SCU88, 10)); -SS_PIN_DECL(AA4, GPIOO2, VPIR0); +SIG_EXPR_LIST_DECL_SINGLE(AA4, VPIR0, VPI30, VPI30_DESC, + SIG_DESC_SET(SCU88, 10)); +PIN_DECL_1(AA4, GPIOO2, VPIR0); #define AB3 115 -SIG_EXPR_LIST_DECL_SINGLE(VPIR1, VPI30, VPI30_DESC, SIG_DESC_SET(SCU88, 11)); -SS_PIN_DECL(AB3, GPIOO3, VPIR1); +SIG_EXPR_LIST_DECL_SINGLE(AB3, VPIR1, VPI30, VPI30_DESC, + SIG_DESC_SET(SCU88, 11)); +PIN_DECL_1(AB3, GPIOO3, VPIR1); #define W6 116 -SIG_EXPR_LIST_DECL_SINGLE(VPIR2, VPI24, VPI24_DESC, SIG_DESC_SET(SCU88, 12)); -SS_PIN_DECL(W6, GPIOO4, VPIR2); +SIG_EXPR_LIST_DECL_SINGLE(W6, VPIR2, VPI24, VPI24_DESC, + SIG_DESC_SET(SCU88, 12)); +PIN_DECL_1(W6, GPIOO4, VPIR2); #define AA5 117 -SIG_EXPR_LIST_DECL_SINGLE(VPIR3, VPI24, VPI24_DESC, SIG_DESC_SET(SCU88, 13)); -SS_PIN_DECL(AA5, GPIOO5, VPIR3); +SIG_EXPR_LIST_DECL_SINGLE(AA5, VPIR3, VPI24, VPI24_DESC, + SIG_DESC_SET(SCU88, 13)); +PIN_DECL_1(AA5, GPIOO5, VPIR3); #define AB4 118 -SIG_EXPR_LIST_DECL_SINGLE(VPIR4, VPI24, VPI24_DESC, SIG_DESC_SET(SCU88, 14)); -SS_PIN_DECL(AB4, GPIOO6, VPIR4); +SIG_EXPR_LIST_DECL_SINGLE(AB4, VPIR4, VPI24, VPI24_DESC, + SIG_DESC_SET(SCU88, 14)); +PIN_DECL_1(AB4, GPIOO6, VPIR4); #define V7 119 -SIG_EXPR_LIST_DECL_SINGLE(VPIR5, VPI24, VPI24_DESC, SIG_DESC_SET(SCU88, 15)); -SS_PIN_DECL(V7, GPIOO7, VPIR5); +SIG_EXPR_LIST_DECL_SINGLE(V7, VPIR5, VPI24, VPI24_DESC, + SIG_DESC_SET(SCU88, 15)); +PIN_DECL_1(V7, GPIOO7, VPIR5); #define Y6 120 -SIG_EXPR_LIST_DECL_SINGLE(VPIR6, VPI24, VPI24_DESC, SIG_DESC_SET(SCU88, 16)); -SS_PIN_DECL(Y6, GPIOP0, VPIR6); +SIG_EXPR_LIST_DECL_SINGLE(Y6, VPIR6, VPI24, VPI24_DESC, + SIG_DESC_SET(SCU88, 16)); +PIN_DECL_1(Y6, GPIOP0, VPIR6); #define AB5 121 -SIG_EXPR_LIST_DECL_SINGLE(VPIR7, VPI24, VPI24_DESC, SIG_DESC_SET(SCU88, 17)); -SS_PIN_DECL(AB5, GPIOP1, VPIR7); +SIG_EXPR_LIST_DECL_SINGLE(AB5, VPIR7, VPI24, VPI24_DESC, + SIG_DESC_SET(SCU88, 17)); +PIN_DECL_1(AB5, GPIOP1, VPIR7); #define W7 122 -SIG_EXPR_LIST_DECL_SINGLE(VPIR8, VPI24, VPI24_DESC, SIG_DESC_SET(SCU88, 18)); -SS_PIN_DECL(W7, GPIOP2, VPIR8); +SIG_EXPR_LIST_DECL_SINGLE(W7, VPIR8, VPI24, VPI24_DESC, + SIG_DESC_SET(SCU88, 18)); +PIN_DECL_1(W7, GPIOP2, VPIR8); #define AA6 123 -SIG_EXPR_LIST_DECL_SINGLE(VPIR9, VPI24, VPI24_DESC, SIG_DESC_SET(SCU88, 19)); -SS_PIN_DECL(AA6, GPIOP3, VPIR9); +SIG_EXPR_LIST_DECL_SINGLE(AA6, VPIR9, VPI24, VPI24_DESC, + SIG_DESC_SET(SCU88, 19)); +PIN_DECL_1(AA6, GPIOP3, VPIR9); FUNC_GROUP_DECL(VPI18, T5, U3, V1, U4, V2, V3, W2, Y1, V4, W3, Y2, AA1, V5, AA22, W5, Y4, AA3, AB2); @@ -979,12 +1038,12 @@ FUNC_GROUP_DECL(VPI30, T5, U3, V1, U4, V2, W1, U5, V3, W2, Y1, V4, W3, Y2, AA1, V5, W4, Y3, AA22, W5, Y4, AA3, AB2, AA4, AB3); #define AB6 124 -SIG_EXPR_LIST_DECL_SINGLE(GPIOP4, GPIOP4); -MS_PIN_DECL_(AB6, SIG_EXPR_LIST_PTR(GPIOP4)); +SIG_EXPR_LIST_DECL_SINGLE(AB6, GPIOP4, GPIOP4); +PIN_DECL_(AB6, SIG_EXPR_LIST_PTR(AB6, GPIOP4)); #define Y7 125 -SIG_EXPR_LIST_DECL_SINGLE(GPIOP5, GPIOP5); -MS_PIN_DECL_(Y7, SIG_EXPR_LIST_PTR(GPIOP5)); +SIG_EXPR_LIST_DECL_SINGLE(Y7, GPIOP5, GPIOP5); +PIN_DECL_(Y7, SIG_EXPR_LIST_PTR(Y7, GPIOP5)); #define AA7 126 SSSF_PIN_DECL(AA7, GPIOP6, BMCINT, SIG_DESC_SET(SCU88, 22)); @@ -995,36 +1054,36 @@ SSSF_PIN_DECL(AB7, GPIOP7, FLACK, SIG_DESC_SET(SCU88, 23)); #define I2C3_DESC SIG_DESC_SET(SCU90, 16) #define D3 128 -SIG_EXPR_LIST_DECL_SINGLE(SCL3, I2C3, I2C3_DESC); -SS_PIN_DECL(D3, GPIOQ0, SCL3); +SIG_EXPR_LIST_DECL_SINGLE(D3, SCL3, I2C3, I2C3_DESC); +PIN_DECL_1(D3, GPIOQ0, SCL3); #define C2 129 -SIG_EXPR_LIST_DECL_SINGLE(SDA3, I2C3, I2C3_DESC); -SS_PIN_DECL(C2, GPIOQ1, SDA3); +SIG_EXPR_LIST_DECL_SINGLE(C2, SDA3, I2C3, I2C3_DESC); +PIN_DECL_1(C2, GPIOQ1, SDA3); FUNC_GROUP_DECL(I2C3, D3, C2); #define I2C4_DESC SIG_DESC_SET(SCU90, 17) #define B1 130 -SIG_EXPR_LIST_DECL_SINGLE(SCL4, I2C4, I2C4_DESC); -SS_PIN_DECL(B1, GPIOQ2, SCL4); +SIG_EXPR_LIST_DECL_SINGLE(B1, SCL4, I2C4, I2C4_DESC); +PIN_DECL_1(B1, GPIOQ2, SCL4); #define F5 131 -SIG_EXPR_LIST_DECL_SINGLE(SDA4, I2C4, I2C4_DESC); -SS_PIN_DECL(F5, GPIOQ3, SDA4); +SIG_EXPR_LIST_DECL_SINGLE(F5, SDA4, I2C4, I2C4_DESC); +PIN_DECL_1(F5, GPIOQ3, SDA4); FUNC_GROUP_DECL(I2C4, B1, F5); #define I2C14_DESC SIG_DESC_SET(SCU90, 27) #define H4 132 -SIG_EXPR_LIST_DECL_SINGLE(SCL14, I2C14, I2C14_DESC); -SS_PIN_DECL(H4, GPIOQ4, SCL14); +SIG_EXPR_LIST_DECL_SINGLE(H4, SCL14, I2C14, I2C14_DESC); +PIN_DECL_1(H4, GPIOQ4, SCL14); #define H3 133 -SIG_EXPR_LIST_DECL_SINGLE(SDA14, I2C14, I2C14_DESC); -SS_PIN_DECL(H3, GPIOQ5, SDA14); +SIG_EXPR_LIST_DECL_SINGLE(H3, SDA14, I2C14, I2C14_DESC); +PIN_DECL_1(H3, GPIOQ5, SDA14); FUNC_GROUP_DECL(I2C14, H4, H3); @@ -1039,12 +1098,12 @@ FUNC_GROUP_DECL(I2C14, H4, H3); #define USB11H3_DESC SIG_DESC_SET(SCU90, 28) #define H2 134 -SIG_EXPR_LIST_DECL_SINGLE(USB11HDP3, USB11H3, USB11H3_DESC); -SS_PIN_DECL(H2, GPIOQ6, USB11HDP3); +SIG_EXPR_LIST_DECL_SINGLE(H2, USB11HDP3, USB11H3, USB11H3_DESC); +PIN_DECL_1(H2, GPIOQ6, USB11HDP3); #define H1 135 -SIG_EXPR_LIST_DECL_SINGLE(USB11HDN3, USB11H3, USB11H3_DESC); -SS_PIN_DECL(H1, GPIOQ7, USB11HDN3); +SIG_EXPR_LIST_DECL_SINGLE(H1, USB11HDN3, USB11H3, USB11H3_DESC); +PIN_DECL_1(H1, GPIOQ7, USB11HDN3); #define V20 136 SSSF_PIN_DECL(V20, GPIOR0, ROMCS1, SIG_DESC_SET(SCU88, 24)); @@ -1067,303 +1126,333 @@ SSSF_PIN_DECL(U19, GPIOR3, ROMCS4, SIG_DESC_SET(SCU88, 27)); #define V21 140 #define V21_DESC SIG_DESC_SET(SCU88, 28) -SIG_EXPR_DECL(ROMA24, ROM8, V21_DESC, VPO_OFF_12); -SIG_EXPR_DECL(ROMA24, ROM16, V21_DESC, VPO_OFF_12); -SIG_EXPR_DECL(ROMA24, ROM16S, V21_DESC, VPO_OFF_12); -SIG_EXPR_LIST_DECL(ROMA24, SIG_EXPR_PTR(ROMA24, ROM8), +SIG_EXPR_DECL_SINGLE(ROMA24, ROM8, V21_DESC, VPO_OFF_12); +SIG_EXPR_DECL_SINGLE(ROMA24, ROM16, V21_DESC, VPO_OFF_12); +SIG_EXPR_DECL_SINGLE(ROMA24, ROM16S, V21_DESC, VPO_OFF_12); +SIG_EXPR_LIST_DECL(ROMA24, ROM, + SIG_EXPR_PTR(ROMA24, ROM8), SIG_EXPR_PTR(ROMA24, ROM16), SIG_EXPR_PTR(ROMA24, ROM16S)); -SIG_EXPR_LIST_DECL_SINGLE(VPOR6, VPO24, V21_DESC, VPO_24_OFF); -MS_PIN_DECL(V21, GPIOR4, ROMA24, VPOR6); +SIG_EXPR_LIST_ALIAS(V21, ROMA24, ROM); +SIG_EXPR_LIST_DECL_SINGLE(V21, VPOR6, VPO24, V21_DESC, VPO_24_OFF); +PIN_DECL_2(V21, GPIOR4, ROMA24, VPOR6); #define W22 141 #define W22_DESC SIG_DESC_SET(SCU88, 29) -SIG_EXPR_DECL(ROMA25, ROM8, W22_DESC, VPO_OFF_12); -SIG_EXPR_DECL(ROMA25, ROM16, W22_DESC, VPO_OFF_12); -SIG_EXPR_DECL(ROMA25, ROM16S, W22_DESC, VPO_OFF_12); -SIG_EXPR_LIST_DECL(ROMA25, SIG_EXPR_PTR(ROMA25, ROM8), +SIG_EXPR_DECL_SINGLE(ROMA25, ROM8, W22_DESC, VPO_OFF_12); +SIG_EXPR_DECL_SINGLE(ROMA25, ROM16, W22_DESC, VPO_OFF_12); +SIG_EXPR_DECL_SINGLE(ROMA25, ROM16S, W22_DESC, VPO_OFF_12); +SIG_EXPR_LIST_DECL(ROMA25, ROM, + SIG_EXPR_PTR(ROMA25, ROM8), SIG_EXPR_PTR(ROMA25, ROM16), SIG_EXPR_PTR(ROMA25, ROM16S)); -SIG_EXPR_LIST_DECL_SINGLE(VPOR7, VPO24, W22_DESC, VPO_24_OFF); -MS_PIN_DECL(W22, GPIOR5, ROMA25, VPOR7); +SIG_EXPR_LIST_ALIAS(W22, ROMA25, ROM); +SIG_EXPR_LIST_DECL_SINGLE(W22, VPOR7, VPO24, W22_DESC, VPO_24_OFF); +PIN_DECL_2(W22, GPIOR5, ROMA25, VPOR7); #define C6 142 -SIG_EXPR_LIST_DECL_SINGLE(MDC1, MDIO1, SIG_DESC_SET(SCU88, 30)); -SS_PIN_DECL(C6, GPIOR6, MDC1); +SIG_EXPR_LIST_DECL_SINGLE(C6, MDC1, MDIO1, SIG_DESC_SET(SCU88, 30)); +PIN_DECL_1(C6, GPIOR6, MDC1); #define A5 143 -SIG_EXPR_LIST_DECL_SINGLE(MDIO1, MDIO1, SIG_DESC_SET(SCU88, 31)); -SS_PIN_DECL(A5, GPIOR7, MDIO1); +SIG_EXPR_LIST_DECL_SINGLE(A5, MDIO1, MDIO1, SIG_DESC_SET(SCU88, 31)); +PIN_DECL_1(A5, GPIOR7, MDIO1); FUNC_GROUP_DECL(MDIO1, C6, A5); #define U21 144 #define U21_DESC SIG_DESC_SET(SCU8C, 0) -SIG_EXPR_DECL(ROMD4, ROM8, U21_DESC, VPOOFF0_DESC); -SIG_EXPR_DECL(ROMD4, ROM16, U21_DESC, VPOOFF0_DESC); -SIG_EXPR_DECL(ROMD4, ROM16S, U21_DESC, VPOOFF0_DESC); -SIG_EXPR_LIST_DECL(ROMD4, SIG_EXPR_PTR(ROMD4, ROM8), +SIG_EXPR_DECL_SINGLE(ROMD4, ROM8, U21_DESC, VPOOFF0_DESC); +SIG_EXPR_DECL_SINGLE(ROMD4, ROM16, U21_DESC, VPOOFF0_DESC); +SIG_EXPR_DECL_SINGLE(ROMD4, ROM16S, U21_DESC, VPOOFF0_DESC); +SIG_EXPR_LIST_DECL(ROMD4, ROM, + SIG_EXPR_PTR(ROMD4, ROM8), SIG_EXPR_PTR(ROMD4, ROM16), SIG_EXPR_PTR(ROMD4, ROM16S)); -SIG_EXPR_DECL(VPODE, VPO12, U21_DESC, VPO12_DESC); -SIG_EXPR_DECL(VPODE, VPO24, U21_DESC, VPO12_DESC); -SIG_EXPR_LIST_DECL_DUAL(VPODE, VPO12, VPO24); -MS_PIN_DECL(U21, GPIOS0, ROMD4, VPODE); +SIG_EXPR_LIST_ALIAS(U21, ROMD4, ROM); +SIG_EXPR_DECL_SINGLE(VPODE, VPO12, U21_DESC, VPO12_DESC); +SIG_EXPR_DECL_SINGLE(VPODE, VPO24, U21_DESC, VPO12_DESC); +SIG_EXPR_LIST_DECL_DUAL(U21, VPODE, VPO12, VPO24); +PIN_DECL_2(U21, GPIOS0, ROMD4, VPODE); #define T19 145 #define T19_DESC SIG_DESC_SET(SCU8C, 1) -SIG_EXPR_DECL(ROMD5, ROM8, T19_DESC, VPOOFF0_DESC); -SIG_EXPR_DECL(ROMD5, ROM16, T19_DESC, VPOOFF0_DESC); -SIG_EXPR_DECL(ROMD5, ROM16S, T19_DESC, VPOOFF0_DESC); -SIG_EXPR_LIST_DECL(ROMD5, SIG_EXPR_PTR(ROMD5, ROM8), +SIG_EXPR_DECL_SINGLE(ROMD5, ROM8, T19_DESC, VPOOFF0_DESC); +SIG_EXPR_DECL_SINGLE(ROMD5, ROM16, T19_DESC, VPOOFF0_DESC); +SIG_EXPR_DECL_SINGLE(ROMD5, ROM16S, T19_DESC, VPOOFF0_DESC); +SIG_EXPR_LIST_DECL(ROMD5, ROM, + SIG_EXPR_PTR(ROMD5, ROM8), SIG_EXPR_PTR(ROMD5, ROM16), SIG_EXPR_PTR(ROMD5, ROM16S)); -SIG_EXPR_DECL(VPOHS, VPO12, T19_DESC, VPO12_DESC); -SIG_EXPR_DECL(VPOHS, VPO24, T19_DESC, VPO24_DESC); -SIG_EXPR_LIST_DECL_DUAL(VPOHS, VPO12, VPO24); -MS_PIN_DECL(T19, GPIOS1, ROMD5, VPOHS); +SIG_EXPR_LIST_ALIAS(T19, ROMD5, ROM); +SIG_EXPR_DECL_SINGLE(VPOHS, VPO12, T19_DESC, VPO12_DESC); +SIG_EXPR_DECL_SINGLE(VPOHS, VPO24, T19_DESC, VPO24_DESC); +SIG_EXPR_LIST_DECL_DUAL(T19, VPOHS, VPO12, VPO24); +PIN_DECL_2(T19, GPIOS1, ROMD5, VPOHS); #define V22 146 #define V22_DESC SIG_DESC_SET(SCU8C, 2) -SIG_EXPR_DECL(ROMD6, ROM8, V22_DESC, VPOOFF0_DESC); -SIG_EXPR_DECL(ROMD6, ROM16, V22_DESC, VPOOFF0_DESC); -SIG_EXPR_DECL(ROMD6, ROM16S, V22_DESC, VPOOFF0_DESC); -SIG_EXPR_LIST_DECL(ROMD6, SIG_EXPR_PTR(ROMD6, ROM8), +SIG_EXPR_DECL_SINGLE(ROMD6, ROM8, V22_DESC, VPOOFF0_DESC); +SIG_EXPR_DECL_SINGLE(ROMD6, ROM16, V22_DESC, VPOOFF0_DESC); +SIG_EXPR_DECL_SINGLE(ROMD6, ROM16S, V22_DESC, VPOOFF0_DESC); +SIG_EXPR_LIST_DECL(ROMD6, ROM, + SIG_EXPR_PTR(ROMD6, ROM8), SIG_EXPR_PTR(ROMD6, ROM16), SIG_EXPR_PTR(ROMD6, ROM16S)); -SIG_EXPR_DECL(VPOVS, VPO12, V22_DESC, VPO12_DESC); -SIG_EXPR_DECL(VPOVS, VPO24, V22_DESC, VPO24_DESC); -SIG_EXPR_LIST_DECL_DUAL(VPOVS, VPO12, VPO24); -MS_PIN_DECL(V22, GPIOS2, ROMD6, VPOVS); +SIG_EXPR_LIST_ALIAS(V22, ROMD6, ROM); +SIG_EXPR_DECL_SINGLE(VPOVS, VPO12, V22_DESC, VPO12_DESC); +SIG_EXPR_DECL_SINGLE(VPOVS, VPO24, V22_DESC, VPO24_DESC); +SIG_EXPR_LIST_DECL_DUAL(V22, VPOVS, VPO12, VPO24); +PIN_DECL_2(V22, GPIOS2, ROMD6, VPOVS); #define U20 147 #define U20_DESC SIG_DESC_SET(SCU8C, 3) -SIG_EXPR_DECL(ROMD7, ROM8, U20_DESC, VPOOFF0_DESC); -SIG_EXPR_DECL(ROMD7, ROM16, U20_DESC, VPOOFF0_DESC); -SIG_EXPR_DECL(ROMD7, ROM16S, U20_DESC, VPOOFF0_DESC); -SIG_EXPR_LIST_DECL(ROMD7, SIG_EXPR_PTR(ROMD7, ROM8), +SIG_EXPR_DECL_SINGLE(ROMD7, ROM8, U20_DESC, VPOOFF0_DESC); +SIG_EXPR_DECL_SINGLE(ROMD7, ROM16, U20_DESC, VPOOFF0_DESC); +SIG_EXPR_DECL_SINGLE(ROMD7, ROM16S, U20_DESC, VPOOFF0_DESC); +SIG_EXPR_LIST_DECL(ROMD7, ROM, + SIG_EXPR_PTR(ROMD7, ROM8), SIG_EXPR_PTR(ROMD7, ROM16), SIG_EXPR_PTR(ROMD7, ROM16S)); -SIG_EXPR_DECL(VPOCLK, VPO12, U20_DESC, VPO12_DESC); -SIG_EXPR_DECL(VPOCLK, VPO24, U20_DESC, VPO24_DESC); -SIG_EXPR_LIST_DECL_DUAL(VPOCLK, VPO12, VPO24); -MS_PIN_DECL(U20, GPIOS3, ROMD7, VPOCLK); +SIG_EXPR_LIST_ALIAS(U20, ROMD7, ROM); +SIG_EXPR_DECL_SINGLE(VPOCLK, VPO12, U20_DESC, VPO12_DESC); +SIG_EXPR_DECL_SINGLE(VPOCLK, VPO24, U20_DESC, VPO24_DESC); +SIG_EXPR_LIST_DECL_DUAL(U20, VPOCLK, VPO12, VPO24); +PIN_DECL_2(U20, GPIOS3, ROMD7, VPOCLK); #define R18 148 #define ROMOE_DESC SIG_DESC_SET(SCU8C, 4) -SIG_EXPR_LIST_DECL_SINGLE(GPIOS4, GPIOS4); -SIG_EXPR_DECL(ROMOE, ROM8, ROMOE_DESC); -SIG_EXPR_DECL(ROMOE, ROM16, ROMOE_DESC); -SIG_EXPR_DECL(ROMOE, ROM16S, ROMOE_DESC); -SIG_EXPR_LIST_DECL(ROMOE, SIG_EXPR_PTR(ROMOE, ROM8), +SIG_EXPR_LIST_DECL_SINGLE(R18, GPIOS4, GPIOS4); +SIG_EXPR_DECL_SINGLE(ROMOE, ROM8, ROMOE_DESC); +SIG_EXPR_DECL_SINGLE(ROMOE, ROM16, ROMOE_DESC); +SIG_EXPR_DECL_SINGLE(ROMOE, ROM16S, ROMOE_DESC); +SIG_EXPR_LIST_DECL(ROMOE, ROM, + SIG_EXPR_PTR(ROMOE, ROM8), SIG_EXPR_PTR(ROMOE, ROM16), SIG_EXPR_PTR(ROMOE, ROM16S)); -MS_PIN_DECL_(R18, SIG_EXPR_LIST_PTR(ROMOE), SIG_EXPR_LIST_PTR(GPIOS4)); +SIG_EXPR_LIST_ALIAS(R18, ROMOE, ROM); +PIN_DECL_(R18, SIG_EXPR_LIST_PTR(R18, ROMOE), SIG_EXPR_LIST_PTR(R18, GPIOS4)); #define N21 149 #define ROMWE_DESC SIG_DESC_SET(SCU8C, 5) -SIG_EXPR_LIST_DECL_SINGLE(GPIOS5, GPIOS5); -SIG_EXPR_DECL(ROMWE, ROM8, ROMWE_DESC); -SIG_EXPR_DECL(ROMWE, ROM16, ROMWE_DESC); -SIG_EXPR_DECL(ROMWE, ROM16S, ROMWE_DESC); -SIG_EXPR_LIST_DECL(ROMWE, SIG_EXPR_PTR(ROMWE, ROM8), +SIG_EXPR_LIST_DECL_SINGLE(N21, GPIOS5, GPIOS5); +SIG_EXPR_DECL_SINGLE(ROMWE, ROM8, ROMWE_DESC); +SIG_EXPR_DECL_SINGLE(ROMWE, ROM16, ROMWE_DESC); +SIG_EXPR_DECL_SINGLE(ROMWE, ROM16S, ROMWE_DESC); +SIG_EXPR_LIST_DECL(ROMWE, ROM, + SIG_EXPR_PTR(ROMWE, ROM8), SIG_EXPR_PTR(ROMWE, ROM16), SIG_EXPR_PTR(ROMWE, ROM16S)); -MS_PIN_DECL_(N21, SIG_EXPR_LIST_PTR(ROMWE), SIG_EXPR_LIST_PTR(GPIOS5)); +SIG_EXPR_LIST_ALIAS(N21, ROMWE, ROM); +PIN_DECL_(N21, SIG_EXPR_LIST_PTR(N21, ROMWE), SIG_EXPR_LIST_PTR(N21, GPIOS5)); #define L22 150 #define L22_DESC SIG_DESC_SET(SCU8C, 6) -SIG_EXPR_DECL(ROMA22, ROM8, L22_DESC, VPO_OFF_12); -SIG_EXPR_DECL(ROMA22, ROM16, L22_DESC, VPO_OFF_12); -SIG_EXPR_DECL(ROMA22, ROM16S, L22_DESC, VPO_OFF_12); -SIG_EXPR_LIST_DECL(ROMA22, SIG_EXPR_PTR(ROMA22, ROM8), +SIG_EXPR_DECL_SINGLE(ROMA22, ROM8, L22_DESC, VPO_OFF_12); +SIG_EXPR_DECL_SINGLE(ROMA22, ROM16, L22_DESC, VPO_OFF_12); +SIG_EXPR_DECL_SINGLE(ROMA22, ROM16S, L22_DESC, VPO_OFF_12); +SIG_EXPR_LIST_DECL(ROMA22, ROM, + SIG_EXPR_PTR(ROMA22, ROM8), SIG_EXPR_PTR(ROMA22, ROM16), SIG_EXPR_PTR(ROMA22, ROM16S)); -SIG_EXPR_LIST_DECL_SINGLE(VPOR4, VPO24, L22_DESC, VPO_24_OFF); -MS_PIN_DECL(L22, GPIOS6, ROMA22, VPOR4); +SIG_EXPR_LIST_ALIAS(L22, ROMA22, ROM); +SIG_EXPR_LIST_DECL_SINGLE(L22, VPOR4, VPO24, L22_DESC, VPO_24_OFF); +PIN_DECL_2(L22, GPIOS6, ROMA22, VPOR4); #define K18 151 #define K18_DESC SIG_DESC_SET(SCU8C, 7) -SIG_EXPR_DECL(ROMA23, ROM8, K18_DESC, VPO_OFF_12); -SIG_EXPR_DECL(ROMA23, ROM16, K18_DESC, VPO_OFF_12); -SIG_EXPR_DECL(ROMA23, ROM16S, K18_DESC, VPO_OFF_12); -SIG_EXPR_LIST_DECL(ROMA23, SIG_EXPR_PTR(ROMA23, ROM8), +SIG_EXPR_DECL_SINGLE(ROMA23, ROM8, K18_DESC, VPO_OFF_12); +SIG_EXPR_DECL_SINGLE(ROMA23, ROM16, K18_DESC, VPO_OFF_12); +SIG_EXPR_DECL_SINGLE(ROMA23, ROM16S, K18_DESC, VPO_OFF_12); +SIG_EXPR_LIST_DECL(ROMA23, ROM, + SIG_EXPR_PTR(ROMA23, ROM8), SIG_EXPR_PTR(ROMA23, ROM16), SIG_EXPR_PTR(ROMA23, ROM16S)); -SIG_EXPR_LIST_DECL_SINGLE(VPOR5, VPO24, K18_DESC, VPO_24_OFF); -MS_PIN_DECL(K18, GPIOS7, ROMA23, VPOR5); +SIG_EXPR_LIST_ALIAS(K18, ROMA23, ROM); +SIG_EXPR_LIST_DECL_SINGLE(K18, VPOR5, VPO24, K18_DESC, VPO_24_OFF); +PIN_DECL_2(K18, GPIOS7, ROMA23, VPOR5); #define RMII1_DESC SIG_DESC_BIT(HW_STRAP1, 6, 0) #define A12 152 -SIG_EXPR_LIST_DECL_SINGLE(GPIOT0, GPIOT0, SIG_DESC_SET(SCUA0, 0)); -SIG_EXPR_LIST_DECL_SINGLE(RMII1TXEN, RMII1, RMII1_DESC); -SIG_EXPR_LIST_DECL_SINGLE(RGMII1TXCK, RGMII1); -MS_PIN_DECL_(A12, SIG_EXPR_LIST_PTR(GPIOT0), SIG_EXPR_LIST_PTR(RMII1TXEN), - SIG_EXPR_LIST_PTR(RGMII1TXCK)); +SIG_EXPR_LIST_DECL_SINGLE(A12, GPIOT0, GPIOT0, SIG_DESC_SET(SCUA0, 0)); +SIG_EXPR_LIST_DECL_SINGLE(A12, RMII1TXEN, RMII1, RMII1_DESC); +SIG_EXPR_LIST_DECL_SINGLE(A12, RGMII1TXCK, RGMII1); +PIN_DECL_(A12, SIG_EXPR_LIST_PTR(A12, GPIOT0), + SIG_EXPR_LIST_PTR(A12, RMII1TXEN), + SIG_EXPR_LIST_PTR(A12, RGMII1TXCK)); #define B12 153 -SIG_EXPR_LIST_DECL_SINGLE(GPIOT1, GPIOT1, SIG_DESC_SET(SCUA0, 1)); -SIG_EXPR_LIST_DECL_SINGLE(DASHB12, RMII1, RMII1_DESC); -SIG_EXPR_LIST_DECL_SINGLE(RGMII1TXCTL, RGMII1); -MS_PIN_DECL_(B12, SIG_EXPR_LIST_PTR(GPIOT1), SIG_EXPR_LIST_PTR(DASHB12), - SIG_EXPR_LIST_PTR(RGMII1TXCTL)); +SIG_EXPR_LIST_DECL_SINGLE(B12, GPIOT1, GPIOT1, SIG_DESC_SET(SCUA0, 1)); +SIG_EXPR_LIST_DECL_SINGLE(B12, DASHB12, RMII1, RMII1_DESC); +SIG_EXPR_LIST_DECL_SINGLE(B12, RGMII1TXCTL, RGMII1); +PIN_DECL_(B12, SIG_EXPR_LIST_PTR(B12, GPIOT1), SIG_EXPR_LIST_PTR(B12, DASHB12), + SIG_EXPR_LIST_PTR(B12, RGMII1TXCTL)); #define C12 154 -SIG_EXPR_LIST_DECL_SINGLE(GPIOT2, GPIOT2, SIG_DESC_SET(SCUA0, 2)); -SIG_EXPR_LIST_DECL_SINGLE(RMII1TXD0, RMII1, RMII1_DESC); -SIG_EXPR_LIST_DECL_SINGLE(RGMII1TXD0, RGMII1); -MS_PIN_DECL_(C12, SIG_EXPR_LIST_PTR(GPIOT2), SIG_EXPR_LIST_PTR(RMII1TXD0), - SIG_EXPR_LIST_PTR(RGMII1TXD0)); +SIG_EXPR_LIST_DECL_SINGLE(C12, GPIOT2, GPIOT2, SIG_DESC_SET(SCUA0, 2)); +SIG_EXPR_LIST_DECL_SINGLE(C12, RMII1TXD0, RMII1, RMII1_DESC); +SIG_EXPR_LIST_DECL_SINGLE(C12, RGMII1TXD0, RGMII1); +PIN_DECL_(C12, SIG_EXPR_LIST_PTR(C12, GPIOT2), + SIG_EXPR_LIST_PTR(C12, RMII1TXD0), + SIG_EXPR_LIST_PTR(C12, RGMII1TXD0)); #define D12 155 -SIG_EXPR_LIST_DECL_SINGLE(GPIOT3, GPIOT3, SIG_DESC_SET(SCUA0, 3)); -SIG_EXPR_LIST_DECL_SINGLE(RMII1TXD1, RMII1, RMII1_DESC); -SIG_EXPR_LIST_DECL_SINGLE(RGMII1TXD1, RGMII1); -MS_PIN_DECL_(D12, SIG_EXPR_LIST_PTR(GPIOT3), SIG_EXPR_LIST_PTR(RMII1TXD1), - SIG_EXPR_LIST_PTR(RGMII1TXD1)); +SIG_EXPR_LIST_DECL_SINGLE(D12, GPIOT3, GPIOT3, SIG_DESC_SET(SCUA0, 3)); +SIG_EXPR_LIST_DECL_SINGLE(D12, RMII1TXD1, RMII1, RMII1_DESC); +SIG_EXPR_LIST_DECL_SINGLE(D12, RGMII1TXD1, RGMII1); +PIN_DECL_(D12, SIG_EXPR_LIST_PTR(D12, GPIOT3), + SIG_EXPR_LIST_PTR(D12, RMII1TXD1), + SIG_EXPR_LIST_PTR(D12, RGMII1TXD1)); #define E12 156 -SIG_EXPR_LIST_DECL_SINGLE(GPIOT4, GPIOT4, SIG_DESC_SET(SCUA0, 4)); -SIG_EXPR_LIST_DECL_SINGLE(DASHE12, RMII1, RMII1_DESC); -SIG_EXPR_LIST_DECL_SINGLE(RGMII1TXD2, RGMII1); -MS_PIN_DECL_(E12, SIG_EXPR_LIST_PTR(GPIOT4), SIG_EXPR_LIST_PTR(DASHE12), - SIG_EXPR_LIST_PTR(RGMII1TXD2)); +SIG_EXPR_LIST_DECL_SINGLE(E12, GPIOT4, GPIOT4, SIG_DESC_SET(SCUA0, 4)); +SIG_EXPR_LIST_DECL_SINGLE(E12, DASHE12, RMII1, RMII1_DESC); +SIG_EXPR_LIST_DECL_SINGLE(E12, RGMII1TXD2, RGMII1); +PIN_DECL_(E12, SIG_EXPR_LIST_PTR(E12, GPIOT4), SIG_EXPR_LIST_PTR(E12, DASHE12), + SIG_EXPR_LIST_PTR(E12, RGMII1TXD2)); #define A13 157 -SIG_EXPR_LIST_DECL_SINGLE(GPIOT5, GPIOT5, SIG_DESC_SET(SCUA0, 5)); -SIG_EXPR_LIST_DECL_SINGLE(DASHA13, RMII1, RMII1_DESC); -SIG_EXPR_LIST_DECL_SINGLE(RGMII1TXD3, RGMII1); -MS_PIN_DECL_(A13, SIG_EXPR_LIST_PTR(GPIOT5), SIG_EXPR_LIST_PTR(DASHA13), - SIG_EXPR_LIST_PTR(RGMII1TXD3)); +SIG_EXPR_LIST_DECL_SINGLE(A13, GPIOT5, GPIOT5, SIG_DESC_SET(SCUA0, 5)); +SIG_EXPR_LIST_DECL_SINGLE(A13, DASHA13, RMII1, RMII1_DESC); +SIG_EXPR_LIST_DECL_SINGLE(A13, RGMII1TXD3, RGMII1); +PIN_DECL_(A13, SIG_EXPR_LIST_PTR(A13, GPIOT5), SIG_EXPR_LIST_PTR(A13, DASHA13), + SIG_EXPR_LIST_PTR(A13, RGMII1TXD3)); #define RMII2_DESC SIG_DESC_BIT(HW_STRAP1, 7, 0) #define D9 158 -SIG_EXPR_LIST_DECL_SINGLE(GPIOT6, GPIOT6, SIG_DESC_SET(SCUA0, 6)); -SIG_EXPR_LIST_DECL_SINGLE(RMII2TXEN, RMII2, RMII2_DESC); -SIG_EXPR_LIST_DECL_SINGLE(RGMII2TXCK, RGMII2); -MS_PIN_DECL_(D9, SIG_EXPR_LIST_PTR(GPIOT6), SIG_EXPR_LIST_PTR(RMII2TXEN), - SIG_EXPR_LIST_PTR(RGMII2TXCK)); +SIG_EXPR_LIST_DECL_SINGLE(D9, GPIOT6, GPIOT6, SIG_DESC_SET(SCUA0, 6)); +SIG_EXPR_LIST_DECL_SINGLE(D9, RMII2TXEN, RMII2, RMII2_DESC); +SIG_EXPR_LIST_DECL_SINGLE(D9, RGMII2TXCK, RGMII2); +PIN_DECL_(D9, SIG_EXPR_LIST_PTR(D9, GPIOT6), SIG_EXPR_LIST_PTR(D9, RMII2TXEN), + SIG_EXPR_LIST_PTR(D9, RGMII2TXCK)); #define E9 159 -SIG_EXPR_LIST_DECL_SINGLE(GPIOT7, GPIOT7, SIG_DESC_SET(SCUA0, 7)); -SIG_EXPR_LIST_DECL_SINGLE(DASHE9, RMII2, RMII2_DESC); -SIG_EXPR_LIST_DECL_SINGLE(RGMII2TXCTL, RGMII2); -MS_PIN_DECL_(E9, SIG_EXPR_LIST_PTR(GPIOT7), SIG_EXPR_LIST_PTR(DASHE9), - SIG_EXPR_LIST_PTR(RGMII2TXCTL)); +SIG_EXPR_LIST_DECL_SINGLE(E9, GPIOT7, GPIOT7, SIG_DESC_SET(SCUA0, 7)); +SIG_EXPR_LIST_DECL_SINGLE(E9, DASHE9, RMII2, RMII2_DESC); +SIG_EXPR_LIST_DECL_SINGLE(E9, RGMII2TXCTL, RGMII2); +PIN_DECL_(E9, SIG_EXPR_LIST_PTR(E9, GPIOT7), SIG_EXPR_LIST_PTR(E9, DASHE9), + SIG_EXPR_LIST_PTR(E9, RGMII2TXCTL)); #define A10 160 -SIG_EXPR_LIST_DECL_SINGLE(GPIOU0, GPIOU0, SIG_DESC_SET(SCUA0, 8)); -SIG_EXPR_LIST_DECL_SINGLE(RMII2TXD0, RMII2, RMII2_DESC); -SIG_EXPR_LIST_DECL_SINGLE(RGMII2TXD0, RGMII2); -MS_PIN_DECL_(A10, SIG_EXPR_LIST_PTR(GPIOU0), SIG_EXPR_LIST_PTR(RMII2TXD0), - SIG_EXPR_LIST_PTR(RGMII2TXD0)); +SIG_EXPR_LIST_DECL_SINGLE(A10, GPIOU0, GPIOU0, SIG_DESC_SET(SCUA0, 8)); +SIG_EXPR_LIST_DECL_SINGLE(A10, RMII2TXD0, RMII2, RMII2_DESC); +SIG_EXPR_LIST_DECL_SINGLE(A10, RGMII2TXD0, RGMII2); +PIN_DECL_(A10, SIG_EXPR_LIST_PTR(A10, GPIOU0), + SIG_EXPR_LIST_PTR(A10, RMII2TXD0), + SIG_EXPR_LIST_PTR(A10, RGMII2TXD0)); #define B10 161 -SIG_EXPR_LIST_DECL_SINGLE(GPIOU1, GPIOU1, SIG_DESC_SET(SCUA0, 9)); -SIG_EXPR_LIST_DECL_SINGLE(RMII2TXD1, RMII2, RMII2_DESC); -SIG_EXPR_LIST_DECL_SINGLE(RGMII2TXD1, RGMII2); -MS_PIN_DECL_(B10, SIG_EXPR_LIST_PTR(GPIOU1), SIG_EXPR_LIST_PTR(RMII2TXD1), - SIG_EXPR_LIST_PTR(RGMII2TXD1)); +SIG_EXPR_LIST_DECL_SINGLE(B10, GPIOU1, GPIOU1, SIG_DESC_SET(SCUA0, 9)); +SIG_EXPR_LIST_DECL_SINGLE(B10, RMII2TXD1, RMII2, RMII2_DESC); +SIG_EXPR_LIST_DECL_SINGLE(B10, RGMII2TXD1, RGMII2); +PIN_DECL_(B10, SIG_EXPR_LIST_PTR(B10, GPIOU1), + SIG_EXPR_LIST_PTR(B10, RMII2TXD1), + SIG_EXPR_LIST_PTR(B10, RGMII2TXD1)); #define C10 162 -SIG_EXPR_LIST_DECL_SINGLE(GPIOU2, GPIOU2, SIG_DESC_SET(SCUA0, 10)); -SIG_EXPR_LIST_DECL_SINGLE(DASHC10, RMII2, RMII2_DESC); -SIG_EXPR_LIST_DECL_SINGLE(RGMII2TXD2, RGMII2); -MS_PIN_DECL_(C10, SIG_EXPR_LIST_PTR(GPIOU2), SIG_EXPR_LIST_PTR(DASHC10), - SIG_EXPR_LIST_PTR(RGMII2TXD2)); +SIG_EXPR_LIST_DECL_SINGLE(C10, GPIOU2, GPIOU2, SIG_DESC_SET(SCUA0, 10)); +SIG_EXPR_LIST_DECL_SINGLE(C10, DASHC10, RMII2, RMII2_DESC); +SIG_EXPR_LIST_DECL_SINGLE(C10, RGMII2TXD2, RGMII2); +PIN_DECL_(C10, SIG_EXPR_LIST_PTR(C10, GPIOU2), SIG_EXPR_LIST_PTR(C10, DASHC10), + SIG_EXPR_LIST_PTR(C10, RGMII2TXD2)); #define D10 163 -SIG_EXPR_LIST_DECL_SINGLE(GPIOU3, GPIOU3, SIG_DESC_SET(SCUA0, 11)); -SIG_EXPR_LIST_DECL_SINGLE(DASHD10, RMII2, RMII2_DESC); -SIG_EXPR_LIST_DECL_SINGLE(RGMII2TXD3, RGMII2); -MS_PIN_DECL_(D10, SIG_EXPR_LIST_PTR(GPIOU3), SIG_EXPR_LIST_PTR(DASHD10), - SIG_EXPR_LIST_PTR(RGMII2TXD3)); +SIG_EXPR_LIST_DECL_SINGLE(D10, GPIOU3, GPIOU3, SIG_DESC_SET(SCUA0, 11)); +SIG_EXPR_LIST_DECL_SINGLE(D10, DASHD10, RMII2, RMII2_DESC); +SIG_EXPR_LIST_DECL_SINGLE(D10, RGMII2TXD3, RGMII2); +PIN_DECL_(D10, SIG_EXPR_LIST_PTR(D10, GPIOU3), SIG_EXPR_LIST_PTR(D10, DASHD10), + SIG_EXPR_LIST_PTR(D10, RGMII2TXD3)); #define E11 164 -SIG_EXPR_LIST_DECL_SINGLE(GPIOU4, GPIOU4, SIG_DESC_SET(SCUA0, 12)); -SIG_EXPR_LIST_DECL_SINGLE(RMII1RCLK, RMII1, RMII1_DESC); -SIG_EXPR_LIST_DECL_SINGLE(RGMII1RXCK, RGMII1); -MS_PIN_DECL_(E11, SIG_EXPR_LIST_PTR(GPIOU4), SIG_EXPR_LIST_PTR(RMII1RCLK), - SIG_EXPR_LIST_PTR(RGMII1RXCK)); +SIG_EXPR_LIST_DECL_SINGLE(E11, GPIOU4, GPIOU4, SIG_DESC_SET(SCUA0, 12)); +SIG_EXPR_LIST_DECL_SINGLE(E11, RMII1RCLK, RMII1, RMII1_DESC); +SIG_EXPR_LIST_DECL_SINGLE(E11, RGMII1RXCK, RGMII1); +PIN_DECL_(E11, SIG_EXPR_LIST_PTR(E11, GPIOU4), + SIG_EXPR_LIST_PTR(E11, RMII1RCLK), + SIG_EXPR_LIST_PTR(E11, RGMII1RXCK)); #define D11 165 -SIG_EXPR_LIST_DECL_SINGLE(GPIOU5, GPIOU5, SIG_DESC_SET(SCUA0, 13)); -SIG_EXPR_LIST_DECL_SINGLE(DASHD11, RMII1, RMII1_DESC); -SIG_EXPR_LIST_DECL_SINGLE(RGMII1RXCTL, RGMII1); -MS_PIN_DECL_(D11, SIG_EXPR_LIST_PTR(GPIOU5), SIG_EXPR_LIST_PTR(DASHD11), - SIG_EXPR_LIST_PTR(RGMII1RXCTL)); +SIG_EXPR_LIST_DECL_SINGLE(D11, GPIOU5, GPIOU5, SIG_DESC_SET(SCUA0, 13)); +SIG_EXPR_LIST_DECL_SINGLE(D11, DASHD11, RMII1, RMII1_DESC); +SIG_EXPR_LIST_DECL_SINGLE(D11, RGMII1RXCTL, RGMII1); +PIN_DECL_(D11, SIG_EXPR_LIST_PTR(D11, GPIOU5), SIG_EXPR_LIST_PTR(D11, DASHD11), + SIG_EXPR_LIST_PTR(D11, RGMII1RXCTL)); #define C11 166 -SIG_EXPR_LIST_DECL_SINGLE(GPIOU6, GPIOU6, SIG_DESC_SET(SCUA0, 14)); -SIG_EXPR_LIST_DECL_SINGLE(RMII1RXD0, RMII1, RMII1_DESC); -SIG_EXPR_LIST_DECL_SINGLE(RGMII1RXD0, RGMII1); -MS_PIN_DECL_(C11, SIG_EXPR_LIST_PTR(GPIOU6), SIG_EXPR_LIST_PTR(RMII1RXD0), - SIG_EXPR_LIST_PTR(RGMII1RXD0)); +SIG_EXPR_LIST_DECL_SINGLE(C11, GPIOU6, GPIOU6, SIG_DESC_SET(SCUA0, 14)); +SIG_EXPR_LIST_DECL_SINGLE(C11, RMII1RXD0, RMII1, RMII1_DESC); +SIG_EXPR_LIST_DECL_SINGLE(C11, RGMII1RXD0, RGMII1); +PIN_DECL_(C11, SIG_EXPR_LIST_PTR(C11, GPIOU6), + SIG_EXPR_LIST_PTR(C11, RMII1RXD0), + SIG_EXPR_LIST_PTR(C11, RGMII1RXD0)); #define B11 167 -SIG_EXPR_LIST_DECL_SINGLE(GPIOU7, GPIOU7, SIG_DESC_SET(SCUA0, 15)); -SIG_EXPR_LIST_DECL_SINGLE(RMII1RXD1, RMII1, RMII1_DESC); -SIG_EXPR_LIST_DECL_SINGLE(RGMII1RXD1, RGMII1); -MS_PIN_DECL_(B11, SIG_EXPR_LIST_PTR(GPIOU7), SIG_EXPR_LIST_PTR(RMII1RXD1), - SIG_EXPR_LIST_PTR(RGMII1RXD1)); +SIG_EXPR_LIST_DECL_SINGLE(B11, GPIOU7, GPIOU7, SIG_DESC_SET(SCUA0, 15)); +SIG_EXPR_LIST_DECL_SINGLE(B11, RMII1RXD1, RMII1, RMII1_DESC); +SIG_EXPR_LIST_DECL_SINGLE(B11, RGMII1RXD1, RGMII1); +PIN_DECL_(B11, SIG_EXPR_LIST_PTR(B11, GPIOU7), + SIG_EXPR_LIST_PTR(B11, RMII1RXD1), + SIG_EXPR_LIST_PTR(B11, RGMII1RXD1)); #define A11 168 -SIG_EXPR_LIST_DECL_SINGLE(GPIOV0, GPIOV0, SIG_DESC_SET(SCUA0, 16)); -SIG_EXPR_LIST_DECL_SINGLE(RMII1CRSDV, RMII1, RMII1_DESC); -SIG_EXPR_LIST_DECL_SINGLE(RGMII1RXD2, RGMII1); -MS_PIN_DECL_(A11, SIG_EXPR_LIST_PTR(GPIOV0), SIG_EXPR_LIST_PTR(RMII1CRSDV), - SIG_EXPR_LIST_PTR(RGMII1RXD2)); +SIG_EXPR_LIST_DECL_SINGLE(A11, GPIOV0, GPIOV0, SIG_DESC_SET(SCUA0, 16)); +SIG_EXPR_LIST_DECL_SINGLE(A11, RMII1CRSDV, RMII1, RMII1_DESC); +SIG_EXPR_LIST_DECL_SINGLE(A11, RGMII1RXD2, RGMII1); +PIN_DECL_(A11, SIG_EXPR_LIST_PTR(A11, GPIOV0), + SIG_EXPR_LIST_PTR(A11, RMII1CRSDV), + SIG_EXPR_LIST_PTR(A11, RGMII1RXD2)); #define E10 169 -SIG_EXPR_LIST_DECL_SINGLE(GPIOV1, GPIOV1, SIG_DESC_SET(SCUA0, 17)); -SIG_EXPR_LIST_DECL_SINGLE(RMII1RXER, RMII1, RMII1_DESC); -SIG_EXPR_LIST_DECL_SINGLE(RGMII1RXD3, RGMII1); -MS_PIN_DECL_(E10, SIG_EXPR_LIST_PTR(GPIOV1), SIG_EXPR_LIST_PTR(RMII1RXER), - SIG_EXPR_LIST_PTR(RGMII1RXD3)); +SIG_EXPR_LIST_DECL_SINGLE(E10, GPIOV1, GPIOV1, SIG_DESC_SET(SCUA0, 17)); +SIG_EXPR_LIST_DECL_SINGLE(E10, RMII1RXER, RMII1, RMII1_DESC); +SIG_EXPR_LIST_DECL_SINGLE(E10, RGMII1RXD3, RGMII1); +PIN_DECL_(E10, SIG_EXPR_LIST_PTR(E10, GPIOV1), + SIG_EXPR_LIST_PTR(E10, RMII1RXER), + SIG_EXPR_LIST_PTR(E10, RGMII1RXD3)); #define C9 170 -SIG_EXPR_LIST_DECL_SINGLE(GPIOV2, GPIOV2, SIG_DESC_SET(SCUA0, 18)); -SIG_EXPR_LIST_DECL_SINGLE(RMII2RCLK, RMII2, RMII2_DESC); -SIG_EXPR_LIST_DECL_SINGLE(RGMII2RXCK, RGMII2); -MS_PIN_DECL_(C9, SIG_EXPR_LIST_PTR(GPIOV2), SIG_EXPR_LIST_PTR(RMII2RCLK), - SIG_EXPR_LIST_PTR(RGMII2RXCK)); +SIG_EXPR_LIST_DECL_SINGLE(C9, GPIOV2, GPIOV2, SIG_DESC_SET(SCUA0, 18)); +SIG_EXPR_LIST_DECL_SINGLE(C9, RMII2RCLK, RMII2, RMII2_DESC); +SIG_EXPR_LIST_DECL_SINGLE(C9, RGMII2RXCK, RGMII2); +PIN_DECL_(C9, SIG_EXPR_LIST_PTR(C9, GPIOV2), SIG_EXPR_LIST_PTR(C9, RMII2RCLK), + SIG_EXPR_LIST_PTR(C9, RGMII2RXCK)); #define B9 171 -SIG_EXPR_LIST_DECL_SINGLE(GPIOV3, GPIOV3, SIG_DESC_SET(SCUA0, 19)); -SIG_EXPR_LIST_DECL_SINGLE(DASHB9, RMII2, RMII2_DESC); -SIG_EXPR_LIST_DECL_SINGLE(RGMII2RXCTL, RGMII2); -MS_PIN_DECL_(B9, SIG_EXPR_LIST_PTR(GPIOV3), SIG_EXPR_LIST_PTR(DASHB9), - SIG_EXPR_LIST_PTR(RGMII2RXCTL)); +SIG_EXPR_LIST_DECL_SINGLE(B9, GPIOV3, GPIOV3, SIG_DESC_SET(SCUA0, 19)); +SIG_EXPR_LIST_DECL_SINGLE(B9, DASHB9, RMII2, RMII2_DESC); +SIG_EXPR_LIST_DECL_SINGLE(B9, RGMII2RXCTL, RGMII2); +PIN_DECL_(B9, SIG_EXPR_LIST_PTR(B9, GPIOV3), SIG_EXPR_LIST_PTR(B9, DASHB9), + SIG_EXPR_LIST_PTR(B9, RGMII2RXCTL)); #define A9 172 -SIG_EXPR_LIST_DECL_SINGLE(GPIOV4, GPIOV4, SIG_DESC_SET(SCUA0, 20)); -SIG_EXPR_LIST_DECL_SINGLE(RMII2RXD0, RMII2, RMII2_DESC); -SIG_EXPR_LIST_DECL_SINGLE(RGMII2RXD0, RGMII2); -MS_PIN_DECL_(A9, SIG_EXPR_LIST_PTR(GPIOV4), SIG_EXPR_LIST_PTR(RMII2RXD0), - SIG_EXPR_LIST_PTR(RGMII2RXD0)); +SIG_EXPR_LIST_DECL_SINGLE(A9, GPIOV4, GPIOV4, SIG_DESC_SET(SCUA0, 20)); +SIG_EXPR_LIST_DECL_SINGLE(A9, RMII2RXD0, RMII2, RMII2_DESC); +SIG_EXPR_LIST_DECL_SINGLE(A9, RGMII2RXD0, RGMII2); +PIN_DECL_(A9, SIG_EXPR_LIST_PTR(A9, GPIOV4), SIG_EXPR_LIST_PTR(A9, RMII2RXD0), + SIG_EXPR_LIST_PTR(A9, RGMII2RXD0)); #define E8 173 -SIG_EXPR_LIST_DECL_SINGLE(GPIOV5, GPIOV5, SIG_DESC_SET(SCUA0, 21)); -SIG_EXPR_LIST_DECL_SINGLE(RMII2RXD1, RMII2, RMII2_DESC); -SIG_EXPR_LIST_DECL_SINGLE(RGMII2RXD1, RGMII2); -MS_PIN_DECL_(E8, SIG_EXPR_LIST_PTR(GPIOV5), SIG_EXPR_LIST_PTR(RMII2RXD1), - SIG_EXPR_LIST_PTR(RGMII2RXD1)); +SIG_EXPR_LIST_DECL_SINGLE(E8, GPIOV5, GPIOV5, SIG_DESC_SET(SCUA0, 21)); +SIG_EXPR_LIST_DECL_SINGLE(E8, RMII2RXD1, RMII2, RMII2_DESC); +SIG_EXPR_LIST_DECL_SINGLE(E8, RGMII2RXD1, RGMII2); +PIN_DECL_(E8, SIG_EXPR_LIST_PTR(E8, GPIOV5), SIG_EXPR_LIST_PTR(E8, RMII2RXD1), + SIG_EXPR_LIST_PTR(E8, RGMII2RXD1)); #define D8 174 -SIG_EXPR_LIST_DECL_SINGLE(GPIOV6, GPIOV6, SIG_DESC_SET(SCUA0, 22)); -SIG_EXPR_LIST_DECL_SINGLE(RMII2CRSDV, RMII2, RMII2_DESC); -SIG_EXPR_LIST_DECL_SINGLE(RGMII2RXD2, RGMII2); -MS_PIN_DECL_(D8, SIG_EXPR_LIST_PTR(GPIOV6), SIG_EXPR_LIST_PTR(RMII2CRSDV), - SIG_EXPR_LIST_PTR(RGMII2RXD2)); +SIG_EXPR_LIST_DECL_SINGLE(D8, GPIOV6, GPIOV6, SIG_DESC_SET(SCUA0, 22)); +SIG_EXPR_LIST_DECL_SINGLE(D8, RMII2CRSDV, RMII2, RMII2_DESC); +SIG_EXPR_LIST_DECL_SINGLE(D8, RGMII2RXD2, RGMII2); +PIN_DECL_(D8, SIG_EXPR_LIST_PTR(D8, GPIOV6), SIG_EXPR_LIST_PTR(D8, RMII2CRSDV), + SIG_EXPR_LIST_PTR(D8, RGMII2RXD2)); #define C8 175 -SIG_EXPR_LIST_DECL_SINGLE(GPIOV7, GPIOV7, SIG_DESC_SET(SCUA0, 23)); -SIG_EXPR_LIST_DECL_SINGLE(RMII2RXER, RMII2, RMII2_DESC); -SIG_EXPR_LIST_DECL_SINGLE(RGMII2RXD3, RGMII2); -MS_PIN_DECL_(C8, SIG_EXPR_LIST_PTR(GPIOV7), SIG_EXPR_LIST_PTR(RMII2RXER), - SIG_EXPR_LIST_PTR(RGMII2RXD3)); +SIG_EXPR_LIST_DECL_SINGLE(C8, GPIOV7, GPIOV7, SIG_DESC_SET(SCUA0, 23)); +SIG_EXPR_LIST_DECL_SINGLE(C8, RMII2RXER, RMII2, RMII2_DESC); +SIG_EXPR_LIST_DECL_SINGLE(C8, RGMII2RXD3, RGMII2); +PIN_DECL_(C8, SIG_EXPR_LIST_PTR(C8, GPIOV7), SIG_EXPR_LIST_PTR(C8, RMII2RXER), + SIG_EXPR_LIST_PTR(C8, RGMII2RXD3)); FUNC_GROUP_DECL(RMII1, A12, B12, C12, D12, E12, A13, E11, D11, C11, B11, A11, E10); @@ -1374,354 +1463,390 @@ FUNC_GROUP_DECL(RMII2, D9, E9, A10, B10, C10, D10, C9, B9, A9, E8, D8, C8); FUNC_GROUP_DECL(RGMII2, D9, E9, A10, B10, C10, D10, C9, B9, A9, E8, D8, C8); #define L5 176 -SIG_EXPR_LIST_DECL_SINGLE(GPIOW0, GPIOW0, SIG_DESC_SET(SCUA0, 24)); -SIG_EXPR_LIST_DECL_SINGLE(ADC0, ADC0); -MS_PIN_DECL_(L5, SIG_EXPR_LIST_PTR(GPIOW0), SIG_EXPR_LIST_PTR(ADC0)); +SIG_EXPR_LIST_DECL_SINGLE(L5, GPIOW0, GPIOW0, SIG_DESC_SET(SCUA0, 24)); +SIG_EXPR_LIST_DECL_SINGLE(L5, ADC0, ADC0); +PIN_DECL_(L5, SIG_EXPR_LIST_PTR(L5, GPIOW0), SIG_EXPR_LIST_PTR(L5, ADC0)); FUNC_GROUP_DECL(ADC0, L5); #define L4 177 -SIG_EXPR_LIST_DECL_SINGLE(GPIOW1, GPIOW1, SIG_DESC_SET(SCUA0, 25)); -SIG_EXPR_LIST_DECL_SINGLE(ADC1, ADC1); -MS_PIN_DECL_(L4, SIG_EXPR_LIST_PTR(GPIOW1), SIG_EXPR_LIST_PTR(ADC1)); +SIG_EXPR_LIST_DECL_SINGLE(L4, GPIOW1, GPIOW1, SIG_DESC_SET(SCUA0, 25)); +SIG_EXPR_LIST_DECL_SINGLE(L4, ADC1, ADC1); +PIN_DECL_(L4, SIG_EXPR_LIST_PTR(L4, GPIOW1), SIG_EXPR_LIST_PTR(L4, ADC1)); FUNC_GROUP_DECL(ADC1, L4); #define L3 178 -SIG_EXPR_LIST_DECL_SINGLE(GPIOW2, GPIOW2, SIG_DESC_SET(SCUA0, 26)); -SIG_EXPR_LIST_DECL_SINGLE(ADC2, ADC2); -MS_PIN_DECL_(L3, SIG_EXPR_LIST_PTR(GPIOW2), SIG_EXPR_LIST_PTR(ADC2)); +SIG_EXPR_LIST_DECL_SINGLE(L3, GPIOW2, GPIOW2, SIG_DESC_SET(SCUA0, 26)); +SIG_EXPR_LIST_DECL_SINGLE(L3, ADC2, ADC2); +PIN_DECL_(L3, SIG_EXPR_LIST_PTR(L3, GPIOW2), SIG_EXPR_LIST_PTR(L3, ADC2)); FUNC_GROUP_DECL(ADC2, L3); #define L2 179 -SIG_EXPR_LIST_DECL_SINGLE(GPIOW3, GPIOW3, SIG_DESC_SET(SCUA0, 27)); -SIG_EXPR_LIST_DECL_SINGLE(ADC3, ADC3); -MS_PIN_DECL_(L2, SIG_EXPR_LIST_PTR(GPIOW3), SIG_EXPR_LIST_PTR(ADC3)); +SIG_EXPR_LIST_DECL_SINGLE(L2, GPIOW3, GPIOW3, SIG_DESC_SET(SCUA0, 27)); +SIG_EXPR_LIST_DECL_SINGLE(L2, ADC3, ADC3); +PIN_DECL_(L2, SIG_EXPR_LIST_PTR(L2, GPIOW3), SIG_EXPR_LIST_PTR(L2, ADC3)); FUNC_GROUP_DECL(ADC3, L2); #define L1 180 -SIG_EXPR_LIST_DECL_SINGLE(GPIOW4, GPIOW4, SIG_DESC_SET(SCUA0, 28)); -SIG_EXPR_LIST_DECL_SINGLE(ADC4, ADC4); -MS_PIN_DECL_(L1, SIG_EXPR_LIST_PTR(GPIOW4), SIG_EXPR_LIST_PTR(ADC4)); +SIG_EXPR_LIST_DECL_SINGLE(L1, GPIOW4, GPIOW4, SIG_DESC_SET(SCUA0, 28)); +SIG_EXPR_LIST_DECL_SINGLE(L1, ADC4, ADC4); +PIN_DECL_(L1, SIG_EXPR_LIST_PTR(L1, GPIOW4), SIG_EXPR_LIST_PTR(L1, ADC4)); FUNC_GROUP_DECL(ADC4, L1); #define M5 181 -SIG_EXPR_LIST_DECL_SINGLE(GPIOW5, GPIOW5, SIG_DESC_SET(SCUA0, 29)); -SIG_EXPR_LIST_DECL_SINGLE(ADC5, ADC5); -MS_PIN_DECL_(M5, SIG_EXPR_LIST_PTR(GPIOW5), SIG_EXPR_LIST_PTR(ADC5)); +SIG_EXPR_LIST_DECL_SINGLE(M5, GPIOW5, GPIOW5, SIG_DESC_SET(SCUA0, 29)); +SIG_EXPR_LIST_DECL_SINGLE(M5, ADC5, ADC5); +PIN_DECL_(M5, SIG_EXPR_LIST_PTR(M5, GPIOW5), SIG_EXPR_LIST_PTR(M5, ADC5)); FUNC_GROUP_DECL(ADC5, M5); #define M4 182 -SIG_EXPR_LIST_DECL_SINGLE(GPIOW6, GPIOW6, SIG_DESC_SET(SCUA0, 30)); -SIG_EXPR_LIST_DECL_SINGLE(ADC6, ADC6); -MS_PIN_DECL_(M4, SIG_EXPR_LIST_PTR(GPIOW6), SIG_EXPR_LIST_PTR(ADC6)); +SIG_EXPR_LIST_DECL_SINGLE(M4, GPIOW6, GPIOW6, SIG_DESC_SET(SCUA0, 30)); +SIG_EXPR_LIST_DECL_SINGLE(M4, ADC6, ADC6); +PIN_DECL_(M4, SIG_EXPR_LIST_PTR(M4, GPIOW6), SIG_EXPR_LIST_PTR(M4, ADC6)); FUNC_GROUP_DECL(ADC6, M4); #define M3 183 -SIG_EXPR_LIST_DECL_SINGLE(GPIOW7, GPIOW7, SIG_DESC_SET(SCUA0, 31)); -SIG_EXPR_LIST_DECL_SINGLE(ADC7, ADC7); -MS_PIN_DECL_(M3, SIG_EXPR_LIST_PTR(GPIOW7), SIG_EXPR_LIST_PTR(ADC7)); +SIG_EXPR_LIST_DECL_SINGLE(M3, GPIOW7, GPIOW7, SIG_DESC_SET(SCUA0, 31)); +SIG_EXPR_LIST_DECL_SINGLE(M3, ADC7, ADC7); +PIN_DECL_(M3, SIG_EXPR_LIST_PTR(M3, GPIOW7), SIG_EXPR_LIST_PTR(M3, ADC7)); FUNC_GROUP_DECL(ADC7, M3); #define M2 184 -SIG_EXPR_LIST_DECL_SINGLE(GPIOX0, GPIOX0, SIG_DESC_SET(SCUA4, 0)); -SIG_EXPR_LIST_DECL_SINGLE(ADC8, ADC8); -MS_PIN_DECL_(M2, SIG_EXPR_LIST_PTR(GPIOX0), SIG_EXPR_LIST_PTR(ADC8)); +SIG_EXPR_LIST_DECL_SINGLE(M2, GPIOX0, GPIOX0, SIG_DESC_SET(SCUA4, 0)); +SIG_EXPR_LIST_DECL_SINGLE(M2, ADC8, ADC8); +PIN_DECL_(M2, SIG_EXPR_LIST_PTR(M2, GPIOX0), SIG_EXPR_LIST_PTR(M2, ADC8)); FUNC_GROUP_DECL(ADC8, M2); #define M1 185 -SIG_EXPR_LIST_DECL_SINGLE(GPIOX1, GPIOX1, SIG_DESC_SET(SCUA4, 1)); -SIG_EXPR_LIST_DECL_SINGLE(ADC9, ADC9); -MS_PIN_DECL_(M1, SIG_EXPR_LIST_PTR(GPIOX1), SIG_EXPR_LIST_PTR(ADC9)); +SIG_EXPR_LIST_DECL_SINGLE(M1, GPIOX1, GPIOX1, SIG_DESC_SET(SCUA4, 1)); +SIG_EXPR_LIST_DECL_SINGLE(M1, ADC9, ADC9); +PIN_DECL_(M1, SIG_EXPR_LIST_PTR(M1, GPIOX1), SIG_EXPR_LIST_PTR(M1, ADC9)); FUNC_GROUP_DECL(ADC9, M1); #define N5 186 -SIG_EXPR_LIST_DECL_SINGLE(GPIOX2, GPIOX2, SIG_DESC_SET(SCUA4, 2)); -SIG_EXPR_LIST_DECL_SINGLE(ADC10, ADC10); -MS_PIN_DECL_(N5, SIG_EXPR_LIST_PTR(GPIOX2), SIG_EXPR_LIST_PTR(ADC10)); +SIG_EXPR_LIST_DECL_SINGLE(N5, GPIOX2, GPIOX2, SIG_DESC_SET(SCUA4, 2)); +SIG_EXPR_LIST_DECL_SINGLE(N5, ADC10, ADC10); +PIN_DECL_(N5, SIG_EXPR_LIST_PTR(N5, GPIOX2), SIG_EXPR_LIST_PTR(N5, ADC10)); FUNC_GROUP_DECL(ADC10, N5); #define N4 187 -SIG_EXPR_LIST_DECL_SINGLE(GPIOX3, GPIOX3, SIG_DESC_SET(SCUA4, 3)); -SIG_EXPR_LIST_DECL_SINGLE(ADC11, ADC11); -MS_PIN_DECL_(N4, SIG_EXPR_LIST_PTR(GPIOX3), SIG_EXPR_LIST_PTR(ADC11)); +SIG_EXPR_LIST_DECL_SINGLE(N4, GPIOX3, GPIOX3, SIG_DESC_SET(SCUA4, 3)); +SIG_EXPR_LIST_DECL_SINGLE(N4, ADC11, ADC11); +PIN_DECL_(N4, SIG_EXPR_LIST_PTR(N4, GPIOX3), SIG_EXPR_LIST_PTR(N4, ADC11)); FUNC_GROUP_DECL(ADC11, N4); #define N3 188 -SIG_EXPR_LIST_DECL_SINGLE(GPIOX4, GPIOX4, SIG_DESC_SET(SCUA4, 4)); -SIG_EXPR_LIST_DECL_SINGLE(ADC12, ADC12); -MS_PIN_DECL_(N3, SIG_EXPR_LIST_PTR(GPIOX4), SIG_EXPR_LIST_PTR(ADC12)); +SIG_EXPR_LIST_DECL_SINGLE(N3, GPIOX4, GPIOX4, SIG_DESC_SET(SCUA4, 4)); +SIG_EXPR_LIST_DECL_SINGLE(N3, ADC12, ADC12); +PIN_DECL_(N3, SIG_EXPR_LIST_PTR(N3, GPIOX4), SIG_EXPR_LIST_PTR(N3, ADC12)); FUNC_GROUP_DECL(ADC12, N3); #define N2 189 -SIG_EXPR_LIST_DECL_SINGLE(GPIOX5, GPIOX5, SIG_DESC_SET(SCUA4, 5)); -SIG_EXPR_LIST_DECL_SINGLE(ADC13, ADC13); -MS_PIN_DECL_(N2, SIG_EXPR_LIST_PTR(GPIOX5), SIG_EXPR_LIST_PTR(ADC13)); +SIG_EXPR_LIST_DECL_SINGLE(N2, GPIOX5, GPIOX5, SIG_DESC_SET(SCUA4, 5)); +SIG_EXPR_LIST_DECL_SINGLE(N2, ADC13, ADC13); +PIN_DECL_(N2, SIG_EXPR_LIST_PTR(N2, GPIOX5), SIG_EXPR_LIST_PTR(N2, ADC13)); FUNC_GROUP_DECL(ADC13, N2); #define N1 190 -SIG_EXPR_LIST_DECL_SINGLE(GPIOX6, GPIOX6, SIG_DESC_SET(SCUA4, 6)); -SIG_EXPR_LIST_DECL_SINGLE(ADC14, ADC14); -MS_PIN_DECL_(N1, SIG_EXPR_LIST_PTR(GPIOX6), SIG_EXPR_LIST_PTR(ADC14)); +SIG_EXPR_LIST_DECL_SINGLE(N1, GPIOX6, GPIOX6, SIG_DESC_SET(SCUA4, 6)); +SIG_EXPR_LIST_DECL_SINGLE(N1, ADC14, ADC14); +PIN_DECL_(N1, SIG_EXPR_LIST_PTR(N1, GPIOX6), SIG_EXPR_LIST_PTR(N1, ADC14)); FUNC_GROUP_DECL(ADC14, N1); #define P5 191 -SIG_EXPR_LIST_DECL_SINGLE(GPIOX7, GPIOX7, SIG_DESC_SET(SCUA4, 7)); -SIG_EXPR_LIST_DECL_SINGLE(ADC15, ADC15); -MS_PIN_DECL_(P5, SIG_EXPR_LIST_PTR(GPIOX7), SIG_EXPR_LIST_PTR(ADC15)); +SIG_EXPR_LIST_DECL_SINGLE(P5, GPIOX7, GPIOX7, SIG_DESC_SET(SCUA4, 7)); +SIG_EXPR_LIST_DECL_SINGLE(P5, ADC15, ADC15); +PIN_DECL_(P5, SIG_EXPR_LIST_PTR(P5, GPIOX7), SIG_EXPR_LIST_PTR(P5, ADC15)); FUNC_GROUP_DECL(ADC15, P5); #define C21 192 -SIG_EXPR_DECL(SIOS3, SIOS3, SIG_DESC_SET(SCUA4, 8)); -SIG_EXPR_DECL(SIOS3, ACPI, ACPI_DESC); -SIG_EXPR_LIST_DECL_DUAL(SIOS3, SIOS3, ACPI); -SS_PIN_DECL(C21, GPIOY0, SIOS3); +SIG_EXPR_DECL_SINGLE(SIOS3, SIOS3, SIG_DESC_SET(SCUA4, 8)); +SIG_EXPR_DECL_SINGLE(SIOS3, ACPI, ACPI_DESC); +SIG_EXPR_LIST_DECL_DUAL(C21, SIOS3, SIOS3, ACPI); +PIN_DECL_1(C21, GPIOY0, SIOS3); FUNC_GROUP_DECL(SIOS3, C21); #define F20 193 -SIG_EXPR_DECL(SIOS5, SIOS5, SIG_DESC_SET(SCUA4, 9)); -SIG_EXPR_DECL(SIOS5, ACPI, ACPI_DESC); -SIG_EXPR_LIST_DECL_DUAL(SIOS5, SIOS5, ACPI); -SS_PIN_DECL(F20, GPIOY1, SIOS5); +SIG_EXPR_DECL_SINGLE(SIOS5, SIOS5, SIG_DESC_SET(SCUA4, 9)); +SIG_EXPR_DECL_SINGLE(SIOS5, ACPI, ACPI_DESC); +SIG_EXPR_LIST_DECL_DUAL(F20, SIOS5, SIOS5, ACPI); +PIN_DECL_1(F20, GPIOY1, SIOS5); FUNC_GROUP_DECL(SIOS5, F20); #define G20 194 -SIG_EXPR_DECL(SIOPWREQ, SIOPWREQ, SIG_DESC_SET(SCUA4, 10)); -SIG_EXPR_DECL(SIOPWREQ, ACPI, ACPI_DESC); -SIG_EXPR_LIST_DECL_DUAL(SIOPWREQ, SIOPWREQ, ACPI); -SS_PIN_DECL(G20, GPIOY2, SIOPWREQ); +SIG_EXPR_DECL_SINGLE(SIOPWREQ, SIOPWREQ, SIG_DESC_SET(SCUA4, 10)); +SIG_EXPR_DECL_SINGLE(SIOPWREQ, ACPI, ACPI_DESC); +SIG_EXPR_LIST_DECL_DUAL(G20, SIOPWREQ, SIOPWREQ, ACPI); +PIN_DECL_1(G20, GPIOY2, SIOPWREQ); FUNC_GROUP_DECL(SIOPWREQ, G20); #define K20 195 -SIG_EXPR_DECL(SIOONCTRL, SIOONCTRL, SIG_DESC_SET(SCUA4, 11)); -SIG_EXPR_DECL(SIOONCTRL, ACPI, ACPI_DESC); -SIG_EXPR_LIST_DECL_DUAL(SIOONCTRL, SIOONCTRL, ACPI); -SS_PIN_DECL(K20, GPIOY3, SIOONCTRL); +SIG_EXPR_DECL_SINGLE(SIOONCTRL, SIOONCTRL, SIG_DESC_SET(SCUA4, 11)); +SIG_EXPR_DECL_SINGLE(SIOONCTRL, ACPI, ACPI_DESC); +SIG_EXPR_LIST_DECL_DUAL(K20, SIOONCTRL, SIOONCTRL, ACPI); +PIN_DECL_1(K20, GPIOY3, SIOONCTRL); FUNC_GROUP_DECL(SIOONCTRL, K20); FUNC_GROUP_DECL(ACPI, B19, A20, D17, A19, C21, F20, G20, K20); #define R22 200 #define R22_DESC SIG_DESC_SET(SCUA4, 16) -SIG_EXPR_DECL(ROMA2, ROM8, R22_DESC, VPOOFF0_DESC); -SIG_EXPR_DECL(ROMA2, ROM16, R22_DESC, VPOOFF0_DESC); -SIG_EXPR_LIST_DECL_DUAL(ROMA2, ROM8, ROM16); -SIG_EXPR_DECL(VPOB0, VPO12, R22_DESC, VPO12_DESC); -SIG_EXPR_DECL(VPOB0, VPO24, R22_DESC, VPO24_DESC); -SIG_EXPR_DECL(VPOB0, VPOOFF1, R22_DESC, VPOOFF1_DESC); -SIG_EXPR_LIST_DECL(VPOB0, SIG_EXPR_PTR(VPOB0, VPO12), - SIG_EXPR_PTR(VPOB0, VPO24), SIG_EXPR_PTR(VPOB0, VPOOFF1)); -MS_PIN_DECL(R22, GPIOZ0, ROMA2, VPOB0); +SIG_EXPR_DECL_SINGLE(ROMA2, ROM8, R22_DESC, VPOOFF0_DESC); +SIG_EXPR_DECL_SINGLE(ROMA2, ROM16, R22_DESC, VPOOFF0_DESC); +SIG_EXPR_LIST_DECL_DUAL(R22, ROMA2, ROM8, ROM16); +SIG_EXPR_DECL_SINGLE(VPOB0, VPO12, R22_DESC, VPO12_DESC); +SIG_EXPR_DECL_SINGLE(VPOB0, VPO24, R22_DESC, VPO24_DESC); +SIG_EXPR_DECL_SINGLE(VPOB0, VPOOFF1, R22_DESC, VPOOFF1_DESC); +SIG_EXPR_LIST_DECL(VPOB0, VPO, + SIG_EXPR_PTR(VPOB0, VPO12), + SIG_EXPR_PTR(VPOB0, VPO24), + SIG_EXPR_PTR(VPOB0, VPOOFF1)); +SIG_EXPR_LIST_ALIAS(R22, VPOB0, VPO); +PIN_DECL_2(R22, GPIOZ0, ROMA2, VPOB0); #define P18 201 #define P18_DESC SIG_DESC_SET(SCUA4, 17) -SIG_EXPR_DECL(ROMA3, ROM8, P18_DESC, VPOOFF0_DESC); -SIG_EXPR_DECL(ROMA3, ROM16, P18_DESC, VPOOFF0_DESC); -SIG_EXPR_LIST_DECL_DUAL(ROMA3, ROM8, ROM16); -SIG_EXPR_DECL(VPOB1, VPO12, P18_DESC, VPO12_DESC); -SIG_EXPR_DECL(VPOB1, VPO24, P18_DESC, VPO24_DESC); -SIG_EXPR_DECL(VPOB1, VPOOFF1, P18_DESC, VPOOFF1_DESC); -SIG_EXPR_LIST_DECL(VPOB1, SIG_EXPR_PTR(VPOB1, VPO12), - SIG_EXPR_PTR(VPOB1, VPO24), SIG_EXPR_PTR(VPOB1, VPOOFF1)); -MS_PIN_DECL(P18, GPIOZ1, ROMA3, VPOB1); +SIG_EXPR_DECL_SINGLE(ROMA3, ROM8, P18_DESC, VPOOFF0_DESC); +SIG_EXPR_DECL_SINGLE(ROMA3, ROM16, P18_DESC, VPOOFF0_DESC); +SIG_EXPR_LIST_DECL_DUAL(P18, ROMA3, ROM8, ROM16); +SIG_EXPR_DECL_SINGLE(VPOB1, VPO12, P18_DESC, VPO12_DESC); +SIG_EXPR_DECL_SINGLE(VPOB1, VPO24, P18_DESC, VPO24_DESC); +SIG_EXPR_DECL_SINGLE(VPOB1, VPOOFF1, P18_DESC, VPOOFF1_DESC); +SIG_EXPR_LIST_DECL(VPOB1, VPO, + SIG_EXPR_PTR(VPOB1, VPO12), + SIG_EXPR_PTR(VPOB1, VPO24), + SIG_EXPR_PTR(VPOB1, VPOOFF1)); +SIG_EXPR_LIST_ALIAS(P18, VPOB1, VPO); +PIN_DECL_2(P18, GPIOZ1, ROMA3, VPOB1); #define P19 202 #define P19_DESC SIG_DESC_SET(SCUA4, 18) -SIG_EXPR_DECL(ROMA4, ROM8, P19_DESC, VPOOFF0_DESC); -SIG_EXPR_DECL(ROMA4, ROM16, P19_DESC, VPOOFF0_DESC); -SIG_EXPR_LIST_DECL_DUAL(ROMA4, ROM8, ROM16); -SIG_EXPR_DECL(VPOB2, VPO12, P19_DESC, VPO12_DESC); -SIG_EXPR_DECL(VPOB2, VPO24, P19_DESC, VPO24_DESC); -SIG_EXPR_DECL(VPOB2, VPOOFF1, P19_DESC, VPOOFF1_DESC); -SIG_EXPR_LIST_DECL(VPOB2, SIG_EXPR_PTR(VPOB2, VPO12), - SIG_EXPR_PTR(VPOB2, VPO24), SIG_EXPR_PTR(VPOB2, VPOOFF1)); -MS_PIN_DECL(P19, GPIOZ2, ROMA4, VPOB2); +SIG_EXPR_DECL_SINGLE(ROMA4, ROM8, P19_DESC, VPOOFF0_DESC); +SIG_EXPR_DECL_SINGLE(ROMA4, ROM16, P19_DESC, VPOOFF0_DESC); +SIG_EXPR_LIST_DECL_DUAL(P19, ROMA4, ROM8, ROM16); +SIG_EXPR_DECL_SINGLE(VPOB2, VPO12, P19_DESC, VPO12_DESC); +SIG_EXPR_DECL_SINGLE(VPOB2, VPO24, P19_DESC, VPO24_DESC); +SIG_EXPR_DECL_SINGLE(VPOB2, VPOOFF1, P19_DESC, VPOOFF1_DESC); +SIG_EXPR_LIST_DECL(VPOB2, VPO, + SIG_EXPR_PTR(VPOB2, VPO12), + SIG_EXPR_PTR(VPOB2, VPO24), + SIG_EXPR_PTR(VPOB2, VPOOFF1)); +SIG_EXPR_LIST_ALIAS(P19, VPOB2, VPO); +PIN_DECL_2(P19, GPIOZ2, ROMA4, VPOB2); #define P20 203 #define P20_DESC SIG_DESC_SET(SCUA4, 19) -SIG_EXPR_DECL(ROMA5, ROM8, P20_DESC, VPOOFF0_DESC); -SIG_EXPR_DECL(ROMA5, ROM16, P20_DESC, VPOOFF0_DESC); -SIG_EXPR_LIST_DECL_DUAL(ROMA5, ROM8, ROM16); -SIG_EXPR_DECL(VPOB3, VPO12, P20_DESC, VPO12_DESC); -SIG_EXPR_DECL(VPOB3, VPO24, P20_DESC, VPO24_DESC); -SIG_EXPR_DECL(VPOB3, VPOOFF1, P20_DESC, VPOOFF1_DESC); -SIG_EXPR_LIST_DECL(VPOB3, SIG_EXPR_PTR(VPOB3, VPO12), - SIG_EXPR_PTR(VPOB3, VPO24), SIG_EXPR_PTR(VPOB3, VPOOFF1)); -MS_PIN_DECL(P20, GPIOZ3, ROMA5, VPOB3); +SIG_EXPR_DECL_SINGLE(ROMA5, ROM8, P20_DESC, VPOOFF0_DESC); +SIG_EXPR_DECL_SINGLE(ROMA5, ROM16, P20_DESC, VPOOFF0_DESC); +SIG_EXPR_LIST_DECL_DUAL(P20, ROMA5, ROM8, ROM16); +SIG_EXPR_DECL_SINGLE(VPOB3, VPO12, P20_DESC, VPO12_DESC); +SIG_EXPR_DECL_SINGLE(VPOB3, VPO24, P20_DESC, VPO24_DESC); +SIG_EXPR_DECL_SINGLE(VPOB3, VPOOFF1, P20_DESC, VPOOFF1_DESC); +SIG_EXPR_LIST_DECL(VPOB3, VPO, + SIG_EXPR_PTR(VPOB3, VPO12), + SIG_EXPR_PTR(VPOB3, VPO24), + SIG_EXPR_PTR(VPOB3, VPOOFF1)); +SIG_EXPR_LIST_ALIAS(P20, VPOB3, VPO); +PIN_DECL_2(P20, GPIOZ3, ROMA5, VPOB3); #define P21 204 #define P21_DESC SIG_DESC_SET(SCUA4, 20) -SIG_EXPR_DECL(ROMA6, ROM8, P21_DESC, VPOOFF0_DESC); -SIG_EXPR_DECL(ROMA6, ROM16, P21_DESC, VPOOFF0_DESC); -SIG_EXPR_LIST_DECL_DUAL(ROMA6, ROM8, ROM16); -SIG_EXPR_DECL(VPOB4, VPO12, P21_DESC, VPO12_DESC); -SIG_EXPR_DECL(VPOB4, VPO24, P21_DESC, VPO24_DESC); -SIG_EXPR_DECL(VPOB4, VPOOFF1, P21_DESC, VPOOFF1_DESC); -SIG_EXPR_LIST_DECL(VPOB4, SIG_EXPR_PTR(VPOB4, VPO12), - SIG_EXPR_PTR(VPOB4, VPO24), SIG_EXPR_PTR(VPOB4, VPOOFF1)); -MS_PIN_DECL(P21, GPIOZ4, ROMA6, VPOB4); +SIG_EXPR_DECL_SINGLE(ROMA6, ROM8, P21_DESC, VPOOFF0_DESC); +SIG_EXPR_DECL_SINGLE(ROMA6, ROM16, P21_DESC, VPOOFF0_DESC); +SIG_EXPR_LIST_DECL_DUAL(P21, ROMA6, ROM8, ROM16); +SIG_EXPR_DECL_SINGLE(VPOB4, VPO12, P21_DESC, VPO12_DESC); +SIG_EXPR_DECL_SINGLE(VPOB4, VPO24, P21_DESC, VPO24_DESC); +SIG_EXPR_DECL_SINGLE(VPOB4, VPOOFF1, P21_DESC, VPOOFF1_DESC); +SIG_EXPR_LIST_DECL(VPOB4, VPO, + SIG_EXPR_PTR(VPOB4, VPO12), + SIG_EXPR_PTR(VPOB4, VPO24), + SIG_EXPR_PTR(VPOB4, VPOOFF1)); +SIG_EXPR_LIST_ALIAS(P21, VPOB4, VPO); +PIN_DECL_2(P21, GPIOZ4, ROMA6, VPOB4); #define P22 205 #define P22_DESC SIG_DESC_SET(SCUA4, 21) -SIG_EXPR_DECL(ROMA7, ROM8, P22_DESC, VPOOFF0_DESC); -SIG_EXPR_DECL(ROMA7, ROM16, P22_DESC, VPOOFF0_DESC); -SIG_EXPR_LIST_DECL_DUAL(ROMA7, ROM8, ROM16); -SIG_EXPR_DECL(VPOB5, VPO12, P22_DESC, VPO12_DESC); -SIG_EXPR_DECL(VPOB5, VPO24, P22_DESC, VPO24_DESC); -SIG_EXPR_DECL(VPOB5, VPOOFF1, P22_DESC, VPOOFF1_DESC); -SIG_EXPR_LIST_DECL(VPOB5, SIG_EXPR_PTR(VPOB5, VPO12), - SIG_EXPR_PTR(VPOB5, VPO24), SIG_EXPR_PTR(VPOB5, VPOOFF1)); -MS_PIN_DECL(P22, GPIOZ5, ROMA7, VPOB5); +SIG_EXPR_DECL_SINGLE(ROMA7, ROM8, P22_DESC, VPOOFF0_DESC); +SIG_EXPR_DECL_SINGLE(ROMA7, ROM16, P22_DESC, VPOOFF0_DESC); +SIG_EXPR_LIST_DECL_DUAL(P22, ROMA7, ROM8, ROM16); +SIG_EXPR_DECL_SINGLE(VPOB5, VPO12, P22_DESC, VPO12_DESC); +SIG_EXPR_DECL_SINGLE(VPOB5, VPO24, P22_DESC, VPO24_DESC); +SIG_EXPR_DECL_SINGLE(VPOB5, VPOOFF1, P22_DESC, VPOOFF1_DESC); +SIG_EXPR_LIST_DECL(VPOB5, VPO, + SIG_EXPR_PTR(VPOB5, VPO12), + SIG_EXPR_PTR(VPOB5, VPO24), + SIG_EXPR_PTR(VPOB5, VPOOFF1)); +SIG_EXPR_LIST_ALIAS(P22, VPOB5, VPO); +PIN_DECL_2(P22, GPIOZ5, ROMA7, VPOB5); #define M19 206 #define M19_DESC SIG_DESC_SET(SCUA4, 22) -SIG_EXPR_DECL(ROMA8, ROM8, M19_DESC, VPOOFF0_DESC); -SIG_EXPR_DECL(ROMA8, ROM16, M19_DESC, VPOOFF0_DESC); -SIG_EXPR_LIST_DECL_DUAL(ROMA8, ROM8, ROM16); -SIG_EXPR_DECL(VPOB6, VPO12, M19_DESC, VPO12_DESC); -SIG_EXPR_DECL(VPOB6, VPO24, M19_DESC, VPO24_DESC); -SIG_EXPR_DECL(VPOB6, VPOOFF1, M19_DESC, VPOOFF1_DESC); -SIG_EXPR_LIST_DECL(VPOB6, SIG_EXPR_PTR(VPOB6, VPO12), - SIG_EXPR_PTR(VPOB6, VPO24), SIG_EXPR_PTR(VPOB6, VPOOFF1)); -MS_PIN_DECL(M19, GPIOZ6, ROMA8, VPOB6); +SIG_EXPR_DECL_SINGLE(ROMA8, ROM8, M19_DESC, VPOOFF0_DESC); +SIG_EXPR_DECL_SINGLE(ROMA8, ROM16, M19_DESC, VPOOFF0_DESC); +SIG_EXPR_LIST_DECL_DUAL(M19, ROMA8, ROM8, ROM16); +SIG_EXPR_DECL_SINGLE(VPOB6, VPO12, M19_DESC, VPO12_DESC); +SIG_EXPR_DECL_SINGLE(VPOB6, VPO24, M19_DESC, VPO24_DESC); +SIG_EXPR_DECL_SINGLE(VPOB6, VPOOFF1, M19_DESC, VPOOFF1_DESC); +SIG_EXPR_LIST_DECL(VPOB6, VPO, + SIG_EXPR_PTR(VPOB6, VPO12), + SIG_EXPR_PTR(VPOB6, VPO24), + SIG_EXPR_PTR(VPOB6, VPOOFF1)); +SIG_EXPR_LIST_ALIAS(M19, VPOB6, VPO); +PIN_DECL_2(M19, GPIOZ6, ROMA8, VPOB6); #define M20 207 #define M20_DESC SIG_DESC_SET(SCUA4, 23) -SIG_EXPR_DECL(ROMA9, ROM8, M20_DESC, VPOOFF0_DESC); -SIG_EXPR_DECL(ROMA9, ROM16, M20_DESC, VPOOFF0_DESC); -SIG_EXPR_LIST_DECL_DUAL(ROMA9, ROM8, ROM16); -SIG_EXPR_DECL(VPOB7, VPO12, M20_DESC, VPO12_DESC); -SIG_EXPR_DECL(VPOB7, VPO24, M20_DESC, VPO24_DESC); -SIG_EXPR_DECL(VPOB7, VPOOFF1, M20_DESC, VPOOFF1_DESC); -SIG_EXPR_LIST_DECL(VPOB7, SIG_EXPR_PTR(VPOB7, VPO12), - SIG_EXPR_PTR(VPOB7, VPO24), SIG_EXPR_PTR(VPOB7, VPOOFF1)); -MS_PIN_DECL(M20, GPIOZ7, ROMA9, VPOB7); +SIG_EXPR_DECL_SINGLE(ROMA9, ROM8, M20_DESC, VPOOFF0_DESC); +SIG_EXPR_DECL_SINGLE(ROMA9, ROM16, M20_DESC, VPOOFF0_DESC); +SIG_EXPR_LIST_DECL_DUAL(M20, ROMA9, ROM8, ROM16); +SIG_EXPR_DECL_SINGLE(VPOB7, VPO12, M20_DESC, VPO12_DESC); +SIG_EXPR_DECL_SINGLE(VPOB7, VPO24, M20_DESC, VPO24_DESC); +SIG_EXPR_DECL_SINGLE(VPOB7, VPOOFF1, M20_DESC, VPOOFF1_DESC); +SIG_EXPR_LIST_DECL(VPOB7, VPO, + SIG_EXPR_PTR(VPOB7, VPO12), + SIG_EXPR_PTR(VPOB7, VPO24), + SIG_EXPR_PTR(VPOB7, VPOOFF1)); +SIG_EXPR_LIST_ALIAS(M20, VPOB7, VPO); +PIN_DECL_2(M20, GPIOZ7, ROMA9, VPOB7); #define M21 208 #define M21_DESC SIG_DESC_SET(SCUA4, 24) -SIG_EXPR_DECL(ROMA10, ROM8, M21_DESC, VPOOFF0_DESC); -SIG_EXPR_DECL(ROMA10, ROM16, M21_DESC, VPOOFF0_DESC); -SIG_EXPR_LIST_DECL_DUAL(ROMA10, ROM8, ROM16); -SIG_EXPR_DECL(VPOG0, VPO12, M21_DESC, VPO12_DESC); -SIG_EXPR_DECL(VPOG0, VPO24, M21_DESC, VPO24_DESC); -SIG_EXPR_DECL(VPOG0, VPOOFF1, M21_DESC, VPOOFF1_DESC); -SIG_EXPR_LIST_DECL(VPOG0, SIG_EXPR_PTR(VPOG0, VPO12), - SIG_EXPR_PTR(VPOG0, VPO24), SIG_EXPR_PTR(VPOG0, VPOOFF1)); -MS_PIN_DECL(M21, GPIOAA0, ROMA10, VPOG0); +SIG_EXPR_DECL_SINGLE(ROMA10, ROM8, M21_DESC, VPOOFF0_DESC); +SIG_EXPR_DECL_SINGLE(ROMA10, ROM16, M21_DESC, VPOOFF0_DESC); +SIG_EXPR_LIST_DECL_DUAL(M21, ROMA10, ROM8, ROM16); +SIG_EXPR_DECL_SINGLE(VPOG0, VPO12, M21_DESC, VPO12_DESC); +SIG_EXPR_DECL_SINGLE(VPOG0, VPO24, M21_DESC, VPO24_DESC); +SIG_EXPR_DECL_SINGLE(VPOG0, VPOOFF1, M21_DESC, VPOOFF1_DESC); +SIG_EXPR_LIST_DECL(VPOG0, VPO, + SIG_EXPR_PTR(VPOG0, VPO12), + SIG_EXPR_PTR(VPOG0, VPO24), + SIG_EXPR_PTR(VPOG0, VPOOFF1)); +SIG_EXPR_LIST_ALIAS(M21, VPOG0, VPO); +PIN_DECL_2(M21, GPIOAA0, ROMA10, VPOG0); #define M22 209 #define M22_DESC SIG_DESC_SET(SCUA4, 25) -SIG_EXPR_DECL(ROMA11, ROM8, M22_DESC, VPOOFF0_DESC); -SIG_EXPR_DECL(ROMA11, ROM16, M22_DESC, VPOOFF0_DESC); -SIG_EXPR_LIST_DECL_DUAL(ROMA11, ROM8, ROM16); -SIG_EXPR_DECL(VPOG1, VPO12, M22_DESC, VPO12_DESC); -SIG_EXPR_DECL(VPOG1, VPO24, M22_DESC, VPO24_DESC); -SIG_EXPR_DECL(VPOG1, VPOOFF1, M22_DESC, VPOOFF1_DESC); -SIG_EXPR_LIST_DECL(VPOG1, SIG_EXPR_PTR(VPOG1, VPO12), - SIG_EXPR_PTR(VPOG1, VPO24), SIG_EXPR_PTR(VPOG1, VPOOFF1)); -MS_PIN_DECL(M22, GPIOAA1, ROMA11, VPOG1); +SIG_EXPR_DECL_SINGLE(ROMA11, ROM8, M22_DESC, VPOOFF0_DESC); +SIG_EXPR_DECL_SINGLE(ROMA11, ROM16, M22_DESC, VPOOFF0_DESC); +SIG_EXPR_LIST_DECL_DUAL(M22, ROMA11, ROM8, ROM16); +SIG_EXPR_DECL_SINGLE(VPOG1, VPO12, M22_DESC, VPO12_DESC); +SIG_EXPR_DECL_SINGLE(VPOG1, VPO24, M22_DESC, VPO24_DESC); +SIG_EXPR_DECL_SINGLE(VPOG1, VPOOFF1, M22_DESC, VPOOFF1_DESC); +SIG_EXPR_LIST_DECL(VPOG1, VPO, + SIG_EXPR_PTR(VPOG1, VPO12), + SIG_EXPR_PTR(VPOG1, VPO24), + SIG_EXPR_PTR(VPOG1, VPOOFF1)); +SIG_EXPR_LIST_ALIAS(M22, VPOG1, VPO); +PIN_DECL_2(M22, GPIOAA1, ROMA11, VPOG1); #define L18 210 #define L18_DESC SIG_DESC_SET(SCUA4, 26) -SIG_EXPR_DECL(ROMA12, ROM8, L18_DESC, VPOOFF0_DESC); -SIG_EXPR_DECL(ROMA12, ROM16, L18_DESC, VPOOFF0_DESC); -SIG_EXPR_LIST_DECL_DUAL(ROMA12, ROM8, ROM16); -SIG_EXPR_DECL(VPOG2, VPO12, L18_DESC, VPO12_DESC); -SIG_EXPR_DECL(VPOG2, VPO24, L18_DESC, VPO24_DESC); -SIG_EXPR_DECL(VPOG2, VPOOFF1, L18_DESC, VPOOFF1_DESC); -SIG_EXPR_LIST_DECL(VPOG2, SIG_EXPR_PTR(VPOG2, VPO12), - SIG_EXPR_PTR(VPOG2, VPO24), SIG_EXPR_PTR(VPOG2, VPOOFF1)); -MS_PIN_DECL(L18, GPIOAA2, ROMA12, VPOG2); +SIG_EXPR_DECL_SINGLE(ROMA12, ROM8, L18_DESC, VPOOFF0_DESC); +SIG_EXPR_DECL_SINGLE(ROMA12, ROM16, L18_DESC, VPOOFF0_DESC); +SIG_EXPR_LIST_DECL_DUAL(L18, ROMA12, ROM8, ROM16); +SIG_EXPR_DECL_SINGLE(VPOG2, VPO12, L18_DESC, VPO12_DESC); +SIG_EXPR_DECL_SINGLE(VPOG2, VPO24, L18_DESC, VPO24_DESC); +SIG_EXPR_DECL_SINGLE(VPOG2, VPOOFF1, L18_DESC, VPOOFF1_DESC); +SIG_EXPR_LIST_DECL(VPOG2, VPO, + SIG_EXPR_PTR(VPOG2, VPO12), + SIG_EXPR_PTR(VPOG2, VPO24), + SIG_EXPR_PTR(VPOG2, VPOOFF1)); +SIG_EXPR_LIST_ALIAS(L18, VPOG2, VPO); +PIN_DECL_2(L18, GPIOAA2, ROMA12, VPOG2); #define L19 211 #define L19_DESC SIG_DESC_SET(SCUA4, 27) -SIG_EXPR_DECL(ROMA13, ROM8, L19_DESC, VPOOFF0_DESC); -SIG_EXPR_DECL(ROMA13, ROM16, L19_DESC, VPOOFF0_DESC); -SIG_EXPR_LIST_DECL_DUAL(ROMA13, ROM8, ROM16); -SIG_EXPR_DECL(VPOG3, VPO12, L19_DESC, VPO12_DESC); -SIG_EXPR_DECL(VPOG3, VPO24, L19_DESC, VPO24_DESC); -SIG_EXPR_DECL(VPOG3, VPOOFF1, L19_DESC, VPOOFF1_DESC); -SIG_EXPR_LIST_DECL(VPOG3, SIG_EXPR_PTR(VPOG3, VPO12), - SIG_EXPR_PTR(VPOG3, VPO24), SIG_EXPR_PTR(VPOG3, VPOOFF1)); -MS_PIN_DECL(L19, GPIOAA3, ROMA13, VPOG3); +SIG_EXPR_DECL_SINGLE(ROMA13, ROM8, L19_DESC, VPOOFF0_DESC); +SIG_EXPR_DECL_SINGLE(ROMA13, ROM16, L19_DESC, VPOOFF0_DESC); +SIG_EXPR_LIST_DECL_DUAL(L19, ROMA13, ROM8, ROM16); +SIG_EXPR_DECL_SINGLE(VPOG3, VPO12, L19_DESC, VPO12_DESC); +SIG_EXPR_DECL_SINGLE(VPOG3, VPO24, L19_DESC, VPO24_DESC); +SIG_EXPR_DECL_SINGLE(VPOG3, VPOOFF1, L19_DESC, VPOOFF1_DESC); +SIG_EXPR_LIST_DECL(VPOG3, VPO, + SIG_EXPR_PTR(VPOG3, VPO12), + SIG_EXPR_PTR(VPOG3, VPO24), + SIG_EXPR_PTR(VPOG3, VPOOFF1)); +SIG_EXPR_LIST_ALIAS(L19, VPOG3, VPO); +PIN_DECL_2(L19, GPIOAA3, ROMA13, VPOG3); #define L20 212 #define L20_DESC SIG_DESC_SET(SCUA4, 28) -SIG_EXPR_DECL(ROMA14, ROM8, L20_DESC, VPO_OFF_12); -SIG_EXPR_DECL(ROMA14, ROM16, L20_DESC, VPO_OFF_12); -SIG_EXPR_LIST_DECL_DUAL(ROMA14, ROM8, ROM16); -SIG_EXPR_DECL(VPOG4, VPO24, L20_DESC, VPO24_DESC); -SIG_EXPR_DECL(VPOG4, VPOOFF1, L20_DESC, VPOOFF1_DESC); -SIG_EXPR_LIST_DECL_DUAL(VPOG4, VPO24, VPOOFF1); -MS_PIN_DECL(L20, GPIOAA4, ROMA14, VPOG4); +SIG_EXPR_DECL_SINGLE(ROMA14, ROM8, L20_DESC, VPO_OFF_12); +SIG_EXPR_DECL_SINGLE(ROMA14, ROM16, L20_DESC, VPO_OFF_12); +SIG_EXPR_LIST_DECL_DUAL(L20, ROMA14, ROM8, ROM16); +SIG_EXPR_DECL_SINGLE(VPOG4, VPO24, L20_DESC, VPO24_DESC); +SIG_EXPR_DECL_SINGLE(VPOG4, VPOOFF1, L20_DESC, VPOOFF1_DESC); +SIG_EXPR_LIST_DECL_DUAL(L20, VPOG4, VPO24, VPOOFF1); +PIN_DECL_2(L20, GPIOAA4, ROMA14, VPOG4); #define L21 213 #define L21_DESC SIG_DESC_SET(SCUA4, 29) -SIG_EXPR_DECL(ROMA15, ROM8, L21_DESC, VPO_OFF_12); -SIG_EXPR_DECL(ROMA15, ROM16, L21_DESC, VPO_OFF_12); -SIG_EXPR_LIST_DECL_DUAL(ROMA15, ROM8, ROM16); -SIG_EXPR_DECL(VPOG5, VPO24, L21_DESC, VPO24_DESC); -SIG_EXPR_DECL(VPOG5, VPOOFF1, L21_DESC, VPOOFF1_DESC); -SIG_EXPR_LIST_DECL_DUAL(VPOG5, VPO24, VPOOFF1); -MS_PIN_DECL(L21, GPIOAA5, ROMA15, VPOG5); +SIG_EXPR_DECL_SINGLE(ROMA15, ROM8, L21_DESC, VPO_OFF_12); +SIG_EXPR_DECL_SINGLE(ROMA15, ROM16, L21_DESC, VPO_OFF_12); +SIG_EXPR_LIST_DECL_DUAL(L21, ROMA15, ROM8, ROM16); +SIG_EXPR_DECL_SINGLE(VPOG5, VPO24, L21_DESC, VPO24_DESC); +SIG_EXPR_DECL_SINGLE(VPOG5, VPOOFF1, L21_DESC, VPOOFF1_DESC); +SIG_EXPR_LIST_DECL_DUAL(L21, VPOG5, VPO24, VPOOFF1); +PIN_DECL_2(L21, GPIOAA5, ROMA15, VPOG5); #define T18 214 #define T18_DESC SIG_DESC_SET(SCUA4, 30) -SIG_EXPR_DECL(ROMA16, ROM8, T18_DESC, VPO_OFF_12); -SIG_EXPR_DECL(ROMA16, ROM16, T18_DESC, VPO_OFF_12); -SIG_EXPR_LIST_DECL_DUAL(ROMA16, ROM8, ROM16); -SIG_EXPR_DECL(VPOG6, VPO24, T18_DESC, VPO24_DESC); -SIG_EXPR_DECL(VPOG6, VPOOFF1, T18_DESC, VPOOFF1_DESC); -SIG_EXPR_LIST_DECL_DUAL(VPOG6, VPO24, VPOOFF1); -MS_PIN_DECL(T18, GPIOAA6, ROMA16, VPOG6); +SIG_EXPR_DECL_SINGLE(ROMA16, ROM8, T18_DESC, VPO_OFF_12); +SIG_EXPR_DECL_SINGLE(ROMA16, ROM16, T18_DESC, VPO_OFF_12); +SIG_EXPR_LIST_DECL_DUAL(T18, ROMA16, ROM8, ROM16); +SIG_EXPR_DECL_SINGLE(VPOG6, VPO24, T18_DESC, VPO24_DESC); +SIG_EXPR_DECL_SINGLE(VPOG6, VPOOFF1, T18_DESC, VPOOFF1_DESC); +SIG_EXPR_LIST_DECL_DUAL(T18, VPOG6, VPO24, VPOOFF1); +PIN_DECL_2(T18, GPIOAA6, ROMA16, VPOG6); #define N18 215 #define N18_DESC SIG_DESC_SET(SCUA4, 31) -SIG_EXPR_DECL(ROMA17, ROM8, N18_DESC, VPO_OFF_12); -SIG_EXPR_DECL(ROMA17, ROM16, N18_DESC, VPO_OFF_12); -SIG_EXPR_LIST_DECL_DUAL(ROMA17, ROM8, ROM16); -SIG_EXPR_DECL(VPOG7, VPO24, N18_DESC, VPO24_DESC); -SIG_EXPR_DECL(VPOG7, VPOOFF1, N18_DESC, VPOOFF1_DESC); -SIG_EXPR_LIST_DECL_DUAL(VPOG7, VPO24, VPOOFF1); -MS_PIN_DECL(N18, GPIOAA7, ROMA17, VPOG7); +SIG_EXPR_DECL_SINGLE(ROMA17, ROM8, N18_DESC, VPO_OFF_12); +SIG_EXPR_DECL_SINGLE(ROMA17, ROM16, N18_DESC, VPO_OFF_12); +SIG_EXPR_LIST_DECL_DUAL(N18, ROMA17, ROM8, ROM16); +SIG_EXPR_DECL_SINGLE(VPOG7, VPO24, N18_DESC, VPO24_DESC); +SIG_EXPR_DECL_SINGLE(VPOG7, VPOOFF1, N18_DESC, VPOOFF1_DESC); +SIG_EXPR_LIST_DECL_DUAL(N18, VPOG7, VPO24, VPOOFF1); +PIN_DECL_2(N18, GPIOAA7, ROMA17, VPOG7); #define N19 216 #define N19_DESC SIG_DESC_SET(SCUA8, 0) -SIG_EXPR_DECL(ROMA18, ROM8, N19_DESC, VPO_OFF_12); -SIG_EXPR_DECL(ROMA18, ROM16, N19_DESC, VPO_OFF_12); -SIG_EXPR_LIST_DECL_DUAL(ROMA18, ROM8, ROM16); -SIG_EXPR_DECL(VPOR0, VPO24, N19_DESC, VPO24_DESC); -SIG_EXPR_DECL(VPOR0, VPOOFF1, N19_DESC, VPOOFF1_DESC); -SIG_EXPR_LIST_DECL_DUAL(VPOR0, VPO24, VPOOFF1); -MS_PIN_DECL(N19, GPIOAB0, ROMA18, VPOR0); +SIG_EXPR_DECL_SINGLE(ROMA18, ROM8, N19_DESC, VPO_OFF_12); +SIG_EXPR_DECL_SINGLE(ROMA18, ROM16, N19_DESC, VPO_OFF_12); +SIG_EXPR_LIST_DECL_DUAL(N19, ROMA18, ROM8, ROM16); +SIG_EXPR_DECL_SINGLE(VPOR0, VPO24, N19_DESC, VPO24_DESC); +SIG_EXPR_DECL_SINGLE(VPOR0, VPOOFF1, N19_DESC, VPOOFF1_DESC); +SIG_EXPR_LIST_DECL_DUAL(N19, VPOR0, VPO24, VPOOFF1); +PIN_DECL_2(N19, GPIOAB0, ROMA18, VPOR0); #define M18 217 #define M18_DESC SIG_DESC_SET(SCUA8, 1) -SIG_EXPR_DECL(ROMA19, ROM8, M18_DESC, VPO_OFF_12); -SIG_EXPR_DECL(ROMA19, ROM16, M18_DESC, VPO_OFF_12); -SIG_EXPR_LIST_DECL_DUAL(ROMA19, ROM8, ROM16); -SIG_EXPR_DECL(VPOR1, VPO24, M18_DESC, VPO24_DESC); -SIG_EXPR_DECL(VPOR1, VPOOFF1, M18_DESC, VPOOFF1_DESC); -SIG_EXPR_LIST_DECL_DUAL(VPOR1, VPO24, VPOOFF1); -MS_PIN_DECL(M18, GPIOAB1, ROMA19, VPOR1); +SIG_EXPR_DECL_SINGLE(ROMA19, ROM8, M18_DESC, VPO_OFF_12); +SIG_EXPR_DECL_SINGLE(ROMA19, ROM16, M18_DESC, VPO_OFF_12); +SIG_EXPR_LIST_DECL_DUAL(M18, ROMA19, ROM8, ROM16); +SIG_EXPR_DECL_SINGLE(VPOR1, VPO24, M18_DESC, VPO24_DESC); +SIG_EXPR_DECL_SINGLE(VPOR1, VPOOFF1, M18_DESC, VPOOFF1_DESC); +SIG_EXPR_LIST_DECL_DUAL(M18, VPOR1, VPO24, VPOOFF1); +PIN_DECL_2(M18, GPIOAB1, ROMA19, VPOR1); #define N22 218 #define N22_DESC SIG_DESC_SET(SCUA8, 2) -SIG_EXPR_DECL(ROMA20, ROM8, N22_DESC, VPO_OFF_12); -SIG_EXPR_DECL(ROMA20, ROM16, N22_DESC, VPO_OFF_12); -SIG_EXPR_LIST_DECL_DUAL(ROMA20, ROM8, ROM16); -SIG_EXPR_DECL(VPOR2, VPO24, N22_DESC, VPO24_DESC); -SIG_EXPR_DECL(VPOR2, VPOOFF1, N22_DESC, VPOOFF1_DESC); -SIG_EXPR_LIST_DECL_DUAL(VPOR2, VPO24, VPOOFF1); -MS_PIN_DECL(N22, GPIOAB2, ROMA20, VPOR2); +SIG_EXPR_DECL_SINGLE(ROMA20, ROM8, N22_DESC, VPO_OFF_12); +SIG_EXPR_DECL_SINGLE(ROMA20, ROM16, N22_DESC, VPO_OFF_12); +SIG_EXPR_LIST_DECL_DUAL(N22, ROMA20, ROM8, ROM16); +SIG_EXPR_DECL_SINGLE(VPOR2, VPO24, N22_DESC, VPO24_DESC); +SIG_EXPR_DECL_SINGLE(VPOR2, VPOOFF1, N22_DESC, VPOOFF1_DESC); +SIG_EXPR_LIST_DECL_DUAL(N22, VPOR2, VPO24, VPOOFF1); +PIN_DECL_2(N22, GPIOAB2, ROMA20, VPOR2); #define N20 219 #define N20_DESC SIG_DESC_SET(SCUA8, 3) -SIG_EXPR_DECL(ROMA21, ROM8, N20_DESC, VPO_OFF_12); -SIG_EXPR_DECL(ROMA21, ROM16, N20_DESC, VPO_OFF_12); -SIG_EXPR_LIST_DECL_DUAL(ROMA21, ROM8, ROM16); -SIG_EXPR_DECL(VPOR3, VPO24, N20_DESC, VPO24_DESC); -SIG_EXPR_DECL(VPOR3, VPOOFF1, N20_DESC, VPOOFF1_DESC); -SIG_EXPR_LIST_DECL_DUAL(VPOR3, VPO24, VPOOFF1); -MS_PIN_DECL(N20, GPIOAB3, ROMA21, VPOR3); +SIG_EXPR_DECL_SINGLE(ROMA21, ROM8, N20_DESC, VPO_OFF_12); +SIG_EXPR_DECL_SINGLE(ROMA21, ROM16, N20_DESC, VPO_OFF_12); +SIG_EXPR_LIST_DECL_DUAL(N20, ROMA21, ROM8, ROM16); +SIG_EXPR_DECL_SINGLE(VPOR3, VPO24, N20_DESC, VPO24_DESC); +SIG_EXPR_DECL_SINGLE(VPOR3, VPOOFF1, N20_DESC, VPOOFF1_DESC); +SIG_EXPR_LIST_DECL_DUAL(N20, VPOR3, VPO24, VPOOFF1); +PIN_DECL_2(N20, GPIOAB3, ROMA21, VPOR3); FUNC_GROUP_DECL(ROM8, V20, U21, T19, V22, U20, R18, N21, L22, K18, W21, Y22, U19, R22, P18, P19, P20, P21, P22, M19, M20, M21, M22, L18, @@ -1740,14 +1865,16 @@ FUNC_GROUP_DECL(VPO24, U21, T19, V22, U20, L22, K18, V21, W22, R22, P18, P19, #define USB11D1_DESC SIG_DESC_BIT(SCU90, 3, 0) #define K4 220 -SIG_EXPR_LIST_DECL_SINGLE(USB11HDP2, USB11H2, USB11H2_DESC); -SIG_EXPR_LIST_DECL_SINGLE(USB11DP1, USB11D1, USB11D1_DESC); -MS_PIN_DECL_(K4, SIG_EXPR_LIST_PTR(USB11HDP2), SIG_EXPR_LIST_PTR(USB11DP1)); +SIG_EXPR_LIST_DECL_SINGLE(K4, USB11HDP2, USB11H2, USB11H2_DESC); +SIG_EXPR_LIST_DECL_SINGLE(K4, USB11DP1, USB11D1, USB11D1_DESC); +PIN_DECL_(K4, SIG_EXPR_LIST_PTR(K4, USB11HDP2), + SIG_EXPR_LIST_PTR(K4, USB11DP1)); #define K3 221 -SIG_EXPR_LIST_DECL_SINGLE(USB11HDN1, USB11H2, USB11H2_DESC); -SIG_EXPR_LIST_DECL_SINGLE(USB11DDN1, USB11D1, USB11D1_DESC); -MS_PIN_DECL_(K3, SIG_EXPR_LIST_PTR(USB11HDN1), SIG_EXPR_LIST_PTR(USB11DDN1)); +SIG_EXPR_LIST_DECL_SINGLE(K3, USB11HDN1, USB11H2, USB11H2_DESC); +SIG_EXPR_LIST_DECL_SINGLE(K3, USB11DDN1, USB11D1, USB11D1_DESC); +PIN_DECL_(K3, SIG_EXPR_LIST_PTR(K3, USB11HDN1), + SIG_EXPR_LIST_PTR(K3, USB11DDN1)); FUNC_GROUP_DECL(USB11H2, K4, K3); FUNC_GROUP_DECL(USB11D1, K4, K3); @@ -1756,14 +1883,16 @@ FUNC_GROUP_DECL(USB11D1, K4, K3); #define USB2D1_DESC SIG_DESC_BIT(SCU90, 29, 0) #define AB21 222 -SIG_EXPR_LIST_DECL_SINGLE(USB2HDP1, USB2H1, USB2H1_DESC); -SIG_EXPR_LIST_DECL_SINGLE(USB2DDP1, USB2D1, USB2D1_DESC); -MS_PIN_DECL_(AB21, SIG_EXPR_LIST_PTR(USB2HDP1), SIG_EXPR_LIST_PTR(USB2DDP1)); +SIG_EXPR_LIST_DECL_SINGLE(AB21, USB2HDP1, USB2H1, USB2H1_DESC); +SIG_EXPR_LIST_DECL_SINGLE(AB21, USB2DDP1, USB2D1, USB2D1_DESC); +PIN_DECL_(AB21, SIG_EXPR_LIST_PTR(AB21, USB2HDP1), + SIG_EXPR_LIST_PTR(AB21, USB2DDP1)); #define AB20 223 -SIG_EXPR_LIST_DECL_SINGLE(USB2HDN1, USB2H1, USB2H1_DESC); -SIG_EXPR_LIST_DECL_SINGLE(USB2DDN1, USB2D1, USB2D1_DESC); -MS_PIN_DECL_(AB20, SIG_EXPR_LIST_PTR(USB2HDN1), SIG_EXPR_LIST_PTR(USB2DDN1)); +SIG_EXPR_LIST_DECL_SINGLE(AB20, USB2HDN1, USB2H1, USB2H1_DESC); +SIG_EXPR_LIST_DECL_SINGLE(AB20, USB2DDN1, USB2D1, USB2D1_DESC); +PIN_DECL_(AB20, SIG_EXPR_LIST_PTR(AB20, USB2HDN1), + SIG_EXPR_LIST_PTR(AB20, USB2DDN1)); FUNC_GROUP_DECL(USB2H1, AB21, AB20); FUNC_GROUP_DECL(USB2D1, AB21, AB20); @@ -2531,6 +2660,10 @@ static int aspeed_g4_pinctrl_probe(struct platform_device *pdev) static const struct of_device_id aspeed_g4_pinctrl_of_match[] = { { .compatible = "aspeed,ast2400-pinctrl", }, + /* + * The aspeed,g4-pinctrl compatible has been removed the from the + * bindings, but keep the match in case of old devicetrees. + */ { .compatible = "aspeed,g4-pinctrl", }, { }, }; diff --git a/drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c b/drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c index ff84d1afd229..d8a804b9f958 100644 --- a/drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c +++ b/drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c @@ -21,6 +21,13 @@ #include "../pinctrl-utils.h" #include "pinctrl-aspeed.h" +/* Wrap some of the common macros for clarity */ +#define SIG_EXPR_DECL_SINGLE(sig, func, ...) \ + SIG_EXPR_DECL(sig, func, func, __VA_ARGS__) + +#define SIG_EXPR_LIST_DECL_SINGLE SIG_EXPR_LIST_DECL_SESG +#define SIG_EXPR_LIST_DECL_DUAL SIG_EXPR_LIST_DECL_DESG + /* * The "Multi-function Pins Mapping and Control" table in the SoC datasheet * references registers by the device/offset mnemonic. The register macros @@ -63,9 +70,9 @@ SSSF_PIN_DECL(B14, GPIOA0, MAC1LINK, SIG_DESC_SET(SCU80, 0)); SSSF_PIN_DECL(D14, GPIOA1, MAC2LINK, SIG_DESC_SET(SCU80, 1)); #define D13 2 -SIG_EXPR_LIST_DECL_SINGLE(SPI1CS1, SPI1CS1, SIG_DESC_SET(SCU80, 15)); -SIG_EXPR_LIST_DECL_SINGLE(TIMER3, TIMER3, SIG_DESC_SET(SCU80, 2)); -MS_PIN_DECL(D13, GPIOA2, SPI1CS1, TIMER3); +SIG_EXPR_LIST_DECL_SINGLE(D13, SPI1CS1, SPI1CS1, SIG_DESC_SET(SCU80, 15)); +SIG_EXPR_LIST_DECL_SINGLE(D13, TIMER3, TIMER3, SIG_DESC_SET(SCU80, 2)); +PIN_DECL_2(D13, GPIOA2, SPI1CS1, TIMER3); FUNC_GROUP_DECL(SPI1CS1, D13); FUNC_GROUP_DECL(TIMER3, D13); @@ -75,16 +82,16 @@ SSSF_PIN_DECL(E13, GPIOA3, TIMER4, SIG_DESC_SET(SCU80, 3)); #define I2C9_DESC SIG_DESC_SET(SCU90, 22) #define C14 4 -SIG_EXPR_LIST_DECL_SINGLE(SCL9, I2C9, I2C9_DESC, COND1); -SIG_EXPR_LIST_DECL_SINGLE(TIMER5, TIMER5, SIG_DESC_SET(SCU80, 4), COND1); -MS_PIN_DECL(C14, GPIOA4, SCL9, TIMER5); +SIG_EXPR_LIST_DECL_SINGLE(C14, SCL9, I2C9, I2C9_DESC, COND1); +SIG_EXPR_LIST_DECL_SINGLE(C14, TIMER5, TIMER5, SIG_DESC_SET(SCU80, 4), COND1); +PIN_DECL_2(C14, GPIOA4, SCL9, TIMER5); FUNC_GROUP_DECL(TIMER5, C14); #define A13 5 -SIG_EXPR_LIST_DECL_SINGLE(SDA9, I2C9, I2C9_DESC, COND1); -SIG_EXPR_LIST_DECL_SINGLE(TIMER6, TIMER6, SIG_DESC_SET(SCU80, 5), COND1); -MS_PIN_DECL(A13, GPIOA5, SDA9, TIMER6); +SIG_EXPR_LIST_DECL_SINGLE(A13, SDA9, I2C9, I2C9_DESC, COND1); +SIG_EXPR_LIST_DECL_SINGLE(A13, TIMER6, TIMER6, SIG_DESC_SET(SCU80, 5), COND1); +PIN_DECL_2(A13, GPIOA5, SDA9, TIMER6); FUNC_GROUP_DECL(TIMER6, A13); @@ -93,16 +100,16 @@ FUNC_GROUP_DECL(I2C9, C14, A13); #define MDIO2_DESC SIG_DESC_SET(SCU90, 2) #define C13 6 -SIG_EXPR_LIST_DECL_SINGLE(MDC2, MDIO2, MDIO2_DESC, COND1); -SIG_EXPR_LIST_DECL_SINGLE(TIMER7, TIMER7, SIG_DESC_SET(SCU80, 6), COND1); -MS_PIN_DECL(C13, GPIOA6, MDC2, TIMER7); +SIG_EXPR_LIST_DECL_SINGLE(C13, MDC2, MDIO2, MDIO2_DESC, COND1); +SIG_EXPR_LIST_DECL_SINGLE(C13, TIMER7, TIMER7, SIG_DESC_SET(SCU80, 6), COND1); +PIN_DECL_2(C13, GPIOA6, MDC2, TIMER7); FUNC_GROUP_DECL(TIMER7, C13); #define B13 7 -SIG_EXPR_LIST_DECL_SINGLE(MDIO2, MDIO2, MDIO2_DESC, COND1); -SIG_EXPR_LIST_DECL_SINGLE(TIMER8, TIMER8, SIG_DESC_SET(SCU80, 7), COND1); -MS_PIN_DECL(B13, GPIOA7, MDIO2, TIMER8); +SIG_EXPR_LIST_DECL_SINGLE(B13, MDIO2, MDIO2, MDIO2_DESC, COND1); +SIG_EXPR_LIST_DECL_SINGLE(B13, TIMER8, TIMER8, SIG_DESC_SET(SCU80, 7), COND1); +PIN_DECL_2(B13, GPIOA7, MDIO2, TIMER8); FUNC_GROUP_DECL(TIMER8, B13); @@ -125,9 +132,9 @@ SSSF_PIN_DECL(J20, GPIOB4, USBCKI, SIG_DESC_SET(HW_STRAP1, 23)); #define H21 13 #define H21_DESC SIG_DESC_SET(SCU80, 13) -SIG_EXPR_LIST_DECL_SINGLE(LPCPD, LPCPD, H21_DESC); -SIG_EXPR_LIST_DECL_SINGLE(LPCSMI, LPCSMI, H21_DESC); -MS_PIN_DECL(H21, GPIOB5, LPCPD, LPCSMI); +SIG_EXPR_LIST_DECL_SINGLE(H21, LPCPD, LPCPD, H21_DESC); +SIG_EXPR_LIST_DECL_SINGLE(H21, LPCSMI, LPCSMI, H21_DESC); +PIN_DECL_2(H21, GPIOB5, LPCPD, LPCSMI); FUNC_GROUP_DECL(LPCPD, H21); FUNC_GROUP_DECL(LPCSMI, H21); @@ -141,53 +148,53 @@ GPIO_PIN_DECL(H20, GPIOB7); #define C12 16 #define I2C10_DESC SIG_DESC_SET(SCU90, 23) -SIG_EXPR_LIST_DECL_SINGLE(SD1CLK, SD1, SD1_DESC); -SIG_EXPR_LIST_DECL_SINGLE(SCL10, I2C10, I2C10_DESC); -MS_PIN_DECL(C12, GPIOC0, SD1CLK, SCL10); +SIG_EXPR_LIST_DECL_SINGLE(C12, SD1CLK, SD1, SD1_DESC); +SIG_EXPR_LIST_DECL_SINGLE(C12, SCL10, I2C10, I2C10_DESC); +PIN_DECL_2(C12, GPIOC0, SD1CLK, SCL10); #define A12 17 -SIG_EXPR_LIST_DECL_SINGLE(SD1CMD, SD1, SD1_DESC); -SIG_EXPR_LIST_DECL_SINGLE(SDA10, I2C10, I2C10_DESC); -MS_PIN_DECL(A12, GPIOC1, SD1CMD, SDA10); +SIG_EXPR_LIST_DECL_SINGLE(A12, SD1CMD, SD1, SD1_DESC); +SIG_EXPR_LIST_DECL_SINGLE(A12, SDA10, I2C10, I2C10_DESC); +PIN_DECL_2(A12, GPIOC1, SD1CMD, SDA10); FUNC_GROUP_DECL(I2C10, C12, A12); #define B12 18 #define I2C11_DESC SIG_DESC_SET(SCU90, 24) -SIG_EXPR_LIST_DECL_SINGLE(SD1DAT0, SD1, SD1_DESC); -SIG_EXPR_LIST_DECL_SINGLE(SCL11, I2C11, I2C11_DESC); -MS_PIN_DECL(B12, GPIOC2, SD1DAT0, SCL11); +SIG_EXPR_LIST_DECL_SINGLE(B12, SD1DAT0, SD1, SD1_DESC); +SIG_EXPR_LIST_DECL_SINGLE(B12, SCL11, I2C11, I2C11_DESC); +PIN_DECL_2(B12, GPIOC2, SD1DAT0, SCL11); #define D9 19 -SIG_EXPR_LIST_DECL_SINGLE(SD1DAT1, SD1, SD1_DESC); -SIG_EXPR_LIST_DECL_SINGLE(SDA11, I2C11, I2C11_DESC); -MS_PIN_DECL(D9, GPIOC3, SD1DAT1, SDA11); +SIG_EXPR_LIST_DECL_SINGLE(D9, SD1DAT1, SD1, SD1_DESC); +SIG_EXPR_LIST_DECL_SINGLE(D9, SDA11, I2C11, I2C11_DESC); +PIN_DECL_2(D9, GPIOC3, SD1DAT1, SDA11); FUNC_GROUP_DECL(I2C11, B12, D9); #define D10 20 #define I2C12_DESC SIG_DESC_SET(SCU90, 25) -SIG_EXPR_LIST_DECL_SINGLE(SD1DAT2, SD1, SD1_DESC); -SIG_EXPR_LIST_DECL_SINGLE(SCL12, I2C12, I2C12_DESC); -MS_PIN_DECL(D10, GPIOC4, SD1DAT2, SCL12); +SIG_EXPR_LIST_DECL_SINGLE(D10, SD1DAT2, SD1, SD1_DESC); +SIG_EXPR_LIST_DECL_SINGLE(D10, SCL12, I2C12, I2C12_DESC); +PIN_DECL_2(D10, GPIOC4, SD1DAT2, SCL12); #define E12 21 -SIG_EXPR_LIST_DECL_SINGLE(SD1DAT3, SD1, SD1_DESC); -SIG_EXPR_LIST_DECL_SINGLE(SDA12, I2C12, I2C12_DESC); -MS_PIN_DECL(E12, GPIOC5, SD1DAT3, SDA12); +SIG_EXPR_LIST_DECL_SINGLE(E12, SD1DAT3, SD1, SD1_DESC); +SIG_EXPR_LIST_DECL_SINGLE(E12, SDA12, I2C12, I2C12_DESC); +PIN_DECL_2(E12, GPIOC5, SD1DAT3, SDA12); FUNC_GROUP_DECL(I2C12, D10, E12); #define C11 22 #define I2C13_DESC SIG_DESC_SET(SCU90, 26) -SIG_EXPR_LIST_DECL_SINGLE(SD1CD, SD1, SD1_DESC); -SIG_EXPR_LIST_DECL_SINGLE(SCL13, I2C13, I2C13_DESC); -MS_PIN_DECL(C11, GPIOC6, SD1CD, SCL13); +SIG_EXPR_LIST_DECL_SINGLE(C11, SD1CD, SD1, SD1_DESC); +SIG_EXPR_LIST_DECL_SINGLE(C11, SCL13, I2C13, I2C13_DESC); +PIN_DECL_2(C11, GPIOC6, SD1CD, SCL13); #define B11 23 -SIG_EXPR_LIST_DECL_SINGLE(SD1WP, SD1, SD1_DESC); -SIG_EXPR_LIST_DECL_SINGLE(SDA13, I2C13, I2C13_DESC); -MS_PIN_DECL(B11, GPIOC7, SD1WP, SDA13); +SIG_EXPR_LIST_DECL_SINGLE(B11, SD1WP, SD1, SD1_DESC); +SIG_EXPR_LIST_DECL_SINGLE(B11, SDA13, I2C13, I2C13_DESC); +PIN_DECL_2(B11, GPIOC7, SD1WP, SDA13); FUNC_GROUP_DECL(I2C13, C11, B11); FUNC_GROUP_DECL(SD1, C12, A12, B12, D9, D10, E12, C11, B11); @@ -197,72 +204,72 @@ FUNC_GROUP_DECL(SD1, C12, A12, B12, D9, D10, E12, C11, B11); #define GPID_DESC SIG_DESC_SET(HW_STRAP1, 21) #define F19 24 -SIG_EXPR_LIST_DECL_SINGLE(SD2CLK, SD2, SD2_DESC); -SIG_EXPR_DECL(GPID0IN, GPID0, GPID0_DESC); -SIG_EXPR_DECL(GPID0IN, GPID, GPID_DESC); -SIG_EXPR_LIST_DECL_DUAL(GPID0IN, GPID0, GPID); -MS_PIN_DECL(F19, GPIOD0, SD2CLK, GPID0IN); +SIG_EXPR_LIST_DECL_SINGLE(F19, SD2CLK, SD2, SD2_DESC); +SIG_EXPR_DECL_SINGLE(GPID0IN, GPID0, GPID0_DESC); +SIG_EXPR_DECL_SINGLE(GPID0IN, GPID, GPID_DESC); +SIG_EXPR_LIST_DECL_DUAL(F19, GPID0IN, GPID0, GPID); +PIN_DECL_2(F19, GPIOD0, SD2CLK, GPID0IN); #define E21 25 -SIG_EXPR_LIST_DECL_SINGLE(SD2CMD, SD2, SD2_DESC); -SIG_EXPR_DECL(GPID0OUT, GPID0, GPID0_DESC); -SIG_EXPR_DECL(GPID0OUT, GPID, GPID_DESC); -SIG_EXPR_LIST_DECL_DUAL(GPID0OUT, GPID0, GPID); -MS_PIN_DECL(E21, GPIOD1, SD2CMD, GPID0OUT); +SIG_EXPR_LIST_DECL_SINGLE(E21, SD2CMD, SD2, SD2_DESC); +SIG_EXPR_DECL_SINGLE(GPID0OUT, GPID0, GPID0_DESC); +SIG_EXPR_DECL_SINGLE(GPID0OUT, GPID, GPID_DESC); +SIG_EXPR_LIST_DECL_DUAL(E21, GPID0OUT, GPID0, GPID); +PIN_DECL_2(E21, GPIOD1, SD2CMD, GPID0OUT); FUNC_GROUP_DECL(GPID0, F19, E21); #define GPID2_DESC SIG_DESC_SET(SCU8C, 9) #define F20 26 -SIG_EXPR_LIST_DECL_SINGLE(SD2DAT0, SD2, SD2_DESC); -SIG_EXPR_DECL(GPID2IN, GPID2, GPID2_DESC); -SIG_EXPR_DECL(GPID2IN, GPID, GPID_DESC); -SIG_EXPR_LIST_DECL_DUAL(GPID2IN, GPID2, GPID); -MS_PIN_DECL(F20, GPIOD2, SD2DAT0, GPID2IN); +SIG_EXPR_LIST_DECL_SINGLE(F20, SD2DAT0, SD2, SD2_DESC); +SIG_EXPR_DECL_SINGLE(GPID2IN, GPID2, GPID2_DESC); +SIG_EXPR_DECL_SINGLE(GPID2IN, GPID, GPID_DESC); +SIG_EXPR_LIST_DECL_DUAL(F20, GPID2IN, GPID2, GPID); +PIN_DECL_2(F20, GPIOD2, SD2DAT0, GPID2IN); #define D20 27 -SIG_EXPR_LIST_DECL_SINGLE(SD2DAT1, SD2, SD2_DESC); -SIG_EXPR_DECL(GPID2OUT, GPID2, GPID2_DESC); -SIG_EXPR_DECL(GPID2OUT, GPID, GPID_DESC); -SIG_EXPR_LIST_DECL_DUAL(GPID2OUT, GPID2, GPID); -MS_PIN_DECL(D20, GPIOD3, SD2DAT1, GPID2OUT); +SIG_EXPR_LIST_DECL_SINGLE(D20, SD2DAT1, SD2, SD2_DESC); +SIG_EXPR_DECL_SINGLE(GPID2OUT, GPID2, GPID2_DESC); +SIG_EXPR_DECL_SINGLE(GPID2OUT, GPID, GPID_DESC); +SIG_EXPR_LIST_DECL_DUAL(D20, GPID2OUT, GPID2, GPID); +PIN_DECL_2(D20, GPIOD3, SD2DAT1, GPID2OUT); FUNC_GROUP_DECL(GPID2, F20, D20); #define GPID4_DESC SIG_DESC_SET(SCU8C, 10) #define D21 28 -SIG_EXPR_LIST_DECL_SINGLE(SD2DAT2, SD2, SD2_DESC); -SIG_EXPR_DECL(GPID4IN, GPID4, GPID4_DESC); -SIG_EXPR_DECL(GPID4IN, GPID, GPID_DESC); -SIG_EXPR_LIST_DECL_DUAL(GPID4IN, GPID4, GPID); -MS_PIN_DECL(D21, GPIOD4, SD2DAT2, GPID4IN); +SIG_EXPR_LIST_DECL_SINGLE(D21, SD2DAT2, SD2, SD2_DESC); +SIG_EXPR_DECL_SINGLE(GPID4IN, GPID4, GPID4_DESC); +SIG_EXPR_DECL_SINGLE(GPID4IN, GPID, GPID_DESC); +SIG_EXPR_LIST_DECL_DUAL(D21, GPID4IN, GPID4, GPID); +PIN_DECL_2(D21, GPIOD4, SD2DAT2, GPID4IN); #define E20 29 -SIG_EXPR_LIST_DECL_SINGLE(SD2DAT3, SD2, SD2_DESC); -SIG_EXPR_DECL(GPID4OUT, GPID4, GPID4_DESC); -SIG_EXPR_DECL(GPID4OUT, GPID, GPID_DESC); -SIG_EXPR_LIST_DECL_DUAL(GPID4OUT, GPID4, GPID); -MS_PIN_DECL(E20, GPIOD5, SD2DAT3, GPID4OUT); +SIG_EXPR_LIST_DECL_SINGLE(E20, SD2DAT3, SD2, SD2_DESC); +SIG_EXPR_DECL_SINGLE(GPID4OUT, GPID4, GPID4_DESC); +SIG_EXPR_DECL_SINGLE(GPID4OUT, GPID, GPID_DESC); +SIG_EXPR_LIST_DECL_DUAL(E20, GPID4OUT, GPID4, GPID); +PIN_DECL_2(E20, GPIOD5, SD2DAT3, GPID4OUT); FUNC_GROUP_DECL(GPID4, D21, E20); #define GPID6_DESC SIG_DESC_SET(SCU8C, 11) #define G18 30 -SIG_EXPR_LIST_DECL_SINGLE(SD2CD, SD2, SD2_DESC); -SIG_EXPR_DECL(GPID6IN, GPID6, GPID6_DESC); -SIG_EXPR_DECL(GPID6IN, GPID, GPID_DESC); -SIG_EXPR_LIST_DECL_DUAL(GPID6IN, GPID6, GPID); -MS_PIN_DECL(G18, GPIOD6, SD2CD, GPID6IN); +SIG_EXPR_LIST_DECL_SINGLE(G18, SD2CD, SD2, SD2_DESC); +SIG_EXPR_DECL_SINGLE(GPID6IN, GPID6, GPID6_DESC); +SIG_EXPR_DECL_SINGLE(GPID6IN, GPID, GPID_DESC); +SIG_EXPR_LIST_DECL_DUAL(G18, GPID6IN, GPID6, GPID); +PIN_DECL_2(G18, GPIOD6, SD2CD, GPID6IN); #define C21 31 -SIG_EXPR_LIST_DECL_SINGLE(SD2WP, SD2, SD2_DESC); -SIG_EXPR_DECL(GPID6OUT, GPID6, GPID6_DESC); -SIG_EXPR_DECL(GPID6OUT, GPID, GPID_DESC); -SIG_EXPR_LIST_DECL_DUAL(GPID6OUT, GPID6, GPID); -MS_PIN_DECL(C21, GPIOD7, SD2WP, GPID6OUT); +SIG_EXPR_LIST_DECL_SINGLE(C21, SD2WP, SD2, SD2_DESC); +SIG_EXPR_DECL_SINGLE(GPID6OUT, GPID6, GPID6_DESC); +SIG_EXPR_DECL_SINGLE(GPID6OUT, GPID, GPID_DESC); +SIG_EXPR_LIST_DECL_DUAL(C21, GPID6OUT, GPID6, GPID); +PIN_DECL_2(C21, GPIOD7, SD2WP, GPID6OUT); FUNC_GROUP_DECL(GPID6, G18, C21); FUNC_GROUP_DECL(SD2, F19, E21, F20, D20, D21, E20, G18, C21); @@ -271,19 +278,19 @@ FUNC_GROUP_DECL(SD2, F19, E21, F20, D20, D21, E20, G18, C21); #define GPIE0_DESC SIG_DESC_SET(SCU8C, 12) #define B20 32 -SIG_EXPR_LIST_DECL_SINGLE(NCTS3, NCTS3, SIG_DESC_SET(SCU80, 16)); -SIG_EXPR_DECL(GPIE0IN, GPIE0, GPIE0_DESC); -SIG_EXPR_DECL(GPIE0IN, GPIE, GPIE_DESC); -SIG_EXPR_LIST_DECL_DUAL(GPIE0IN, GPIE0, GPIE); -MS_PIN_DECL(B20, GPIOE0, NCTS3, GPIE0IN); +SIG_EXPR_LIST_DECL_SINGLE(B20, NCTS3, NCTS3, SIG_DESC_SET(SCU80, 16)); +SIG_EXPR_DECL_SINGLE(GPIE0IN, GPIE0, GPIE0_DESC); +SIG_EXPR_DECL_SINGLE(GPIE0IN, GPIE, GPIE_DESC); +SIG_EXPR_LIST_DECL_DUAL(B20, GPIE0IN, GPIE0, GPIE); +PIN_DECL_2(B20, GPIOE0, NCTS3, GPIE0IN); FUNC_GROUP_DECL(NCTS3, B20); #define C20 33 -SIG_EXPR_LIST_DECL_SINGLE(NDCD3, NDCD3, SIG_DESC_SET(SCU80, 17)); -SIG_EXPR_DECL(GPIE0OUT, GPIE0, GPIE0_DESC); -SIG_EXPR_DECL(GPIE0OUT, GPIE, GPIE_DESC); -SIG_EXPR_LIST_DECL_DUAL(GPIE0OUT, GPIE0, GPIE); -MS_PIN_DECL(C20, GPIOE1, NDCD3, GPIE0OUT); +SIG_EXPR_LIST_DECL_SINGLE(C20, NDCD3, NDCD3, SIG_DESC_SET(SCU80, 17)); +SIG_EXPR_DECL_SINGLE(GPIE0OUT, GPIE0, GPIE0_DESC); +SIG_EXPR_DECL_SINGLE(GPIE0OUT, GPIE, GPIE_DESC); +SIG_EXPR_LIST_DECL_DUAL(C20, GPIE0OUT, GPIE0, GPIE); +PIN_DECL_2(C20, GPIOE1, NDCD3, GPIE0OUT); FUNC_GROUP_DECL(NDCD3, C20); FUNC_GROUP_DECL(GPIE0, B20, C20); @@ -291,20 +298,20 @@ FUNC_GROUP_DECL(GPIE0, B20, C20); #define GPIE2_DESC SIG_DESC_SET(SCU8C, 13) #define F18 34 -SIG_EXPR_LIST_DECL_SINGLE(NDSR3, NDSR3, SIG_DESC_SET(SCU80, 18)); -SIG_EXPR_DECL(GPIE2IN, GPIE2, GPIE2_DESC); -SIG_EXPR_DECL(GPIE2IN, GPIE, GPIE_DESC); -SIG_EXPR_LIST_DECL_DUAL(GPIE2IN, GPIE2, GPIE); -MS_PIN_DECL(F18, GPIOE2, NDSR3, GPIE2IN); +SIG_EXPR_LIST_DECL_SINGLE(F18, NDSR3, NDSR3, SIG_DESC_SET(SCU80, 18)); +SIG_EXPR_DECL_SINGLE(GPIE2IN, GPIE2, GPIE2_DESC); +SIG_EXPR_DECL_SINGLE(GPIE2IN, GPIE, GPIE_DESC); +SIG_EXPR_LIST_DECL_DUAL(F18, GPIE2IN, GPIE2, GPIE); +PIN_DECL_2(F18, GPIOE2, NDSR3, GPIE2IN); FUNC_GROUP_DECL(NDSR3, F18); #define F17 35 -SIG_EXPR_LIST_DECL_SINGLE(NRI3, NRI3, SIG_DESC_SET(SCU80, 19)); -SIG_EXPR_DECL(GPIE2OUT, GPIE2, GPIE2_DESC); -SIG_EXPR_DECL(GPIE2OUT, GPIE, GPIE_DESC); -SIG_EXPR_LIST_DECL_DUAL(GPIE2OUT, GPIE2, GPIE); -MS_PIN_DECL(F17, GPIOE3, NRI3, GPIE2OUT); +SIG_EXPR_LIST_DECL_SINGLE(F17, NRI3, NRI3, SIG_DESC_SET(SCU80, 19)); +SIG_EXPR_DECL_SINGLE(GPIE2OUT, GPIE2, GPIE2_DESC); +SIG_EXPR_DECL_SINGLE(GPIE2OUT, GPIE, GPIE_DESC); +SIG_EXPR_LIST_DECL_DUAL(F17, GPIE2OUT, GPIE2, GPIE); +PIN_DECL_2(F17, GPIOE3, NRI3, GPIE2OUT); FUNC_GROUP_DECL(NRI3, F17); FUNC_GROUP_DECL(GPIE2, F18, F17); @@ -312,19 +319,19 @@ FUNC_GROUP_DECL(GPIE2, F18, F17); #define GPIE4_DESC SIG_DESC_SET(SCU8C, 14) #define E18 36 -SIG_EXPR_LIST_DECL_SINGLE(NDTR3, NDTR3, SIG_DESC_SET(SCU80, 20)); -SIG_EXPR_DECL(GPIE4IN, GPIE4, GPIE4_DESC); -SIG_EXPR_DECL(GPIE4IN, GPIE, GPIE_DESC); -SIG_EXPR_LIST_DECL_DUAL(GPIE4IN, GPIE4, GPIE); -MS_PIN_DECL(E18, GPIOE4, NDTR3, GPIE4IN); +SIG_EXPR_LIST_DECL_SINGLE(E18, NDTR3, NDTR3, SIG_DESC_SET(SCU80, 20)); +SIG_EXPR_DECL_SINGLE(GPIE4IN, GPIE4, GPIE4_DESC); +SIG_EXPR_DECL_SINGLE(GPIE4IN, GPIE, GPIE_DESC); +SIG_EXPR_LIST_DECL_DUAL(E18, GPIE4IN, GPIE4, GPIE); +PIN_DECL_2(E18, GPIOE4, NDTR3, GPIE4IN); FUNC_GROUP_DECL(NDTR3, E18); #define D19 37 -SIG_EXPR_LIST_DECL_SINGLE(NRTS3, NRTS3, SIG_DESC_SET(SCU80, 21)); -SIG_EXPR_DECL(GPIE4OUT, GPIE4, GPIE4_DESC); -SIG_EXPR_DECL(GPIE4OUT, GPIE, GPIE_DESC); -SIG_EXPR_LIST_DECL_DUAL(GPIE4OUT, GPIE4, GPIE); -MS_PIN_DECL(D19, GPIOE5, NRTS3, GPIE4OUT); +SIG_EXPR_LIST_DECL_SINGLE(D19, NRTS3, NRTS3, SIG_DESC_SET(SCU80, 21)); +SIG_EXPR_DECL_SINGLE(GPIE4OUT, GPIE4, GPIE4_DESC); +SIG_EXPR_DECL_SINGLE(GPIE4OUT, GPIE, GPIE_DESC); +SIG_EXPR_LIST_DECL_DUAL(D19, GPIE4OUT, GPIE4, GPIE); +PIN_DECL_2(D19, GPIOE5, NRTS3, GPIE4OUT); FUNC_GROUP_DECL(NRTS3, D19); FUNC_GROUP_DECL(GPIE4, E18, D19); @@ -332,19 +339,19 @@ FUNC_GROUP_DECL(GPIE4, E18, D19); #define GPIE6_DESC SIG_DESC_SET(SCU8C, 15) #define A20 38 -SIG_EXPR_LIST_DECL_SINGLE(TXD3, TXD3, SIG_DESC_SET(SCU80, 22)); -SIG_EXPR_DECL(GPIE6IN, GPIE6, GPIE6_DESC); -SIG_EXPR_DECL(GPIE6IN, GPIE, GPIE_DESC); -SIG_EXPR_LIST_DECL_DUAL(GPIE6IN, GPIE6, GPIE); -MS_PIN_DECL(A20, GPIOE6, TXD3, GPIE6IN); +SIG_EXPR_LIST_DECL_SINGLE(A20, TXD3, TXD3, SIG_DESC_SET(SCU80, 22)); +SIG_EXPR_DECL_SINGLE(GPIE6IN, GPIE6, GPIE6_DESC); +SIG_EXPR_DECL_SINGLE(GPIE6IN, GPIE, GPIE_DESC); +SIG_EXPR_LIST_DECL_DUAL(A20, GPIE6IN, GPIE6, GPIE); +PIN_DECL_2(A20, GPIOE6, TXD3, GPIE6IN); FUNC_GROUP_DECL(TXD3, A20); #define B19 39 -SIG_EXPR_LIST_DECL_SINGLE(RXD3, RXD3, SIG_DESC_SET(SCU80, 23)); -SIG_EXPR_DECL(GPIE6OUT, GPIE6, GPIE6_DESC); -SIG_EXPR_DECL(GPIE6OUT, GPIE, GPIE_DESC); -SIG_EXPR_LIST_DECL_DUAL(GPIE6OUT, GPIE6, GPIE); -MS_PIN_DECL(B19, GPIOE7, RXD3, GPIE6OUT); +SIG_EXPR_LIST_DECL_SINGLE(B19, RXD3, RXD3, SIG_DESC_SET(SCU80, 23)); +SIG_EXPR_DECL_SINGLE(GPIE6OUT, GPIE6, GPIE6_DESC); +SIG_EXPR_DECL_SINGLE(GPIE6OUT, GPIE, GPIE_DESC); +SIG_EXPR_LIST_DECL_DUAL(B19, GPIE6OUT, GPIE6, GPIE); +PIN_DECL_2(B19, GPIOE7, RXD3, GPIE6OUT); FUNC_GROUP_DECL(RXD3, B19); FUNC_GROUP_DECL(GPIE6, A20, B19); @@ -353,112 +360,112 @@ FUNC_GROUP_DECL(GPIE6, A20, B19); #define LPCPLUS_DESC SIG_DESC_SET(SCU90, 30) #define J19 40 -SIG_EXPR_DECL(LHAD0, LPCHC, LPCHC_DESC); -SIG_EXPR_DECL(LHAD0, LPCPLUS, LPCPLUS_DESC); -SIG_EXPR_LIST_DECL_DUAL(LHAD0, LPCHC, LPCPLUS); -SIG_EXPR_LIST_DECL_SINGLE(NCTS4, NCTS4, SIG_DESC_SET(SCU80, 24)); -MS_PIN_DECL(J19, GPIOF0, LHAD0, NCTS4); +SIG_EXPR_DECL_SINGLE(LHAD0, LPCHC, LPCHC_DESC); +SIG_EXPR_DECL_SINGLE(LHAD0, LPCPLUS, LPCPLUS_DESC); +SIG_EXPR_LIST_DECL_DUAL(J19, LHAD0, LPCHC, LPCPLUS); +SIG_EXPR_LIST_DECL_SINGLE(J19, NCTS4, NCTS4, SIG_DESC_SET(SCU80, 24)); +PIN_DECL_2(J19, GPIOF0, LHAD0, NCTS4); FUNC_GROUP_DECL(NCTS4, J19); #define J18 41 -SIG_EXPR_DECL(LHAD1, LPCHC, LPCHC_DESC); -SIG_EXPR_DECL(LHAD1, LPCPLUS, LPCPLUS_DESC); -SIG_EXPR_LIST_DECL_DUAL(LHAD1, LPCHC, LPCPLUS); -SIG_EXPR_LIST_DECL_SINGLE(NDCD4, NDCD4, SIG_DESC_SET(SCU80, 25)); -MS_PIN_DECL(J18, GPIOF1, LHAD1, NDCD4); +SIG_EXPR_DECL_SINGLE(LHAD1, LPCHC, LPCHC_DESC); +SIG_EXPR_DECL_SINGLE(LHAD1, LPCPLUS, LPCPLUS_DESC); +SIG_EXPR_LIST_DECL_DUAL(J18, LHAD1, LPCHC, LPCPLUS); +SIG_EXPR_LIST_DECL_SINGLE(J18, NDCD4, NDCD4, SIG_DESC_SET(SCU80, 25)); +PIN_DECL_2(J18, GPIOF1, LHAD1, NDCD4); FUNC_GROUP_DECL(NDCD4, J18); #define B22 42 -SIG_EXPR_DECL(LHAD2, LPCHC, LPCHC_DESC); -SIG_EXPR_DECL(LHAD2, LPCPLUS, LPCPLUS_DESC); -SIG_EXPR_LIST_DECL_DUAL(LHAD2, LPCHC, LPCPLUS); -SIG_EXPR_LIST_DECL_SINGLE(NDSR4, NDSR4, SIG_DESC_SET(SCU80, 26)); -MS_PIN_DECL(B22, GPIOF2, LHAD2, NDSR4); +SIG_EXPR_DECL_SINGLE(LHAD2, LPCHC, LPCHC_DESC); +SIG_EXPR_DECL_SINGLE(LHAD2, LPCPLUS, LPCPLUS_DESC); +SIG_EXPR_LIST_DECL_DUAL(B22, LHAD2, LPCHC, LPCPLUS); +SIG_EXPR_LIST_DECL_SINGLE(B22, NDSR4, NDSR4, SIG_DESC_SET(SCU80, 26)); +PIN_DECL_2(B22, GPIOF2, LHAD2, NDSR4); FUNC_GROUP_DECL(NDSR4, B22); #define B21 43 -SIG_EXPR_DECL(LHAD3, LPCHC, LPCHC_DESC); -SIG_EXPR_DECL(LHAD3, LPCPLUS, LPCPLUS_DESC); -SIG_EXPR_LIST_DECL_DUAL(LHAD3, LPCHC, LPCPLUS); -SIG_EXPR_LIST_DECL_SINGLE(NRI4, NRI4, SIG_DESC_SET(SCU80, 27)); -MS_PIN_DECL(B21, GPIOF3, LHAD3, NRI4); +SIG_EXPR_DECL_SINGLE(LHAD3, LPCHC, LPCHC_DESC); +SIG_EXPR_DECL_SINGLE(LHAD3, LPCPLUS, LPCPLUS_DESC); +SIG_EXPR_LIST_DECL_DUAL(B21, LHAD3, LPCHC, LPCPLUS); +SIG_EXPR_LIST_DECL_SINGLE(B21, NRI4, NRI4, SIG_DESC_SET(SCU80, 27)); +PIN_DECL_2(B21, GPIOF3, LHAD3, NRI4); FUNC_GROUP_DECL(NRI4, B21); #define A21 44 -SIG_EXPR_DECL(LHCLK, LPCHC, LPCHC_DESC); -SIG_EXPR_DECL(LHCLK, LPCPLUS, LPCPLUS_DESC); -SIG_EXPR_LIST_DECL_DUAL(LHCLK, LPCHC, LPCPLUS); -SIG_EXPR_LIST_DECL_SINGLE(NDTR4, NDTR4, SIG_DESC_SET(SCU80, 28)); -MS_PIN_DECL(A21, GPIOF4, LHCLK, NDTR4); +SIG_EXPR_DECL_SINGLE(LHCLK, LPCHC, LPCHC_DESC); +SIG_EXPR_DECL_SINGLE(LHCLK, LPCPLUS, LPCPLUS_DESC); +SIG_EXPR_LIST_DECL_DUAL(A21, LHCLK, LPCHC, LPCPLUS); +SIG_EXPR_LIST_DECL_SINGLE(A21, NDTR4, NDTR4, SIG_DESC_SET(SCU80, 28)); +PIN_DECL_2(A21, GPIOF4, LHCLK, NDTR4); FUNC_GROUP_DECL(NDTR4, A21); #define H19 45 -SIG_EXPR_DECL(LHFRAME, LPCHC, LPCHC_DESC); -SIG_EXPR_DECL(LHFRAME, LPCPLUS, LPCPLUS_DESC); -SIG_EXPR_LIST_DECL_DUAL(LHFRAME, LPCHC, LPCPLUS); -SIG_EXPR_LIST_DECL_SINGLE(NRTS4, NRTS4, SIG_DESC_SET(SCU80, 29)); -MS_PIN_DECL(H19, GPIOF5, LHFRAME, NRTS4); +SIG_EXPR_DECL_SINGLE(LHFRAME, LPCHC, LPCHC_DESC); +SIG_EXPR_DECL_SINGLE(LHFRAME, LPCPLUS, LPCPLUS_DESC); +SIG_EXPR_LIST_DECL_DUAL(H19, LHFRAME, LPCHC, LPCPLUS); +SIG_EXPR_LIST_DECL_SINGLE(H19, NRTS4, NRTS4, SIG_DESC_SET(SCU80, 29)); +PIN_DECL_2(H19, GPIOF5, LHFRAME, NRTS4); FUNC_GROUP_DECL(NRTS4, H19); #define G17 46 -SIG_EXPR_LIST_DECL_SINGLE(LHSIRQ, LPCHC, LPCHC_DESC); -SIG_EXPR_LIST_DECL_SINGLE(TXD4, TXD4, SIG_DESC_SET(SCU80, 30)); -MS_PIN_DECL(G17, GPIOF6, LHSIRQ, TXD4); +SIG_EXPR_LIST_DECL_SINGLE(G17, LHSIRQ, LPCHC, LPCHC_DESC); +SIG_EXPR_LIST_DECL_SINGLE(G17, TXD4, TXD4, SIG_DESC_SET(SCU80, 30)); +PIN_DECL_2(G17, GPIOF6, LHSIRQ, TXD4); FUNC_GROUP_DECL(TXD4, G17); #define H18 47 -SIG_EXPR_DECL(LHRST, LPCHC, LPCHC_DESC); -SIG_EXPR_DECL(LHRST, LPCPLUS, LPCPLUS_DESC); -SIG_EXPR_LIST_DECL_DUAL(LHRST, LPCHC, LPCPLUS); -SIG_EXPR_LIST_DECL_SINGLE(RXD4, RXD4, SIG_DESC_SET(SCU80, 31)); -MS_PIN_DECL(H18, GPIOF7, LHRST, RXD4); +SIG_EXPR_DECL_SINGLE(LHRST, LPCHC, LPCHC_DESC); +SIG_EXPR_DECL_SINGLE(LHRST, LPCPLUS, LPCPLUS_DESC); +SIG_EXPR_LIST_DECL_DUAL(H18, LHRST, LPCHC, LPCPLUS); +SIG_EXPR_LIST_DECL_SINGLE(H18, RXD4, RXD4, SIG_DESC_SET(SCU80, 31)); +PIN_DECL_2(H18, GPIOF7, LHRST, RXD4); FUNC_GROUP_DECL(RXD4, H18); FUNC_GROUP_DECL(LPCHC, J19, J18, B22, B21, A21, H19, G17, H18); FUNC_GROUP_DECL(LPCPLUS, J19, J18, B22, B21, A21, H19, H18); #define A19 48 -SIG_EXPR_LIST_DECL_SINGLE(SGPS1CK, SGPS1, COND1, SIG_DESC_SET(SCU84, 0)); -SS_PIN_DECL(A19, GPIOG0, SGPS1CK); +SIG_EXPR_LIST_DECL_SINGLE(A19, SGPS1CK, SGPS1, COND1, SIG_DESC_SET(SCU84, 0)); +PIN_DECL_1(A19, GPIOG0, SGPS1CK); #define E19 49 -SIG_EXPR_LIST_DECL_SINGLE(SGPS1LD, SGPS1, COND1, SIG_DESC_SET(SCU84, 1)); -SS_PIN_DECL(E19, GPIOG1, SGPS1LD); +SIG_EXPR_LIST_DECL_SINGLE(E19, SGPS1LD, SGPS1, COND1, SIG_DESC_SET(SCU84, 1)); +PIN_DECL_1(E19, GPIOG1, SGPS1LD); #define C19 50 -SIG_EXPR_LIST_DECL_SINGLE(SGPS1I0, SGPS1, COND1, SIG_DESC_SET(SCU84, 2)); -SS_PIN_DECL(C19, GPIOG2, SGPS1I0); +SIG_EXPR_LIST_DECL_SINGLE(C19, SGPS1I0, SGPS1, COND1, SIG_DESC_SET(SCU84, 2)); +PIN_DECL_1(C19, GPIOG2, SGPS1I0); #define E16 51 -SIG_EXPR_LIST_DECL_SINGLE(SGPS1I1, SGPS1, COND1, SIG_DESC_SET(SCU84, 3)); -SS_PIN_DECL(E16, GPIOG3, SGPS1I1); +SIG_EXPR_LIST_DECL_SINGLE(E16, SGPS1I1, SGPS1, COND1, SIG_DESC_SET(SCU84, 3)); +PIN_DECL_1(E16, GPIOG3, SGPS1I1); FUNC_GROUP_DECL(SGPS1, A19, E19, C19, E16); #define SGPS2_DESC SIG_DESC_SET(SCU94, 12) #define E17 52 -SIG_EXPR_LIST_DECL_SINGLE(SGPS2CK, SGPS2, COND1, SGPS2_DESC); -SIG_EXPR_LIST_DECL_SINGLE(SALT1, SALT1, COND1, SIG_DESC_SET(SCU84, 4)); -MS_PIN_DECL(E17, GPIOG4, SGPS2CK, SALT1); +SIG_EXPR_LIST_DECL_SINGLE(E17, SGPS2CK, SGPS2, COND1, SGPS2_DESC); +SIG_EXPR_LIST_DECL_SINGLE(E17, SALT1, SALT1, COND1, SIG_DESC_SET(SCU84, 4)); +PIN_DECL_2(E17, GPIOG4, SGPS2CK, SALT1); FUNC_GROUP_DECL(SALT1, E17); #define D16 53 -SIG_EXPR_LIST_DECL_SINGLE(SGPS2LD, SGPS2, COND1, SGPS2_DESC); -SIG_EXPR_LIST_DECL_SINGLE(SALT2, SALT2, COND1, SIG_DESC_SET(SCU84, 5)); -MS_PIN_DECL(D16, GPIOG5, SGPS2LD, SALT2); +SIG_EXPR_LIST_DECL_SINGLE(D16, SGPS2LD, SGPS2, COND1, SGPS2_DESC); +SIG_EXPR_LIST_DECL_SINGLE(D16, SALT2, SALT2, COND1, SIG_DESC_SET(SCU84, 5)); +PIN_DECL_2(D16, GPIOG5, SGPS2LD, SALT2); FUNC_GROUP_DECL(SALT2, D16); #define D15 54 -SIG_EXPR_LIST_DECL_SINGLE(SGPS2I0, SGPS2, COND1, SGPS2_DESC); -SIG_EXPR_LIST_DECL_SINGLE(SALT3, SALT3, COND1, SIG_DESC_SET(SCU84, 6)); -MS_PIN_DECL(D15, GPIOG6, SGPS2I0, SALT3); +SIG_EXPR_LIST_DECL_SINGLE(D15, SGPS2I0, SGPS2, COND1, SGPS2_DESC); +SIG_EXPR_LIST_DECL_SINGLE(D15, SALT3, SALT3, COND1, SIG_DESC_SET(SCU84, 6)); +PIN_DECL_2(D15, GPIOG6, SGPS2I0, SALT3); FUNC_GROUP_DECL(SALT3, D15); #define E14 55 -SIG_EXPR_LIST_DECL_SINGLE(SGPS2I1, SGPS2, COND1, SGPS2_DESC); -SIG_EXPR_LIST_DECL_SINGLE(SALT4, SALT4, COND1, SIG_DESC_SET(SCU84, 7)); -MS_PIN_DECL(E14, GPIOG7, SGPS2I1, SALT4); +SIG_EXPR_LIST_DECL_SINGLE(E14, SGPS2I1, SGPS2, COND1, SGPS2_DESC); +SIG_EXPR_LIST_DECL_SINGLE(E14, SALT4, SALT4, COND1, SIG_DESC_SET(SCU84, 7)); +PIN_DECL_2(E14, GPIOG7, SGPS2I1, SALT4); FUNC_GROUP_DECL(SALT4, E14); FUNC_GROUP_DECL(SGPS2, E17, D16, D15, E14); @@ -466,42 +473,42 @@ FUNC_GROUP_DECL(SGPS2, E17, D16, D15, E14); #define UART6_DESC SIG_DESC_SET(SCU90, 7) #define A18 56 -SIG_EXPR_LIST_DECL_SINGLE(DASHA18, DASHA18, COND1, SIG_DESC_SET(SCU94, 5)); -SIG_EXPR_LIST_DECL_SINGLE(NCTS6, UART6, COND1, UART6_DESC); -MS_PIN_DECL(A18, GPIOH0, DASHA18, NCTS6); +SIG_EXPR_LIST_DECL_SINGLE(A18, DASHA18, DASHA18, COND1, SIG_DESC_SET(SCU94, 5)); +SIG_EXPR_LIST_DECL_SINGLE(A18, NCTS6, UART6, COND1, UART6_DESC); +PIN_DECL_2(A18, GPIOH0, DASHA18, NCTS6); #define B18 57 -SIG_EXPR_LIST_DECL_SINGLE(DASHB18, DASHB18, COND1, SIG_DESC_SET(SCU94, 5)); -SIG_EXPR_LIST_DECL_SINGLE(NDCD6, UART6, COND1, UART6_DESC); -MS_PIN_DECL(B18, GPIOH1, DASHB18, NDCD6); +SIG_EXPR_LIST_DECL_SINGLE(B18, DASHB18, DASHB18, COND1, SIG_DESC_SET(SCU94, 5)); +SIG_EXPR_LIST_DECL_SINGLE(B18, NDCD6, UART6, COND1, UART6_DESC); +PIN_DECL_2(B18, GPIOH1, DASHB18, NDCD6); #define D17 58 -SIG_EXPR_LIST_DECL_SINGLE(DASHD17, DASHD17, COND1, SIG_DESC_SET(SCU94, 6)); -SIG_EXPR_LIST_DECL_SINGLE(NDSR6, UART6, COND1, UART6_DESC); -MS_PIN_DECL(D17, GPIOH2, DASHD17, NDSR6); +SIG_EXPR_LIST_DECL_SINGLE(D17, DASHD17, DASHD17, COND1, SIG_DESC_SET(SCU94, 6)); +SIG_EXPR_LIST_DECL_SINGLE(D17, NDSR6, UART6, COND1, UART6_DESC); +PIN_DECL_2(D17, GPIOH2, DASHD17, NDSR6); #define C17 59 -SIG_EXPR_LIST_DECL_SINGLE(DASHC17, DASHC17, COND1, SIG_DESC_SET(SCU94, 6)); -SIG_EXPR_LIST_DECL_SINGLE(NRI6, UART6, COND1, UART6_DESC); -MS_PIN_DECL(C17, GPIOH3, DASHC17, NRI6); +SIG_EXPR_LIST_DECL_SINGLE(C17, DASHC17, DASHC17, COND1, SIG_DESC_SET(SCU94, 6)); +SIG_EXPR_LIST_DECL_SINGLE(C17, NRI6, UART6, COND1, UART6_DESC); +PIN_DECL_2(C17, GPIOH3, DASHC17, NRI6); #define A17 60 -SIG_EXPR_LIST_DECL_SINGLE(DASHA17, DASHA17, COND1, SIG_DESC_SET(SCU94, 7)); -SIG_EXPR_LIST_DECL_SINGLE(NDTR6, UART6, COND1, UART6_DESC); -MS_PIN_DECL(A17, GPIOH4, DASHA17, NDTR6); +SIG_EXPR_LIST_DECL_SINGLE(A17, DASHA17, DASHA17, COND1, SIG_DESC_SET(SCU94, 7)); +SIG_EXPR_LIST_DECL_SINGLE(A17, NDTR6, UART6, COND1, UART6_DESC); +PIN_DECL_2(A17, GPIOH4, DASHA17, NDTR6); #define B17 61 -SIG_EXPR_LIST_DECL_SINGLE(DASHB17, DASHB17, COND1, SIG_DESC_SET(SCU94, 7)); -SIG_EXPR_LIST_DECL_SINGLE(NRTS6, UART6, COND1, UART6_DESC); -MS_PIN_DECL(B17, GPIOH5, DASHB17, NRTS6); +SIG_EXPR_LIST_DECL_SINGLE(B17, DASHB17, DASHB17, COND1, SIG_DESC_SET(SCU94, 7)); +SIG_EXPR_LIST_DECL_SINGLE(B17, NRTS6, UART6, COND1, UART6_DESC); +PIN_DECL_2(B17, GPIOH5, DASHB17, NRTS6); #define A16 62 -SIG_EXPR_LIST_DECL_SINGLE(TXD6, UART6, COND1, UART6_DESC); -SS_PIN_DECL(A16, GPIOH6, TXD6); +SIG_EXPR_LIST_DECL_SINGLE(A16, TXD6, UART6, COND1, UART6_DESC); +PIN_DECL_1(A16, GPIOH6, TXD6); #define D18 63 -SIG_EXPR_LIST_DECL_SINGLE(RXD6, UART6, COND1, UART6_DESC); -SS_PIN_DECL(D18, GPIOH7, RXD6); +SIG_EXPR_LIST_DECL_SINGLE(D18, RXD6, UART6, COND1, UART6_DESC); +PIN_DECL_1(D18, GPIOH7, RXD6); FUNC_GROUP_DECL(UART6, A18, B18, D17, C17, A17, B17, A16, D18); @@ -513,70 +520,78 @@ FUNC_GROUP_DECL(UART6, A18, B18, D17, C17, A17, B17, A16, D18); { ASPEED_IP_SCU, HW_STRAP1, GENMASK(13, 12), 3, 0 } #define C18 64 -SIG_EXPR_DECL(SYSCS, SPI1DEBUG, COND1, SPI1DEBUG_DESC); -SIG_EXPR_DECL(SYSCS, SPI1PASSTHRU, COND1, SPI1PASSTHRU_DESC); -SIG_EXPR_LIST_DECL_DUAL(SYSCS, SPI1DEBUG, SPI1PASSTHRU); -SS_PIN_DECL(C18, GPIOI0, SYSCS); +SIG_EXPR_DECL_SINGLE(SYSCS, SPI1DEBUG, COND1, SPI1DEBUG_DESC); +SIG_EXPR_DECL_SINGLE(SYSCS, SPI1PASSTHRU, COND1, SPI1PASSTHRU_DESC); +SIG_EXPR_LIST_DECL_DUAL(C18, SYSCS, SPI1DEBUG, SPI1PASSTHRU); +PIN_DECL_1(C18, GPIOI0, SYSCS); #define E15 65 -SIG_EXPR_DECL(SYSCK, SPI1DEBUG, COND1, SPI1DEBUG_DESC); -SIG_EXPR_DECL(SYSCK, SPI1PASSTHRU, COND1, SPI1PASSTHRU_DESC); -SIG_EXPR_LIST_DECL_DUAL(SYSCK, SPI1DEBUG, SPI1PASSTHRU); -SS_PIN_DECL(E15, GPIOI1, SYSCK); +SIG_EXPR_DECL_SINGLE(SYSCK, SPI1DEBUG, COND1, SPI1DEBUG_DESC); +SIG_EXPR_DECL_SINGLE(SYSCK, SPI1PASSTHRU, COND1, SPI1PASSTHRU_DESC); +SIG_EXPR_LIST_DECL_DUAL(E15, SYSCK, SPI1DEBUG, SPI1PASSTHRU); +PIN_DECL_1(E15, GPIOI1, SYSCK); #define B16 66 -SIG_EXPR_DECL(SYSMOSI, SPI1DEBUG, COND1, SPI1DEBUG_DESC); -SIG_EXPR_DECL(SYSMOSI, SPI1PASSTHRU, COND1, SPI1PASSTHRU_DESC); -SIG_EXPR_LIST_DECL_DUAL(SYSMOSI, SPI1DEBUG, SPI1PASSTHRU); -SS_PIN_DECL(B16, GPIOI2, SYSMOSI); +SIG_EXPR_DECL_SINGLE(SYSMOSI, SPI1DEBUG, COND1, SPI1DEBUG_DESC); +SIG_EXPR_DECL_SINGLE(SYSMOSI, SPI1PASSTHRU, COND1, SPI1PASSTHRU_DESC); +SIG_EXPR_LIST_DECL_DUAL(B16, SYSMOSI, SPI1DEBUG, SPI1PASSTHRU); +PIN_DECL_1(B16, GPIOI2, SYSMOSI); #define C16 67 -SIG_EXPR_DECL(SYSMISO, SPI1DEBUG, COND1, SPI1DEBUG_DESC); -SIG_EXPR_DECL(SYSMISO, SPI1PASSTHRU, COND1, SPI1PASSTHRU_DESC); -SIG_EXPR_LIST_DECL_DUAL(SYSMISO, SPI1DEBUG, SPI1PASSTHRU); -SS_PIN_DECL(C16, GPIOI3, SYSMISO); +SIG_EXPR_DECL_SINGLE(SYSMISO, SPI1DEBUG, COND1, SPI1DEBUG_DESC); +SIG_EXPR_DECL_SINGLE(SYSMISO, SPI1PASSTHRU, COND1, SPI1PASSTHRU_DESC); +SIG_EXPR_LIST_DECL_DUAL(C16, SYSMISO, SPI1DEBUG, SPI1PASSTHRU); +PIN_DECL_1(C16, GPIOI3, SYSMISO); #define VB_DESC SIG_DESC_SET(HW_STRAP1, 5) #define B15 68 -SIG_EXPR_DECL(SPI1CS0, SPI1, COND1, SPI1_DESC); -SIG_EXPR_DECL(SPI1CS0, SPI1DEBUG, COND1, SPI1DEBUG_DESC); -SIG_EXPR_DECL(SPI1CS0, SPI1PASSTHRU, COND1, SPI1PASSTHRU_DESC); -SIG_EXPR_LIST_DECL(SPI1CS0, SIG_EXPR_PTR(SPI1CS0, SPI1), +SIG_EXPR_DECL_SINGLE(SPI1CS0, SPI1, COND1, SPI1_DESC); +SIG_EXPR_DECL_SINGLE(SPI1CS0, SPI1DEBUG, COND1, SPI1DEBUG_DESC); +SIG_EXPR_DECL_SINGLE(SPI1CS0, SPI1PASSTHRU, COND1, SPI1PASSTHRU_DESC); +SIG_EXPR_LIST_DECL(SPI1CS0, SPI1, + SIG_EXPR_PTR(SPI1CS0, SPI1), SIG_EXPR_PTR(SPI1CS0, SPI1DEBUG), SIG_EXPR_PTR(SPI1CS0, SPI1PASSTHRU)); -SIG_EXPR_LIST_DECL_SINGLE(VBCS, VGABIOSROM, COND1, VB_DESC); -MS_PIN_DECL(B15, GPIOI4, SPI1CS0, VBCS); +SIG_EXPR_LIST_ALIAS(B15, SPI1CS0, SPI1); +SIG_EXPR_LIST_DECL_SINGLE(B15, VBCS, VGABIOSROM, COND1, VB_DESC); +PIN_DECL_2(B15, GPIOI4, SPI1CS0, VBCS); #define C15 69 -SIG_EXPR_DECL(SPI1CK, SPI1, COND1, SPI1_DESC); -SIG_EXPR_DECL(SPI1CK, SPI1DEBUG, COND1, SPI1DEBUG_DESC); -SIG_EXPR_DECL(SPI1CK, SPI1PASSTHRU, COND1, SPI1PASSTHRU_DESC); -SIG_EXPR_LIST_DECL(SPI1CK, SIG_EXPR_PTR(SPI1CK, SPI1), +SIG_EXPR_DECL_SINGLE(SPI1CK, SPI1, COND1, SPI1_DESC); +SIG_EXPR_DECL_SINGLE(SPI1CK, SPI1DEBUG, COND1, SPI1DEBUG_DESC); +SIG_EXPR_DECL_SINGLE(SPI1CK, SPI1PASSTHRU, COND1, SPI1PASSTHRU_DESC); +SIG_EXPR_LIST_DECL(SPI1CK, SPI1, + SIG_EXPR_PTR(SPI1CK, SPI1), SIG_EXPR_PTR(SPI1CK, SPI1DEBUG), SIG_EXPR_PTR(SPI1CK, SPI1PASSTHRU)); -SIG_EXPR_LIST_DECL_SINGLE(VBCK, VGABIOSROM, COND1, VB_DESC); -MS_PIN_DECL(C15, GPIOI5, SPI1CK, VBCK); +SIG_EXPR_LIST_ALIAS(C15, SPI1CK, SPI1); +SIG_EXPR_LIST_DECL_SINGLE(C15, VBCK, VGABIOSROM, COND1, VB_DESC); +PIN_DECL_2(C15, GPIOI5, SPI1CK, VBCK); #define A14 70 -SIG_EXPR_DECL(SPI1MOSI, SPI1, COND1, SPI1_DESC); -SIG_EXPR_DECL(SPI1MOSI, SPI1DEBUG, COND1, SPI1DEBUG_DESC); -SIG_EXPR_DECL(SPI1MOSI, SPI1PASSTHRU, COND1, SPI1PASSTHRU_DESC); -SIG_EXPR_LIST_DECL(SPI1MOSI, SIG_EXPR_PTR(SPI1MOSI, SPI1), +SIG_EXPR_DECL_SINGLE(SPI1MOSI, SPI1, COND1, SPI1_DESC); +SIG_EXPR_DECL_SINGLE(SPI1MOSI, SPI1DEBUG, COND1, SPI1DEBUG_DESC); +SIG_EXPR_DECL_SINGLE(SPI1MOSI, SPI1PASSTHRU, COND1, SPI1PASSTHRU_DESC); +SIG_EXPR_LIST_DECL(SPI1MOSI, SPI1, + SIG_EXPR_PTR(SPI1MOSI, SPI1), SIG_EXPR_PTR(SPI1MOSI, SPI1DEBUG), SIG_EXPR_PTR(SPI1MOSI, SPI1PASSTHRU)); -SIG_EXPR_LIST_DECL_SINGLE(VBMOSI, VGABIOSROM, COND1, VB_DESC); -MS_PIN_DECL(A14, GPIOI6, SPI1MOSI, VBMOSI); +SIG_EXPR_LIST_ALIAS(A14, SPI1MOSI, SPI1); +SIG_EXPR_LIST_DECL_SINGLE(A14, VBMOSI, VGABIOSROM, COND1, VB_DESC); +PIN_DECL_2(A14, GPIOI6, SPI1MOSI, VBMOSI); #define A15 71 -SIG_EXPR_DECL(SPI1MISO, SPI1, COND1, SPI1_DESC); -SIG_EXPR_DECL(SPI1MISO, SPI1DEBUG, COND1, SPI1DEBUG_DESC); -SIG_EXPR_DECL(SPI1MISO, SPI1PASSTHRU, COND1, SPI1PASSTHRU_DESC); -SIG_EXPR_LIST_DECL(SPI1MISO, SIG_EXPR_PTR(SPI1MISO, SPI1), +SIG_EXPR_DECL_SINGLE(SPI1MISO, SPI1, COND1, SPI1_DESC); +SIG_EXPR_DECL_SINGLE(SPI1MISO, SPI1DEBUG, COND1, SPI1DEBUG_DESC); +SIG_EXPR_DECL_SINGLE(SPI1MISO, SPI1PASSTHRU, COND1, SPI1PASSTHRU_DESC); +SIG_EXPR_LIST_DECL(SPI1MISO, SPI1, + SIG_EXPR_PTR(SPI1MISO, SPI1), SIG_EXPR_PTR(SPI1MISO, SPI1DEBUG), SIG_EXPR_PTR(SPI1MISO, SPI1PASSTHRU)); -SIG_EXPR_LIST_DECL_SINGLE(VBMISO, VGABIOSROM, COND1, VB_DESC); -MS_PIN_DECL(A15, GPIOI7, SPI1MISO, VBMISO); +SIG_EXPR_LIST_ALIAS(A15, SPI1MISO, SPI1); +SIG_EXPR_LIST_DECL_SINGLE(A15, VBMISO, VGABIOSROM, COND1, VB_DESC); +PIN_DECL_2(A15, GPIOI7, SPI1MISO, VBMISO); FUNC_GROUP_DECL(SPI1, B15, C15, A14, A15); FUNC_GROUP_DECL(SPI1DEBUG, C18, E15, B16, C16, B15, C15, A14, A15); @@ -584,92 +599,92 @@ FUNC_GROUP_DECL(SPI1PASSTHRU, C18, E15, B16, C16, B15, C15, A14, A15); FUNC_GROUP_DECL(VGABIOSROM, B15, C15, A14, A15); #define R2 72 -SIG_EXPR_LIST_DECL_SINGLE(SGPMCK, SGPM, SIG_DESC_SET(SCU84, 8)); -SS_PIN_DECL(R2, GPIOJ0, SGPMCK); +SIG_EXPR_LIST_DECL_SINGLE(R2, SGPMCK, SGPM, SIG_DESC_SET(SCU84, 8)); +PIN_DECL_1(R2, GPIOJ0, SGPMCK); #define L2 73 -SIG_EXPR_LIST_DECL_SINGLE(SGPMLD, SGPM, SIG_DESC_SET(SCU84, 9)); -SS_PIN_DECL(L2, GPIOJ1, SGPMLD); +SIG_EXPR_LIST_DECL_SINGLE(L2, SGPMLD, SGPM, SIG_DESC_SET(SCU84, 9)); +PIN_DECL_1(L2, GPIOJ1, SGPMLD); #define N3 74 -SIG_EXPR_LIST_DECL_SINGLE(SGPMO, SGPM, SIG_DESC_SET(SCU84, 10)); -SS_PIN_DECL(N3, GPIOJ2, SGPMO); +SIG_EXPR_LIST_DECL_SINGLE(N3, SGPMO, SGPM, SIG_DESC_SET(SCU84, 10)); +PIN_DECL_1(N3, GPIOJ2, SGPMO); #define N4 75 -SIG_EXPR_LIST_DECL_SINGLE(SGPMI, SGPM, SIG_DESC_SET(SCU84, 11)); -SS_PIN_DECL(N4, GPIOJ3, SGPMI); +SIG_EXPR_LIST_DECL_SINGLE(N4, SGPMI, SGPM, SIG_DESC_SET(SCU84, 11)); +PIN_DECL_1(N4, GPIOJ3, SGPMI); FUNC_GROUP_DECL(SGPM, R2, L2, N3, N4); #define N5 76 -SIG_EXPR_LIST_DECL_SINGLE(VGAHS, VGAHS, SIG_DESC_SET(SCU84, 12)); -SIG_EXPR_LIST_DECL_SINGLE(DASHN5, DASHN5, SIG_DESC_SET(SCU94, 8)); -MS_PIN_DECL(N5, GPIOJ4, VGAHS, DASHN5); +SIG_EXPR_LIST_DECL_SINGLE(N5, VGAHS, VGAHS, SIG_DESC_SET(SCU84, 12)); +SIG_EXPR_LIST_DECL_SINGLE(N5, DASHN5, DASHN5, SIG_DESC_SET(SCU94, 8)); +PIN_DECL_2(N5, GPIOJ4, VGAHS, DASHN5); FUNC_GROUP_DECL(VGAHS, N5); #define R4 77 -SIG_EXPR_LIST_DECL_SINGLE(VGAVS, VGAVS, SIG_DESC_SET(SCU84, 13)); -SIG_EXPR_LIST_DECL_SINGLE(DASHR4, DASHR4, SIG_DESC_SET(SCU94, 8)); -MS_PIN_DECL(R4, GPIOJ5, VGAVS, DASHR4); +SIG_EXPR_LIST_DECL_SINGLE(R4, VGAVS, VGAVS, SIG_DESC_SET(SCU84, 13)); +SIG_EXPR_LIST_DECL_SINGLE(R4, DASHR4, DASHR4, SIG_DESC_SET(SCU94, 8)); +PIN_DECL_2(R4, GPIOJ5, VGAVS, DASHR4); FUNC_GROUP_DECL(VGAVS, R4); #define R3 78 -SIG_EXPR_LIST_DECL_SINGLE(DDCCLK, DDCCLK, SIG_DESC_SET(SCU84, 14)); -SIG_EXPR_LIST_DECL_SINGLE(DASHR3, DASHR3, SIG_DESC_SET(SCU94, 9)); -MS_PIN_DECL(R3, GPIOJ6, DDCCLK, DASHR3); +SIG_EXPR_LIST_DECL_SINGLE(R3, DDCCLK, DDCCLK, SIG_DESC_SET(SCU84, 14)); +SIG_EXPR_LIST_DECL_SINGLE(R3, DASHR3, DASHR3, SIG_DESC_SET(SCU94, 9)); +PIN_DECL_2(R3, GPIOJ6, DDCCLK, DASHR3); FUNC_GROUP_DECL(DDCCLK, R3); #define T3 79 -SIG_EXPR_LIST_DECL_SINGLE(DDCDAT, DDCDAT, SIG_DESC_SET(SCU84, 15)); -SIG_EXPR_LIST_DECL_SINGLE(DASHT3, DASHT3, SIG_DESC_SET(SCU94, 9)); -MS_PIN_DECL(T3, GPIOJ7, DDCDAT, DASHT3); +SIG_EXPR_LIST_DECL_SINGLE(T3, DDCDAT, DDCDAT, SIG_DESC_SET(SCU84, 15)); +SIG_EXPR_LIST_DECL_SINGLE(T3, DASHT3, DASHT3, SIG_DESC_SET(SCU94, 9)); +PIN_DECL_2(T3, GPIOJ7, DDCDAT, DASHT3); FUNC_GROUP_DECL(DDCDAT, T3); #define I2C5_DESC SIG_DESC_SET(SCU90, 18) #define L3 80 -SIG_EXPR_LIST_DECL_SINGLE(SCL5, I2C5, I2C5_DESC); -SS_PIN_DECL(L3, GPIOK0, SCL5); +SIG_EXPR_LIST_DECL_SINGLE(L3, SCL5, I2C5, I2C5_DESC); +PIN_DECL_1(L3, GPIOK0, SCL5); #define L4 81 -SIG_EXPR_LIST_DECL_SINGLE(SDA5, I2C5, I2C5_DESC); -SS_PIN_DECL(L4, GPIOK1, SDA5); +SIG_EXPR_LIST_DECL_SINGLE(L4, SDA5, I2C5, I2C5_DESC); +PIN_DECL_1(L4, GPIOK1, SDA5); FUNC_GROUP_DECL(I2C5, L3, L4); #define I2C6_DESC SIG_DESC_SET(SCU90, 19) #define L1 82 -SIG_EXPR_LIST_DECL_SINGLE(SCL6, I2C6, I2C6_DESC); -SS_PIN_DECL(L1, GPIOK2, SCL6); +SIG_EXPR_LIST_DECL_SINGLE(L1, SCL6, I2C6, I2C6_DESC); +PIN_DECL_1(L1, GPIOK2, SCL6); #define N2 83 -SIG_EXPR_LIST_DECL_SINGLE(SDA6, I2C6, I2C6_DESC); -SS_PIN_DECL(N2, GPIOK3, SDA6); +SIG_EXPR_LIST_DECL_SINGLE(N2, SDA6, I2C6, I2C6_DESC); +PIN_DECL_1(N2, GPIOK3, SDA6); FUNC_GROUP_DECL(I2C6, L1, N2); #define I2C7_DESC SIG_DESC_SET(SCU90, 20) #define N1 84 -SIG_EXPR_LIST_DECL_SINGLE(SCL7, I2C7, I2C7_DESC); -SS_PIN_DECL(N1, GPIOK4, SCL7); +SIG_EXPR_LIST_DECL_SINGLE(N1, SCL7, I2C7, I2C7_DESC); +PIN_DECL_1(N1, GPIOK4, SCL7); #define P1 85 -SIG_EXPR_LIST_DECL_SINGLE(SDA7, I2C7, I2C7_DESC); -SS_PIN_DECL(P1, GPIOK5, SDA7); +SIG_EXPR_LIST_DECL_SINGLE(P1, SDA7, I2C7, I2C7_DESC); +PIN_DECL_1(P1, GPIOK5, SDA7); FUNC_GROUP_DECL(I2C7, N1, P1); #define I2C8_DESC SIG_DESC_SET(SCU90, 21) #define P2 86 -SIG_EXPR_LIST_DECL_SINGLE(SCL8, I2C8, I2C8_DESC); -SS_PIN_DECL(P2, GPIOK6, SCL8); +SIG_EXPR_LIST_DECL_SINGLE(P2, SCL8, I2C8, I2C8_DESC); +PIN_DECL_1(P2, GPIOK6, SCL8); #define R1 87 -SIG_EXPR_LIST_DECL_SINGLE(SDA8, I2C8, I2C8_DESC); -SS_PIN_DECL(R1, GPIOK7, SDA8); +SIG_EXPR_LIST_DECL_SINGLE(R1, SDA8, I2C8, I2C8_DESC); +PIN_DECL_1(R1, GPIOK7, SDA8); FUNC_GROUP_DECL(I2C8, P2, R1); @@ -684,290 +699,290 @@ SSSF_PIN_DECL(T2, GPIOL0, NCTS1, SIG_DESC_SET(SCU84, 16)); #define T1 89 #define T1_DESC SIG_DESC_SET(SCU84, 17) -SIG_EXPR_LIST_DECL_SINGLE(VPIDE, VPI24, VPI_24_RSVD_DESC, T1_DESC, COND2); -SIG_EXPR_LIST_DECL_SINGLE(NDCD1, NDCD1, T1_DESC, COND2); -MS_PIN_DECL(T1, GPIOL1, VPIDE, NDCD1); +SIG_EXPR_LIST_DECL_SINGLE(T1, VPIDE, VPI24, VPI_24_RSVD_DESC, T1_DESC, COND2); +SIG_EXPR_LIST_DECL_SINGLE(T1, NDCD1, NDCD1, T1_DESC, COND2); +PIN_DECL_2(T1, GPIOL1, VPIDE, NDCD1); FUNC_GROUP_DECL(NDCD1, T1); #define U1 90 #define U1_DESC SIG_DESC_SET(SCU84, 18) -SIG_EXPR_LIST_DECL_SINGLE(DASHU1, VPI24, VPI_24_RSVD_DESC, U1_DESC); -SIG_EXPR_LIST_DECL_SINGLE(NDSR1, NDSR1, U1_DESC); -MS_PIN_DECL(U1, GPIOL2, DASHU1, NDSR1); +SIG_EXPR_LIST_DECL_SINGLE(U1, DASHU1, VPI24, VPI_24_RSVD_DESC, U1_DESC); +SIG_EXPR_LIST_DECL_SINGLE(U1, NDSR1, NDSR1, U1_DESC); +PIN_DECL_2(U1, GPIOL2, DASHU1, NDSR1); FUNC_GROUP_DECL(NDSR1, U1); #define U2 91 #define U2_DESC SIG_DESC_SET(SCU84, 19) -SIG_EXPR_LIST_DECL_SINGLE(VPIHS, VPI24, VPI_24_RSVD_DESC, U2_DESC, COND2); -SIG_EXPR_LIST_DECL_SINGLE(NRI1, NRI1, U2_DESC, COND2); -MS_PIN_DECL(U2, GPIOL3, VPIHS, NRI1); +SIG_EXPR_LIST_DECL_SINGLE(U2, VPIHS, VPI24, VPI_24_RSVD_DESC, U2_DESC, COND2); +SIG_EXPR_LIST_DECL_SINGLE(U2, NRI1, NRI1, U2_DESC, COND2); +PIN_DECL_2(U2, GPIOL3, VPIHS, NRI1); FUNC_GROUP_DECL(NRI1, U2); #define P4 92 #define P4_DESC SIG_DESC_SET(SCU84, 20) -SIG_EXPR_LIST_DECL_SINGLE(VPIVS, VPI24, VPI_24_RSVD_DESC, P4_DESC, COND2); -SIG_EXPR_LIST_DECL_SINGLE(NDTR1, NDTR1, P4_DESC, COND2); -MS_PIN_DECL(P4, GPIOL4, VPIVS, NDTR1); +SIG_EXPR_LIST_DECL_SINGLE(P4, VPIVS, VPI24, VPI_24_RSVD_DESC, P4_DESC, COND2); +SIG_EXPR_LIST_DECL_SINGLE(P4, NDTR1, NDTR1, P4_DESC, COND2); +PIN_DECL_2(P4, GPIOL4, VPIVS, NDTR1); FUNC_GROUP_DECL(NDTR1, P4); #define P3 93 #define P3_DESC SIG_DESC_SET(SCU84, 21) -SIG_EXPR_LIST_DECL_SINGLE(VPICLK, VPI24, VPI_24_RSVD_DESC, P3_DESC, COND2); -SIG_EXPR_LIST_DECL_SINGLE(NRTS1, NRTS1, P3_DESC, COND2); -MS_PIN_DECL(P3, GPIOL5, VPICLK, NRTS1); +SIG_EXPR_LIST_DECL_SINGLE(P3, VPICLK, VPI24, VPI_24_RSVD_DESC, P3_DESC, COND2); +SIG_EXPR_LIST_DECL_SINGLE(P3, NRTS1, NRTS1, P3_DESC, COND2); +PIN_DECL_2(P3, GPIOL5, VPICLK, NRTS1); FUNC_GROUP_DECL(NRTS1, P3); #define V1 94 #define V1_DESC SIG_DESC_SET(SCU84, 22) -SIG_EXPR_LIST_DECL_SINGLE(DASHV1, DASHV1, VPIRSVD_DESC, V1_DESC); -SIG_EXPR_LIST_DECL_SINGLE(TXD1, TXD1, V1_DESC, COND2); -MS_PIN_DECL(V1, GPIOL6, DASHV1, TXD1); +SIG_EXPR_LIST_DECL_SINGLE(V1, DASHV1, DASHV1, VPIRSVD_DESC, V1_DESC); +SIG_EXPR_LIST_DECL_SINGLE(V1, TXD1, TXD1, V1_DESC, COND2); +PIN_DECL_2(V1, GPIOL6, DASHV1, TXD1); FUNC_GROUP_DECL(TXD1, V1); #define W1 95 #define W1_DESC SIG_DESC_SET(SCU84, 23) -SIG_EXPR_LIST_DECL_SINGLE(DASHW1, DASHW1, VPIRSVD_DESC, W1_DESC); -SIG_EXPR_LIST_DECL_SINGLE(RXD1, RXD1, W1_DESC, COND2); -MS_PIN_DECL(W1, GPIOL7, DASHW1, RXD1); +SIG_EXPR_LIST_DECL_SINGLE(W1, DASHW1, DASHW1, VPIRSVD_DESC, W1_DESC); +SIG_EXPR_LIST_DECL_SINGLE(W1, RXD1, RXD1, W1_DESC, COND2); +PIN_DECL_2(W1, GPIOL7, DASHW1, RXD1); FUNC_GROUP_DECL(RXD1, W1); #define Y1 96 #define Y1_DESC SIG_DESC_SET(SCU84, 24) -SIG_EXPR_LIST_DECL_SINGLE(VPIB2, VPI24, VPI_24_RSVD_DESC, Y1_DESC, COND2); -SIG_EXPR_LIST_DECL_SINGLE(NCTS2, NCTS2, Y1_DESC, COND2); -MS_PIN_DECL(Y1, GPIOM0, VPIB2, NCTS2); +SIG_EXPR_LIST_DECL_SINGLE(Y1, VPIB2, VPI24, VPI_24_RSVD_DESC, Y1_DESC, COND2); +SIG_EXPR_LIST_DECL_SINGLE(Y1, NCTS2, NCTS2, Y1_DESC, COND2); +PIN_DECL_2(Y1, GPIOM0, VPIB2, NCTS2); FUNC_GROUP_DECL(NCTS2, Y1); #define AB2 97 #define AB2_DESC SIG_DESC_SET(SCU84, 25) -SIG_EXPR_LIST_DECL_SINGLE(VPIB3, VPI24, VPI_24_RSVD_DESC, AB2_DESC, COND2); -SIG_EXPR_LIST_DECL_SINGLE(NDCD2, NDCD2, AB2_DESC, COND2); -MS_PIN_DECL(AB2, GPIOM1, VPIB3, NDCD2); +SIG_EXPR_LIST_DECL_SINGLE(AB2, VPIB3, VPI24, VPI_24_RSVD_DESC, AB2_DESC, COND2); +SIG_EXPR_LIST_DECL_SINGLE(AB2, NDCD2, NDCD2, AB2_DESC, COND2); +PIN_DECL_2(AB2, GPIOM1, VPIB3, NDCD2); FUNC_GROUP_DECL(NDCD2, AB2); #define AA1 98 #define AA1_DESC SIG_DESC_SET(SCU84, 26) -SIG_EXPR_LIST_DECL_SINGLE(VPIB4, VPI24, VPI_24_RSVD_DESC, AA1_DESC, COND2); -SIG_EXPR_LIST_DECL_SINGLE(NDSR2, NDSR2, AA1_DESC, COND2); -MS_PIN_DECL(AA1, GPIOM2, VPIB4, NDSR2); +SIG_EXPR_LIST_DECL_SINGLE(AA1, VPIB4, VPI24, VPI_24_RSVD_DESC, AA1_DESC, COND2); +SIG_EXPR_LIST_DECL_SINGLE(AA1, NDSR2, NDSR2, AA1_DESC, COND2); +PIN_DECL_2(AA1, GPIOM2, VPIB4, NDSR2); FUNC_GROUP_DECL(NDSR2, AA1); #define Y2 99 #define Y2_DESC SIG_DESC_SET(SCU84, 27) -SIG_EXPR_LIST_DECL_SINGLE(VPIB5, VPI24, VPI_24_RSVD_DESC, Y2_DESC, COND2); -SIG_EXPR_LIST_DECL_SINGLE(NRI2, NRI2, Y2_DESC, COND2); -MS_PIN_DECL(Y2, GPIOM3, VPIB5, NRI2); +SIG_EXPR_LIST_DECL_SINGLE(Y2, VPIB5, VPI24, VPI_24_RSVD_DESC, Y2_DESC, COND2); +SIG_EXPR_LIST_DECL_SINGLE(Y2, NRI2, NRI2, Y2_DESC, COND2); +PIN_DECL_2(Y2, GPIOM3, VPIB5, NRI2); FUNC_GROUP_DECL(NRI2, Y2); #define AA2 100 #define AA2_DESC SIG_DESC_SET(SCU84, 28) -SIG_EXPR_LIST_DECL_SINGLE(VPIB6, VPI24, VPI_24_RSVD_DESC, AA2_DESC, COND2); -SIG_EXPR_LIST_DECL_SINGLE(NDTR2, NDTR2, AA2_DESC, COND2); -MS_PIN_DECL(AA2, GPIOM4, VPIB6, NDTR2); +SIG_EXPR_LIST_DECL_SINGLE(AA2, VPIB6, VPI24, VPI_24_RSVD_DESC, AA2_DESC, COND2); +SIG_EXPR_LIST_DECL_SINGLE(AA2, NDTR2, NDTR2, AA2_DESC, COND2); +PIN_DECL_2(AA2, GPIOM4, VPIB6, NDTR2); FUNC_GROUP_DECL(NDTR2, AA2); #define P5 101 #define P5_DESC SIG_DESC_SET(SCU84, 29) -SIG_EXPR_LIST_DECL_SINGLE(VPIB7, VPI24, VPI_24_RSVD_DESC, P5_DESC, COND2); -SIG_EXPR_LIST_DECL_SINGLE(NRTS2, NRTS2, P5_DESC, COND2); -MS_PIN_DECL(P5, GPIOM5, VPIB7, NRTS2); +SIG_EXPR_LIST_DECL_SINGLE(P5, VPIB7, VPI24, VPI_24_RSVD_DESC, P5_DESC, COND2); +SIG_EXPR_LIST_DECL_SINGLE(P5, NRTS2, NRTS2, P5_DESC, COND2); +PIN_DECL_2(P5, GPIOM5, VPIB7, NRTS2); FUNC_GROUP_DECL(NRTS2, P5); #define R5 102 #define R5_DESC SIG_DESC_SET(SCU84, 30) -SIG_EXPR_LIST_DECL_SINGLE(VPIB8, VPI24, VPI_24_RSVD_DESC, R5_DESC, COND2); -SIG_EXPR_LIST_DECL_SINGLE(TXD2, TXD2, R5_DESC, COND2); -MS_PIN_DECL(R5, GPIOM6, VPIB8, TXD2); +SIG_EXPR_LIST_DECL_SINGLE(R5, VPIB8, VPI24, VPI_24_RSVD_DESC, R5_DESC, COND2); +SIG_EXPR_LIST_DECL_SINGLE(R5, TXD2, TXD2, R5_DESC, COND2); +PIN_DECL_2(R5, GPIOM6, VPIB8, TXD2); FUNC_GROUP_DECL(TXD2, R5); #define T5 103 #define T5_DESC SIG_DESC_SET(SCU84, 31) -SIG_EXPR_LIST_DECL_SINGLE(VPIB9, VPI24, VPI_24_RSVD_DESC, T5_DESC, COND2); -SIG_EXPR_LIST_DECL_SINGLE(RXD2, RXD2, T5_DESC, COND2); -MS_PIN_DECL(T5, GPIOM7, VPIB9, RXD2); +SIG_EXPR_LIST_DECL_SINGLE(T5, VPIB9, VPI24, VPI_24_RSVD_DESC, T5_DESC, COND2); +SIG_EXPR_LIST_DECL_SINGLE(T5, RXD2, RXD2, T5_DESC, COND2); +PIN_DECL_2(T5, GPIOM7, VPIB9, RXD2); FUNC_GROUP_DECL(RXD2, T5); #define V2 104 #define V2_DESC SIG_DESC_SET(SCU88, 0) -SIG_EXPR_LIST_DECL_SINGLE(DASHN0, DASHN0, VPIRSVD_DESC, V2_DESC); -SIG_EXPR_LIST_DECL_SINGLE(PWM0, PWM0, V2_DESC, COND2); -MS_PIN_DECL(V2, GPION0, DASHN0, PWM0); +SIG_EXPR_LIST_DECL_SINGLE(V2, DASHN0, DASHN0, VPIRSVD_DESC, V2_DESC); +SIG_EXPR_LIST_DECL_SINGLE(V2, PWM0, PWM0, V2_DESC, COND2); +PIN_DECL_2(V2, GPION0, DASHN0, PWM0); FUNC_GROUP_DECL(PWM0, V2); #define W2 105 #define W2_DESC SIG_DESC_SET(SCU88, 1) -SIG_EXPR_LIST_DECL_SINGLE(DASHN1, DASHN1, VPIRSVD_DESC, W2_DESC); -SIG_EXPR_LIST_DECL_SINGLE(PWM1, PWM1, W2_DESC, COND2); -MS_PIN_DECL(W2, GPION1, DASHN1, PWM1); +SIG_EXPR_LIST_DECL_SINGLE(W2, DASHN1, DASHN1, VPIRSVD_DESC, W2_DESC); +SIG_EXPR_LIST_DECL_SINGLE(W2, PWM1, PWM1, W2_DESC, COND2); +PIN_DECL_2(W2, GPION1, DASHN1, PWM1); FUNC_GROUP_DECL(PWM1, W2); #define V3 106 #define V3_DESC SIG_DESC_SET(SCU88, 2) -SIG_EXPR_DECL(VPIG2, VPI24, VPI24_DESC, V3_DESC, COND2); -SIG_EXPR_DECL(VPIG2, VPIRSVD, VPIRSVD_DESC, V3_DESC, COND2); -SIG_EXPR_LIST_DECL_DUAL(VPIG2, VPI24, VPIRSVD); -SIG_EXPR_LIST_DECL_SINGLE(PWM2, PWM2, V3_DESC, COND2); -MS_PIN_DECL(V3, GPION2, VPIG2, PWM2); +SIG_EXPR_DECL_SINGLE(VPIG2, VPI24, VPI24_DESC, V3_DESC, COND2); +SIG_EXPR_DECL_SINGLE(VPIG2, VPIRSVD, VPIRSVD_DESC, V3_DESC, COND2); +SIG_EXPR_LIST_DECL_DUAL(V3, VPIG2, VPI24, VPIRSVD); +SIG_EXPR_LIST_DECL_SINGLE(V3, PWM2, PWM2, V3_DESC, COND2); +PIN_DECL_2(V3, GPION2, VPIG2, PWM2); FUNC_GROUP_DECL(PWM2, V3); #define U3 107 #define U3_DESC SIG_DESC_SET(SCU88, 3) -SIG_EXPR_DECL(VPIG3, VPI24, VPI24_DESC, U3_DESC, COND2); -SIG_EXPR_DECL(VPIG3, VPIRSVD, VPIRSVD_DESC, U3_DESC, COND2); -SIG_EXPR_LIST_DECL_DUAL(VPIG3, VPI24, VPIRSVD); -SIG_EXPR_LIST_DECL_SINGLE(PWM3, PWM3, U3_DESC, COND2); -MS_PIN_DECL(U3, GPION3, VPIG3, PWM3); +SIG_EXPR_DECL_SINGLE(VPIG3, VPI24, VPI24_DESC, U3_DESC, COND2); +SIG_EXPR_DECL_SINGLE(VPIG3, VPIRSVD, VPIRSVD_DESC, U3_DESC, COND2); +SIG_EXPR_LIST_DECL_DUAL(U3, VPIG3, VPI24, VPIRSVD); +SIG_EXPR_LIST_DECL_SINGLE(U3, PWM3, PWM3, U3_DESC, COND2); +PIN_DECL_2(U3, GPION3, VPIG3, PWM3); FUNC_GROUP_DECL(PWM3, U3); #define W3 108 #define W3_DESC SIG_DESC_SET(SCU88, 4) -SIG_EXPR_DECL(VPIG4, VPI24, VPI24_DESC, W3_DESC, COND2); -SIG_EXPR_DECL(VPIG4, VPIRSVD, VPIRSVD_DESC, W3_DESC, COND2); -SIG_EXPR_LIST_DECL_DUAL(VPIG4, VPI24, VPIRSVD); -SIG_EXPR_LIST_DECL_SINGLE(PWM4, PWM4, W3_DESC, COND2); -MS_PIN_DECL(W3, GPION4, VPIG4, PWM4); +SIG_EXPR_DECL_SINGLE(VPIG4, VPI24, VPI24_DESC, W3_DESC, COND2); +SIG_EXPR_DECL_SINGLE(VPIG4, VPIRSVD, VPIRSVD_DESC, W3_DESC, COND2); +SIG_EXPR_LIST_DECL_DUAL(W3, VPIG4, VPI24, VPIRSVD); +SIG_EXPR_LIST_DECL_SINGLE(W3, PWM4, PWM4, W3_DESC, COND2); +PIN_DECL_2(W3, GPION4, VPIG4, PWM4); FUNC_GROUP_DECL(PWM4, W3); #define AA3 109 #define AA3_DESC SIG_DESC_SET(SCU88, 5) -SIG_EXPR_DECL(VPIG5, VPI24, VPI24_DESC, AA3_DESC, COND2); -SIG_EXPR_DECL(VPIG5, VPIRSVD, VPIRSVD_DESC, AA3_DESC, COND2); -SIG_EXPR_LIST_DECL_DUAL(VPIG5, VPI24, VPIRSVD); -SIG_EXPR_LIST_DECL_SINGLE(PWM5, PWM5, AA3_DESC, COND2); -MS_PIN_DECL(AA3, GPION5, VPIG5, PWM5); +SIG_EXPR_DECL_SINGLE(VPIG5, VPI24, VPI24_DESC, AA3_DESC, COND2); +SIG_EXPR_DECL_SINGLE(VPIG5, VPIRSVD, VPIRSVD_DESC, AA3_DESC, COND2); +SIG_EXPR_LIST_DECL_DUAL(AA3, VPIG5, VPI24, VPIRSVD); +SIG_EXPR_LIST_DECL_SINGLE(AA3, PWM5, PWM5, AA3_DESC, COND2); +PIN_DECL_2(AA3, GPION5, VPIG5, PWM5); FUNC_GROUP_DECL(PWM5, AA3); #define Y3 110 #define Y3_DESC SIG_DESC_SET(SCU88, 6) -SIG_EXPR_LIST_DECL_SINGLE(VPIG6, VPI24, VPI24_DESC, Y3_DESC); -SIG_EXPR_LIST_DECL_SINGLE(PWM6, PWM6, Y3_DESC, COND2); -MS_PIN_DECL(Y3, GPION6, VPIG6, PWM6); +SIG_EXPR_LIST_DECL_SINGLE(Y3, VPIG6, VPI24, VPI24_DESC, Y3_DESC); +SIG_EXPR_LIST_DECL_SINGLE(Y3, PWM6, PWM6, Y3_DESC, COND2); +PIN_DECL_2(Y3, GPION6, VPIG6, PWM6); FUNC_GROUP_DECL(PWM6, Y3); #define T4 111 #define T4_DESC SIG_DESC_SET(SCU88, 7) -SIG_EXPR_LIST_DECL_SINGLE(VPIG7, VPI24, VPI24_DESC, T4_DESC); -SIG_EXPR_LIST_DECL_SINGLE(PWM7, PWM7, T4_DESC, COND2); -MS_PIN_DECL(T4, GPION7, VPIG7, PWM7); +SIG_EXPR_LIST_DECL_SINGLE(T4, VPIG7, VPI24, VPI24_DESC, T4_DESC); +SIG_EXPR_LIST_DECL_SINGLE(T4, PWM7, PWM7, T4_DESC, COND2); +PIN_DECL_2(T4, GPION7, VPIG7, PWM7); FUNC_GROUP_DECL(PWM7, T4); #define U5 112 -SIG_EXPR_LIST_DECL_SINGLE(VPIG8, VPI24, VPI24_DESC, SIG_DESC_SET(SCU88, 8), +SIG_EXPR_LIST_DECL_SINGLE(U5, VPIG8, VPI24, VPI24_DESC, SIG_DESC_SET(SCU88, 8), COND2); -SS_PIN_DECL(U5, GPIOO0, VPIG8); +PIN_DECL_1(U5, GPIOO0, VPIG8); #define U4 113 -SIG_EXPR_LIST_DECL_SINGLE(VPIG9, VPI24, VPI24_DESC, SIG_DESC_SET(SCU88, 9), +SIG_EXPR_LIST_DECL_SINGLE(U4, VPIG9, VPI24, VPI24_DESC, SIG_DESC_SET(SCU88, 9), COND2); -SS_PIN_DECL(U4, GPIOO1, VPIG9); +PIN_DECL_1(U4, GPIOO1, VPIG9); #define V5 114 -SIG_EXPR_LIST_DECL_SINGLE(DASHV5, DASHV5, VPI_24_RSVD_DESC, +SIG_EXPR_LIST_DECL_SINGLE(V5, DASHV5, DASHV5, VPI_24_RSVD_DESC, SIG_DESC_SET(SCU88, 10)); -SS_PIN_DECL(V5, GPIOO2, DASHV5); +PIN_DECL_1(V5, GPIOO2, DASHV5); #define AB4 115 -SIG_EXPR_LIST_DECL_SINGLE(DASHAB4, DASHAB4, VPI_24_RSVD_DESC, +SIG_EXPR_LIST_DECL_SINGLE(AB4, DASHAB4, DASHAB4, VPI_24_RSVD_DESC, SIG_DESC_SET(SCU88, 11)); -SS_PIN_DECL(AB4, GPIOO3, DASHAB4); +PIN_DECL_1(AB4, GPIOO3, DASHAB4); #define AB3 116 -SIG_EXPR_LIST_DECL_SINGLE(VPIR2, VPI24, VPI24_DESC, SIG_DESC_SET(SCU88, 12), - COND2); -SS_PIN_DECL(AB3, GPIOO4, VPIR2); +SIG_EXPR_LIST_DECL_SINGLE(AB3, VPIR2, VPI24, VPI24_DESC, + SIG_DESC_SET(SCU88, 12), COND2); +PIN_DECL_1(AB3, GPIOO4, VPIR2); #define Y4 117 -SIG_EXPR_LIST_DECL_SINGLE(VPIR3, VPI24, VPI24_DESC, SIG_DESC_SET(SCU88, 13), - COND2); -SS_PIN_DECL(Y4, GPIOO5, VPIR3); +SIG_EXPR_LIST_DECL_SINGLE(Y4, VPIR3, VPI24, VPI24_DESC, + SIG_DESC_SET(SCU88, 13), COND2); +PIN_DECL_1(Y4, GPIOO5, VPIR3); #define AA4 118 -SIG_EXPR_LIST_DECL_SINGLE(VPIR4, VPI24, VPI24_DESC, SIG_DESC_SET(SCU88, 14), - COND2); -SS_PIN_DECL(AA4, GPIOO6, VPIR4); +SIG_EXPR_LIST_DECL_SINGLE(AA4, VPIR4, VPI24, VPI24_DESC, + SIG_DESC_SET(SCU88, 14), COND2); +PIN_DECL_1(AA4, GPIOO6, VPIR4); #define W4 119 -SIG_EXPR_LIST_DECL_SINGLE(VPIR5, VPI24, VPI24_DESC, SIG_DESC_SET(SCU88, 15), - COND2); -SS_PIN_DECL(W4, GPIOO7, VPIR5); +SIG_EXPR_LIST_DECL_SINGLE(W4, VPIR5, VPI24, VPI24_DESC, + SIG_DESC_SET(SCU88, 15), COND2); +PIN_DECL_1(W4, GPIOO7, VPIR5); #define V4 120 -SIG_EXPR_LIST_DECL_SINGLE(VPIR6, VPI24, VPI24_DESC, SIG_DESC_SET(SCU88, 16), - COND2); -SS_PIN_DECL(V4, GPIOP0, VPIR6); +SIG_EXPR_LIST_DECL_SINGLE(V4, VPIR6, VPI24, VPI24_DESC, + SIG_DESC_SET(SCU88, 16), COND2); +PIN_DECL_1(V4, GPIOP0, VPIR6); #define W5 121 -SIG_EXPR_LIST_DECL_SINGLE(VPIR7, VPI24, VPI24_DESC, SIG_DESC_SET(SCU88, 17), - COND2); -SS_PIN_DECL(W5, GPIOP1, VPIR7); +SIG_EXPR_LIST_DECL_SINGLE(W5, VPIR7, VPI24, VPI24_DESC, + SIG_DESC_SET(SCU88, 17), COND2); +PIN_DECL_1(W5, GPIOP1, VPIR7); #define AA5 122 -SIG_EXPR_LIST_DECL_SINGLE(VPIR8, VPI24, VPI24_DESC, SIG_DESC_SET(SCU88, 18), - COND2); -SS_PIN_DECL(AA5, GPIOP2, VPIR8); +SIG_EXPR_LIST_DECL_SINGLE(AA5, VPIR8, VPI24, VPI24_DESC, + SIG_DESC_SET(SCU88, 18), COND2); +PIN_DECL_1(AA5, GPIOP2, VPIR8); #define AB5 123 -SIG_EXPR_LIST_DECL_SINGLE(VPIR9, VPI24, VPI24_DESC, SIG_DESC_SET(SCU88, 19), - COND2); -SS_PIN_DECL(AB5, GPIOP3, VPIR9); +SIG_EXPR_LIST_DECL_SINGLE(AB5, VPIR9, VPI24, VPI24_DESC, + SIG_DESC_SET(SCU88, 19), COND2); +PIN_DECL_1(AB5, GPIOP3, VPIR9); FUNC_GROUP_DECL(VPI24, T1, U2, P4, P3, Y1, AB2, AA1, Y2, AA2, P5, R5, T5, V3, U3, W3, AA3, Y3, T4, U5, U4, AB3, Y4, AA4, W4, V4, W5, AA5, AB5); #define Y6 124 -SIG_EXPR_LIST_DECL_SINGLE(DASHY6, DASHY6, SIG_DESC_SET(SCU90, 28), +SIG_EXPR_LIST_DECL_SINGLE(Y6, DASHY6, DASHY6, SIG_DESC_SET(SCU90, 28), SIG_DESC_SET(SCU88, 20)); -SS_PIN_DECL(Y6, GPIOP4, DASHY6); +PIN_DECL_1(Y6, GPIOP4, DASHY6); #define Y5 125 -SIG_EXPR_LIST_DECL_SINGLE(DASHY5, DASHY5, SIG_DESC_SET(SCU90, 28), +SIG_EXPR_LIST_DECL_SINGLE(Y5, DASHY5, DASHY5, SIG_DESC_SET(SCU90, 28), SIG_DESC_SET(SCU88, 21)); -SS_PIN_DECL(Y5, GPIOP5, DASHY5); +PIN_DECL_1(Y5, GPIOP5, DASHY5); #define W6 126 -SIG_EXPR_LIST_DECL_SINGLE(DASHW6, DASHW6, SIG_DESC_SET(SCU90, 28), +SIG_EXPR_LIST_DECL_SINGLE(W6, DASHW6, DASHW6, SIG_DESC_SET(SCU90, 28), SIG_DESC_SET(SCU88, 22)); -SS_PIN_DECL(W6, GPIOP6, DASHW6); +PIN_DECL_1(W6, GPIOP6, DASHW6); #define V6 127 -SIG_EXPR_LIST_DECL_SINGLE(DASHV6, DASHV6, SIG_DESC_SET(SCU90, 28), +SIG_EXPR_LIST_DECL_SINGLE(V6, DASHV6, DASHV6, SIG_DESC_SET(SCU90, 28), SIG_DESC_SET(SCU88, 23)); -SS_PIN_DECL(V6, GPIOP7, DASHV6); +PIN_DECL_1(V6, GPIOP7, DASHV6); #define I2C3_DESC SIG_DESC_SET(SCU90, 16) #define A11 128 -SIG_EXPR_LIST_DECL_SINGLE(SCL3, I2C3, I2C3_DESC); -SS_PIN_DECL(A11, GPIOQ0, SCL3); +SIG_EXPR_LIST_DECL_SINGLE(A11, SCL3, I2C3, I2C3_DESC); +PIN_DECL_1(A11, GPIOQ0, SCL3); #define A10 129 -SIG_EXPR_LIST_DECL_SINGLE(SDA3, I2C3, I2C3_DESC); -SS_PIN_DECL(A10, GPIOQ1, SDA3); +SIG_EXPR_LIST_DECL_SINGLE(A10, SDA3, I2C3, I2C3_DESC); +PIN_DECL_1(A10, GPIOQ1, SDA3); FUNC_GROUP_DECL(I2C3, A11, A10); #define I2C4_DESC SIG_DESC_SET(SCU90, 17) #define A9 130 -SIG_EXPR_LIST_DECL_SINGLE(SCL4, I2C4, I2C4_DESC); -SS_PIN_DECL(A9, GPIOQ2, SCL4); +SIG_EXPR_LIST_DECL_SINGLE(A9, SCL4, I2C4, I2C4_DESC); +PIN_DECL_1(A9, GPIOQ2, SCL4); #define B9 131 -SIG_EXPR_LIST_DECL_SINGLE(SDA4, I2C4, I2C4_DESC); -SS_PIN_DECL(B9, GPIOQ3, SDA4); +SIG_EXPR_LIST_DECL_SINGLE(B9, SDA4, I2C4, I2C4_DESC); +PIN_DECL_1(B9, GPIOQ3, SDA4); FUNC_GROUP_DECL(I2C4, A9, B9); #define I2C14_DESC SIG_DESC_SET(SCU90, 27) #define N21 132 -SIG_EXPR_LIST_DECL_SINGLE(SCL14, I2C14, I2C14_DESC); -SS_PIN_DECL(N21, GPIOQ4, SCL14); +SIG_EXPR_LIST_DECL_SINGLE(N21, SCL14, I2C14, I2C14_DESC); +PIN_DECL_1(N21, GPIOQ4, SCL14); #define N22 133 -SIG_EXPR_LIST_DECL_SINGLE(SDA14, I2C14, I2C14_DESC); -SS_PIN_DECL(N22, GPIOQ5, SDA14); +SIG_EXPR_LIST_DECL_SINGLE(N22, SDA14, I2C14, I2C14_DESC); +PIN_DECL_1(N22, GPIOQ5, SDA14); FUNC_GROUP_DECL(I2C14, N21, N22); @@ -996,12 +1011,12 @@ SSSF_PIN_DECL(W19, GPIOR4, SPI2MOSI, SIG_DESC_SET(SCU88, 28), COND2); SSSF_PIN_DECL(V19, GPIOR5, SPI2MISO, SIG_DESC_SET(SCU88, 29), COND2); #define D8 142 -SIG_EXPR_LIST_DECL_SINGLE(MDC1, MDIO1, SIG_DESC_SET(SCU88, 30)); -SS_PIN_DECL(D8, GPIOR6, MDC1); +SIG_EXPR_LIST_DECL_SINGLE(D8, MDC1, MDIO1, SIG_DESC_SET(SCU88, 30)); +PIN_DECL_1(D8, GPIOR6, MDC1); #define E10 143 -SIG_EXPR_LIST_DECL_SINGLE(MDIO1, MDIO1, SIG_DESC_SET(SCU88, 31)); -SS_PIN_DECL(E10, GPIOR7, MDIO1); +SIG_EXPR_LIST_DECL_SINGLE(E10, MDIO1, MDIO1, SIG_DESC_SET(SCU88, 31)); +PIN_DECL_1(E10, GPIOR7, MDIO1); FUNC_GROUP_DECL(MDIO1, D8, E10); @@ -1014,83 +1029,107 @@ FUNC_GROUP_DECL(MDIO1, D8, E10); #define V20 144 #define V20_DESC SIG_DESC_SET(SCU8C, 0) -SIG_EXPR_DECL(VPOB2, VPO, V20_DESC, VPO_DESC, CRT_DVO_EN_DESC); -SIG_EXPR_DECL(VPOB2, VPOOFF1, V20_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC); -SIG_EXPR_DECL(VPOB2, VPOOFF2, V20_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC); -SIG_EXPR_LIST_DECL(VPOB2, SIG_EXPR_PTR(VPOB2, VPO), - SIG_EXPR_PTR(VPOB2, VPOOFF1), SIG_EXPR_PTR(VPOB2, VPOOFF2)); -SIG_EXPR_LIST_DECL_SINGLE(SPI2CS1, SPI2CS1, V20_DESC); -MS_PIN_DECL(V20, GPIOS0, VPOB2, SPI2CS1); +SIG_EXPR_DECL_SINGLE(VPOB2, VPO, V20_DESC, VPO_DESC, CRT_DVO_EN_DESC); +SIG_EXPR_DECL_SINGLE(VPOB2, VPOOFF1, V20_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC); +SIG_EXPR_DECL_SINGLE(VPOB2, VPOOFF2, V20_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC); +SIG_EXPR_LIST_DECL(VPOB2, VPO, + SIG_EXPR_PTR(VPOB2, VPO), + SIG_EXPR_PTR(VPOB2, VPOOFF1), + SIG_EXPR_PTR(VPOB2, VPOOFF2)); +SIG_EXPR_LIST_ALIAS(V20, VPOB2, VPO); +SIG_EXPR_LIST_DECL_SINGLE(V20, SPI2CS1, SPI2CS1, V20_DESC); +PIN_DECL_2(V20, GPIOS0, VPOB2, SPI2CS1); FUNC_GROUP_DECL(SPI2CS1, V20); #define U19 145 #define U19_DESC SIG_DESC_SET(SCU8C, 1) -SIG_EXPR_DECL(VPOB3, VPO, U19_DESC, VPO_DESC, CRT_DVO_EN_DESC); -SIG_EXPR_DECL(VPOB3, VPOOFF1, U19_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC); -SIG_EXPR_DECL(VPOB3, VPOOFF2, U19_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC); -SIG_EXPR_LIST_DECL(VPOB3, SIG_EXPR_PTR(VPOB3, VPO), - SIG_EXPR_PTR(VPOB3, VPOOFF1), SIG_EXPR_PTR(VPOB3, VPOOFF2)); -SIG_EXPR_LIST_DECL_SINGLE(BMCINT, BMCINT, U19_DESC); -MS_PIN_DECL(U19, GPIOS1, VPOB3, BMCINT); +SIG_EXPR_DECL_SINGLE(VPOB3, VPO, U19_DESC, VPO_DESC, CRT_DVO_EN_DESC); +SIG_EXPR_DECL_SINGLE(VPOB3, VPOOFF1, U19_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC); +SIG_EXPR_DECL_SINGLE(VPOB3, VPOOFF2, U19_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC); +SIG_EXPR_LIST_DECL(VPOB3, VPO, + SIG_EXPR_PTR(VPOB3, VPO), + SIG_EXPR_PTR(VPOB3, VPOOFF1), + SIG_EXPR_PTR(VPOB3, VPOOFF2)); +SIG_EXPR_LIST_ALIAS(U19, VPOB3, VPO); +SIG_EXPR_LIST_DECL_SINGLE(U19, BMCINT, BMCINT, U19_DESC); +PIN_DECL_2(U19, GPIOS1, VPOB3, BMCINT); FUNC_GROUP_DECL(BMCINT, U19); #define R18 146 #define R18_DESC SIG_DESC_SET(SCU8C, 2) -SIG_EXPR_DECL(VPOB4, VPO, R18_DESC, VPO_DESC, CRT_DVO_EN_DESC); -SIG_EXPR_DECL(VPOB4, VPOOFF1, R18_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC); -SIG_EXPR_DECL(VPOB4, VPOOFF2, R18_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC); -SIG_EXPR_LIST_DECL(VPOB4, SIG_EXPR_PTR(VPOB4, VPO), - SIG_EXPR_PTR(VPOB4, VPOOFF1), SIG_EXPR_PTR(VPOB4, VPOOFF2)); -SIG_EXPR_LIST_DECL_SINGLE(SALT5, SALT5, R18_DESC); -MS_PIN_DECL(R18, GPIOS2, VPOB4, SALT5); +SIG_EXPR_DECL_SINGLE(VPOB4, VPO, R18_DESC, VPO_DESC, CRT_DVO_EN_DESC); +SIG_EXPR_DECL_SINGLE(VPOB4, VPOOFF1, R18_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC); +SIG_EXPR_DECL_SINGLE(VPOB4, VPOOFF2, R18_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC); +SIG_EXPR_LIST_DECL(VPOB4, VPO, + SIG_EXPR_PTR(VPOB4, VPO), + SIG_EXPR_PTR(VPOB4, VPOOFF1), + SIG_EXPR_PTR(VPOB4, VPOOFF2)); +SIG_EXPR_LIST_ALIAS(R18, VPOB4, VPO); +SIG_EXPR_LIST_DECL_SINGLE(R18, SALT5, SALT5, R18_DESC); +PIN_DECL_2(R18, GPIOS2, VPOB4, SALT5); FUNC_GROUP_DECL(SALT5, R18); #define P18 147 #define P18_DESC SIG_DESC_SET(SCU8C, 3) -SIG_EXPR_DECL(VPOB5, VPO, P18_DESC, VPO_DESC, CRT_DVO_EN_DESC); -SIG_EXPR_DECL(VPOB5, VPOOFF1, P18_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC); -SIG_EXPR_DECL(VPOB5, VPOOFF2, P18_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC); -SIG_EXPR_LIST_DECL(VPOB5, SIG_EXPR_PTR(VPOB5, VPO), - SIG_EXPR_PTR(VPOB5, VPOOFF1), SIG_EXPR_PTR(VPOB5, VPOOFF2)); -SIG_EXPR_LIST_DECL_SINGLE(SALT6, SALT6, P18_DESC); -MS_PIN_DECL(P18, GPIOS3, VPOB5, SALT6); +SIG_EXPR_DECL_SINGLE(VPOB5, VPO, P18_DESC, VPO_DESC, CRT_DVO_EN_DESC); +SIG_EXPR_DECL_SINGLE(VPOB5, VPOOFF1, P18_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC); +SIG_EXPR_DECL_SINGLE(VPOB5, VPOOFF2, P18_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC); +SIG_EXPR_LIST_DECL(VPOB5, VPO, + SIG_EXPR_PTR(VPOB5, VPO), + SIG_EXPR_PTR(VPOB5, VPOOFF1), + SIG_EXPR_PTR(VPOB5, VPOOFF2)); +SIG_EXPR_LIST_ALIAS(P18, VPOB5, VPO); +SIG_EXPR_LIST_DECL_SINGLE(P18, SALT6, SALT6, P18_DESC); +PIN_DECL_2(P18, GPIOS3, VPOB5, SALT6); FUNC_GROUP_DECL(SALT6, P18); #define R19 148 #define R19_DESC SIG_DESC_SET(SCU8C, 4) -SIG_EXPR_DECL(VPOB6, VPO, R19_DESC, VPO_DESC, CRT_DVO_EN_DESC); -SIG_EXPR_DECL(VPOB6, VPOOFF1, R19_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC); -SIG_EXPR_DECL(VPOB6, VPOOFF2, R19_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC); -SIG_EXPR_LIST_DECL(VPOB6, SIG_EXPR_PTR(VPOB6, VPO), - SIG_EXPR_PTR(VPOB6, VPOOFF1), SIG_EXPR_PTR(VPOB6, VPOOFF2)); -SS_PIN_DECL(R19, GPIOS4, VPOB6); +SIG_EXPR_DECL_SINGLE(VPOB6, VPO, R19_DESC, VPO_DESC, CRT_DVO_EN_DESC); +SIG_EXPR_DECL_SINGLE(VPOB6, VPOOFF1, R19_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC); +SIG_EXPR_DECL_SINGLE(VPOB6, VPOOFF2, R19_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC); +SIG_EXPR_LIST_DECL(VPOB6, VPO, + SIG_EXPR_PTR(VPOB6, VPO), + SIG_EXPR_PTR(VPOB6, VPOOFF1), + SIG_EXPR_PTR(VPOB6, VPOOFF2)); +SIG_EXPR_LIST_ALIAS(R19, VPOB6, VPO); +PIN_DECL_1(R19, GPIOS4, VPOB6); #define W20 149 #define W20_DESC SIG_DESC_SET(SCU8C, 5) -SIG_EXPR_DECL(VPOB7, VPO, W20_DESC, VPO_DESC, CRT_DVO_EN_DESC); -SIG_EXPR_DECL(VPOB7, VPOOFF1, W20_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC); -SIG_EXPR_DECL(VPOB7, VPOOFF2, W20_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC); -SIG_EXPR_LIST_DECL(VPOB7, SIG_EXPR_PTR(VPOB7, VPO), - SIG_EXPR_PTR(VPOB7, VPOOFF1), SIG_EXPR_PTR(VPOB7, VPOOFF2)); -SS_PIN_DECL(W20, GPIOS5, VPOB7); +SIG_EXPR_DECL_SINGLE(VPOB7, VPO, W20_DESC, VPO_DESC, CRT_DVO_EN_DESC); +SIG_EXPR_DECL_SINGLE(VPOB7, VPOOFF1, W20_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC); +SIG_EXPR_DECL_SINGLE(VPOB7, VPOOFF2, W20_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC); +SIG_EXPR_LIST_DECL(VPOB7, VPO, + SIG_EXPR_PTR(VPOB7, VPO), + SIG_EXPR_PTR(VPOB7, VPOOFF1), + SIG_EXPR_PTR(VPOB7, VPOOFF2)); +SIG_EXPR_LIST_ALIAS(W20, VPOB7, VPO); +PIN_DECL_1(W20, GPIOS5, VPOB7); #define U20 150 #define U20_DESC SIG_DESC_SET(SCU8C, 6) -SIG_EXPR_DECL(VPOB8, VPO, U20_DESC, VPO_DESC, CRT_DVO_EN_DESC); -SIG_EXPR_DECL(VPOB8, VPOOFF1, U20_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC); -SIG_EXPR_DECL(VPOB8, VPOOFF2, U20_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC); -SIG_EXPR_LIST_DECL(VPOB8, SIG_EXPR_PTR(VPOB8, VPO), - SIG_EXPR_PTR(VPOB8, VPOOFF1), SIG_EXPR_PTR(VPOB8, VPOOFF2)); -SS_PIN_DECL(U20, GPIOS6, VPOB8); +SIG_EXPR_DECL_SINGLE(VPOB8, VPO, U20_DESC, VPO_DESC, CRT_DVO_EN_DESC); +SIG_EXPR_DECL_SINGLE(VPOB8, VPOOFF1, U20_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC); +SIG_EXPR_DECL_SINGLE(VPOB8, VPOOFF2, U20_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC); +SIG_EXPR_LIST_DECL(VPOB8, VPO, + SIG_EXPR_PTR(VPOB8, VPO), + SIG_EXPR_PTR(VPOB8, VPOOFF1), + SIG_EXPR_PTR(VPOB8, VPOOFF2)); +SIG_EXPR_LIST_ALIAS(U20, VPOB8, VPO); +PIN_DECL_1(U20, GPIOS6, VPOB8); #define AA20 151 #define AA20_DESC SIG_DESC_SET(SCU8C, 7) -SIG_EXPR_DECL(VPOB9, VPO, AA20_DESC, VPO_DESC, CRT_DVO_EN_DESC); -SIG_EXPR_DECL(VPOB9, VPOOFF1, AA20_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC); -SIG_EXPR_DECL(VPOB9, VPOOFF2, AA20_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC); -SIG_EXPR_LIST_DECL(VPOB9, SIG_EXPR_PTR(VPOB9, VPO), - SIG_EXPR_PTR(VPOB9, VPOOFF1), SIG_EXPR_PTR(VPOB9, VPOOFF2)); -SS_PIN_DECL(AA20, GPIOS7, VPOB9); +SIG_EXPR_DECL_SINGLE(VPOB9, VPO, AA20_DESC, VPO_DESC, CRT_DVO_EN_DESC); +SIG_EXPR_DECL_SINGLE(VPOB9, VPOOFF1, AA20_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC); +SIG_EXPR_DECL_SINGLE(VPOB9, VPOOFF2, AA20_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC); +SIG_EXPR_LIST_DECL(VPOB9, VPO, + SIG_EXPR_PTR(VPOB9, VPO), + SIG_EXPR_PTR(VPOB9, VPOOFF1), + SIG_EXPR_PTR(VPOB9, VPOOFF2)); +SIG_EXPR_LIST_ALIAS(AA20, VPOB9, VPO); +PIN_DECL_1(AA20, GPIOS7, VPOB9); /* RGMII1/RMII1 */ @@ -1098,309 +1137,309 @@ SS_PIN_DECL(AA20, GPIOS7, VPOB9); #define RMII2_DESC SIG_DESC_BIT(HW_STRAP1, 7, 0) #define B5 152 -SIG_EXPR_LIST_DECL_SINGLE(GPIOT0, GPIOT0, SIG_DESC_SET(SCUA0, 0)); -SIG_EXPR_LIST_DECL_SINGLE(RMII1RCLKO, RMII1, RMII1_DESC, +SIG_EXPR_LIST_DECL_SINGLE(B5, GPIOT0, GPIOT0, SIG_DESC_SET(SCUA0, 0)); +SIG_EXPR_LIST_DECL_SINGLE(B5, RMII1RCLKO, RMII1, RMII1_DESC, SIG_DESC_SET(SCU48, 29)); -SIG_EXPR_LIST_DECL_SINGLE(RGMII1TXCK, RGMII1); -MS_PIN_DECL_(B5, SIG_EXPR_LIST_PTR(GPIOT0), SIG_EXPR_LIST_PTR(RMII1RCLKO), - SIG_EXPR_LIST_PTR(RGMII1TXCK)); +SIG_EXPR_LIST_DECL_SINGLE(B5, RGMII1TXCK, RGMII1); +PIN_DECL_(B5, SIG_EXPR_LIST_PTR(B5, GPIOT0), SIG_EXPR_LIST_PTR(B5, RMII1RCLKO), + SIG_EXPR_LIST_PTR(B5, RGMII1TXCK)); #define E9 153 -SIG_EXPR_LIST_DECL_SINGLE(GPIOT1, GPIOT1, SIG_DESC_SET(SCUA0, 1)); -SIG_EXPR_LIST_DECL_SINGLE(RMII1TXEN, RMII1, RMII1_DESC); -SIG_EXPR_LIST_DECL_SINGLE(RGMII1TXCTL, RGMII1); -MS_PIN_DECL_(E9, SIG_EXPR_LIST_PTR(GPIOT1), SIG_EXPR_LIST_PTR(RMII1TXEN), - SIG_EXPR_LIST_PTR(RGMII1TXCTL)); +SIG_EXPR_LIST_DECL_SINGLE(E9, GPIOT1, GPIOT1, SIG_DESC_SET(SCUA0, 1)); +SIG_EXPR_LIST_DECL_SINGLE(E9, RMII1TXEN, RMII1, RMII1_DESC); +SIG_EXPR_LIST_DECL_SINGLE(E9, RGMII1TXCTL, RGMII1); +PIN_DECL_(E9, SIG_EXPR_LIST_PTR(E9, GPIOT1), SIG_EXPR_LIST_PTR(E9, RMII1TXEN), + SIG_EXPR_LIST_PTR(E9, RGMII1TXCTL)); #define F9 154 -SIG_EXPR_LIST_DECL_SINGLE(GPIOT2, GPIOT2, SIG_DESC_SET(SCUA0, 2)); -SIG_EXPR_LIST_DECL_SINGLE(RMII1TXD0, RMII1, RMII1_DESC); -SIG_EXPR_LIST_DECL_SINGLE(RGMII1TXD0, RGMII1); -MS_PIN_DECL_(F9, SIG_EXPR_LIST_PTR(GPIOT2), SIG_EXPR_LIST_PTR(RMII1TXD0), - SIG_EXPR_LIST_PTR(RGMII1TXD0)); +SIG_EXPR_LIST_DECL_SINGLE(F9, GPIOT2, GPIOT2, SIG_DESC_SET(SCUA0, 2)); +SIG_EXPR_LIST_DECL_SINGLE(F9, RMII1TXD0, RMII1, RMII1_DESC); +SIG_EXPR_LIST_DECL_SINGLE(F9, RGMII1TXD0, RGMII1); +PIN_DECL_(F9, SIG_EXPR_LIST_PTR(F9, GPIOT2), SIG_EXPR_LIST_PTR(F9, RMII1TXD0), + SIG_EXPR_LIST_PTR(F9, RGMII1TXD0)); #define A5 155 -SIG_EXPR_LIST_DECL_SINGLE(GPIOT3, GPIOT3, SIG_DESC_SET(SCUA0, 3)); -SIG_EXPR_LIST_DECL_SINGLE(RMII1TXD1, RMII1, RMII1_DESC); -SIG_EXPR_LIST_DECL_SINGLE(RGMII1TXD1, RGMII1); -MS_PIN_DECL_(A5, SIG_EXPR_LIST_PTR(GPIOT3), SIG_EXPR_LIST_PTR(RMII1TXD1), - SIG_EXPR_LIST_PTR(RGMII1TXD1)); +SIG_EXPR_LIST_DECL_SINGLE(A5, GPIOT3, GPIOT3, SIG_DESC_SET(SCUA0, 3)); +SIG_EXPR_LIST_DECL_SINGLE(A5, RMII1TXD1, RMII1, RMII1_DESC); +SIG_EXPR_LIST_DECL_SINGLE(A5, RGMII1TXD1, RGMII1); +PIN_DECL_(A5, SIG_EXPR_LIST_PTR(A5, GPIOT3), SIG_EXPR_LIST_PTR(A5, RMII1TXD1), + SIG_EXPR_LIST_PTR(A5, RGMII1TXD1)); #define E7 156 -SIG_EXPR_LIST_DECL_SINGLE(GPIOT4, GPIOT4, SIG_DESC_SET(SCUA0, 4)); -SIG_EXPR_LIST_DECL_SINGLE(RMII1DASH0, RMII1, RMII1_DESC); -SIG_EXPR_LIST_DECL_SINGLE(RGMII1TXD2, RGMII1); -MS_PIN_DECL_(E7, SIG_EXPR_LIST_PTR(GPIOT4), SIG_EXPR_LIST_PTR(RMII1DASH0), - SIG_EXPR_LIST_PTR(RGMII1TXD2)); +SIG_EXPR_LIST_DECL_SINGLE(E7, GPIOT4, GPIOT4, SIG_DESC_SET(SCUA0, 4)); +SIG_EXPR_LIST_DECL_SINGLE(E7, RMII1DASH0, RMII1, RMII1_DESC); +SIG_EXPR_LIST_DECL_SINGLE(E7, RGMII1TXD2, RGMII1); +PIN_DECL_(E7, SIG_EXPR_LIST_PTR(E7, GPIOT4), SIG_EXPR_LIST_PTR(E7, RMII1DASH0), + SIG_EXPR_LIST_PTR(E7, RGMII1TXD2)); #define D7 157 -SIG_EXPR_LIST_DECL_SINGLE(GPIOT5, GPIOT5, SIG_DESC_SET(SCUA0, 5)); -SIG_EXPR_LIST_DECL_SINGLE(RMII1DASH1, RMII1, RMII1_DESC); -SIG_EXPR_LIST_DECL_SINGLE(RGMII1TXD3, RGMII1); -MS_PIN_DECL_(D7, SIG_EXPR_LIST_PTR(GPIOT5), SIG_EXPR_LIST_PTR(RMII1DASH1), - SIG_EXPR_LIST_PTR(RGMII1TXD3)); +SIG_EXPR_LIST_DECL_SINGLE(D7, GPIOT5, GPIOT5, SIG_DESC_SET(SCUA0, 5)); +SIG_EXPR_LIST_DECL_SINGLE(D7, RMII1DASH1, RMII1, RMII1_DESC); +SIG_EXPR_LIST_DECL_SINGLE(D7, RGMII1TXD3, RGMII1); +PIN_DECL_(D7, SIG_EXPR_LIST_PTR(D7, GPIOT5), SIG_EXPR_LIST_PTR(D7, RMII1DASH1), + SIG_EXPR_LIST_PTR(D7, RGMII1TXD3)); #define B2 158 -SIG_EXPR_LIST_DECL_SINGLE(GPIOT6, GPIOT6, SIG_DESC_SET(SCUA0, 6)); -SIG_EXPR_LIST_DECL_SINGLE(RMII2RCLKO, RMII2, RMII2_DESC, +SIG_EXPR_LIST_DECL_SINGLE(B2, GPIOT6, GPIOT6, SIG_DESC_SET(SCUA0, 6)); +SIG_EXPR_LIST_DECL_SINGLE(B2, RMII2RCLKO, RMII2, RMII2_DESC, SIG_DESC_SET(SCU48, 30)); -SIG_EXPR_LIST_DECL_SINGLE(RGMII2TXCK, RGMII2); -MS_PIN_DECL_(B2, SIG_EXPR_LIST_PTR(GPIOT6), SIG_EXPR_LIST_PTR(RMII2RCLKO), - SIG_EXPR_LIST_PTR(RGMII2TXCK)); +SIG_EXPR_LIST_DECL_SINGLE(B2, RGMII2TXCK, RGMII2); +PIN_DECL_(B2, SIG_EXPR_LIST_PTR(B2, GPIOT6), SIG_EXPR_LIST_PTR(B2, RMII2RCLKO), + SIG_EXPR_LIST_PTR(B2, RGMII2TXCK)); #define B1 159 -SIG_EXPR_LIST_DECL_SINGLE(GPIOT7, GPIOT7, SIG_DESC_SET(SCUA0, 7)); -SIG_EXPR_LIST_DECL_SINGLE(RMII2TXEN, RMII2, RMII2_DESC); -SIG_EXPR_LIST_DECL_SINGLE(RGMII2TXCTL, RGMII2); -MS_PIN_DECL_(B1, SIG_EXPR_LIST_PTR(GPIOT7), SIG_EXPR_LIST_PTR(RMII2TXEN), - SIG_EXPR_LIST_PTR(RGMII2TXCTL)); +SIG_EXPR_LIST_DECL_SINGLE(B1, GPIOT7, GPIOT7, SIG_DESC_SET(SCUA0, 7)); +SIG_EXPR_LIST_DECL_SINGLE(B1, RMII2TXEN, RMII2, RMII2_DESC); +SIG_EXPR_LIST_DECL_SINGLE(B1, RGMII2TXCTL, RGMII2); +PIN_DECL_(B1, SIG_EXPR_LIST_PTR(B1, GPIOT7), SIG_EXPR_LIST_PTR(B1, RMII2TXEN), + SIG_EXPR_LIST_PTR(B1, RGMII2TXCTL)); #define A2 160 -SIG_EXPR_LIST_DECL_SINGLE(GPIOU0, GPIOU0, SIG_DESC_SET(SCUA0, 8)); -SIG_EXPR_LIST_DECL_SINGLE(RMII2TXD0, RMII2, RMII2_DESC); -SIG_EXPR_LIST_DECL_SINGLE(RGMII2TXD0, RGMII2); -MS_PIN_DECL_(A2, SIG_EXPR_LIST_PTR(GPIOU0), SIG_EXPR_LIST_PTR(RMII2TXD0), - SIG_EXPR_LIST_PTR(RGMII2TXD0)); +SIG_EXPR_LIST_DECL_SINGLE(A2, GPIOU0, GPIOU0, SIG_DESC_SET(SCUA0, 8)); +SIG_EXPR_LIST_DECL_SINGLE(A2, RMII2TXD0, RMII2, RMII2_DESC); +SIG_EXPR_LIST_DECL_SINGLE(A2, RGMII2TXD0, RGMII2); +PIN_DECL_(A2, SIG_EXPR_LIST_PTR(A2, GPIOU0), SIG_EXPR_LIST_PTR(A2, RMII2TXD0), + SIG_EXPR_LIST_PTR(A2, RGMII2TXD0)); #define B3 161 -SIG_EXPR_LIST_DECL_SINGLE(GPIOU1, GPIOU1, SIG_DESC_SET(SCUA0, 9)); -SIG_EXPR_LIST_DECL_SINGLE(RMII2TXD1, RMII2, RMII2_DESC); -SIG_EXPR_LIST_DECL_SINGLE(RGMII2TXD1, RGMII2); -MS_PIN_DECL_(B3, SIG_EXPR_LIST_PTR(GPIOU1), SIG_EXPR_LIST_PTR(RMII2TXD1), - SIG_EXPR_LIST_PTR(RGMII2TXD1)); +SIG_EXPR_LIST_DECL_SINGLE(B3, GPIOU1, GPIOU1, SIG_DESC_SET(SCUA0, 9)); +SIG_EXPR_LIST_DECL_SINGLE(B3, RMII2TXD1, RMII2, RMII2_DESC); +SIG_EXPR_LIST_DECL_SINGLE(B3, RGMII2TXD1, RGMII2); +PIN_DECL_(B3, SIG_EXPR_LIST_PTR(B3, GPIOU1), SIG_EXPR_LIST_PTR(B3, RMII2TXD1), + SIG_EXPR_LIST_PTR(B3, RGMII2TXD1)); #define D5 162 -SIG_EXPR_LIST_DECL_SINGLE(GPIOU2, GPIOU2, SIG_DESC_SET(SCUA0, 10)); -SIG_EXPR_LIST_DECL_SINGLE(RMII2DASH0, RMII2, RMII2_DESC); -SIG_EXPR_LIST_DECL_SINGLE(RGMII2TXD2, RGMII2); -MS_PIN_DECL_(D5, SIG_EXPR_LIST_PTR(GPIOU2), SIG_EXPR_LIST_PTR(RMII2DASH0), - SIG_EXPR_LIST_PTR(RGMII2TXD2)); +SIG_EXPR_LIST_DECL_SINGLE(D5, GPIOU2, GPIOU2, SIG_DESC_SET(SCUA0, 10)); +SIG_EXPR_LIST_DECL_SINGLE(D5, RMII2DASH0, RMII2, RMII2_DESC); +SIG_EXPR_LIST_DECL_SINGLE(D5, RGMII2TXD2, RGMII2); +PIN_DECL_(D5, SIG_EXPR_LIST_PTR(D5, GPIOU2), SIG_EXPR_LIST_PTR(D5, RMII2DASH0), + SIG_EXPR_LIST_PTR(D5, RGMII2TXD2)); #define D4 163 -SIG_EXPR_LIST_DECL_SINGLE(GPIOU3, GPIOU3, SIG_DESC_SET(SCUA0, 11)); -SIG_EXPR_LIST_DECL_SINGLE(RMII2DASH1, RMII2, RMII2_DESC); -SIG_EXPR_LIST_DECL_SINGLE(RGMII2TXD3, RGMII2); -MS_PIN_DECL_(D4, SIG_EXPR_LIST_PTR(GPIOU3), SIG_EXPR_LIST_PTR(RMII2DASH1), - SIG_EXPR_LIST_PTR(RGMII2TXD3)); +SIG_EXPR_LIST_DECL_SINGLE(D4, GPIOU3, GPIOU3, SIG_DESC_SET(SCUA0, 11)); +SIG_EXPR_LIST_DECL_SINGLE(D4, RMII2DASH1, RMII2, RMII2_DESC); +SIG_EXPR_LIST_DECL_SINGLE(D4, RGMII2TXD3, RGMII2); +PIN_DECL_(D4, SIG_EXPR_LIST_PTR(D4, GPIOU3), SIG_EXPR_LIST_PTR(D4, RMII2DASH1), + SIG_EXPR_LIST_PTR(D4, RGMII2TXD3)); #define B4 164 -SIG_EXPR_LIST_DECL_SINGLE(GPIOU4, GPIOU4, SIG_DESC_SET(SCUA0, 12)); -SIG_EXPR_LIST_DECL_SINGLE(RMII1RCLKI, RMII1, RMII1_DESC); -SIG_EXPR_LIST_DECL_SINGLE(RGMII1RXCK, RGMII1); -MS_PIN_DECL_(B4, SIG_EXPR_LIST_PTR(GPIOU4), SIG_EXPR_LIST_PTR(RMII1RCLKI), - SIG_EXPR_LIST_PTR(RGMII1RXCK)); +SIG_EXPR_LIST_DECL_SINGLE(B4, GPIOU4, GPIOU4, SIG_DESC_SET(SCUA0, 12)); +SIG_EXPR_LIST_DECL_SINGLE(B4, RMII1RCLKI, RMII1, RMII1_DESC); +SIG_EXPR_LIST_DECL_SINGLE(B4, RGMII1RXCK, RGMII1); +PIN_DECL_(B4, SIG_EXPR_LIST_PTR(B4, GPIOU4), SIG_EXPR_LIST_PTR(B4, RMII1RCLKI), + SIG_EXPR_LIST_PTR(B4, RGMII1RXCK)); #define A4 165 -SIG_EXPR_LIST_DECL_SINGLE(GPIOU5, GPIOU5, SIG_DESC_SET(SCUA0, 13)); -SIG_EXPR_LIST_DECL_SINGLE(RMII1DASH2, RMII1, RMII1_DESC); -SIG_EXPR_LIST_DECL_SINGLE(RGMII1RXCTL, RGMII1); -MS_PIN_DECL_(A4, SIG_EXPR_LIST_PTR(GPIOU5), SIG_EXPR_LIST_PTR(RMII1DASH2), - SIG_EXPR_LIST_PTR(RGMII1RXCTL)); +SIG_EXPR_LIST_DECL_SINGLE(A4, GPIOU5, GPIOU5, SIG_DESC_SET(SCUA0, 13)); +SIG_EXPR_LIST_DECL_SINGLE(A4, RMII1DASH2, RMII1, RMII1_DESC); +SIG_EXPR_LIST_DECL_SINGLE(A4, RGMII1RXCTL, RGMII1); +PIN_DECL_(A4, SIG_EXPR_LIST_PTR(A4, GPIOU5), SIG_EXPR_LIST_PTR(A4, RMII1DASH2), + SIG_EXPR_LIST_PTR(A4, RGMII1RXCTL)); #define A3 166 -SIG_EXPR_LIST_DECL_SINGLE(GPIOU6, GPIOU6, SIG_DESC_SET(SCUA0, 14)); -SIG_EXPR_LIST_DECL_SINGLE(RMII1RXD0, RMII1, RMII1_DESC); -SIG_EXPR_LIST_DECL_SINGLE(RGMII1RXD0, RGMII1); -MS_PIN_DECL_(A3, SIG_EXPR_LIST_PTR(GPIOU6), SIG_EXPR_LIST_PTR(RMII1RXD0), - SIG_EXPR_LIST_PTR(RGMII1RXD0)); +SIG_EXPR_LIST_DECL_SINGLE(A3, GPIOU6, GPIOU6, SIG_DESC_SET(SCUA0, 14)); +SIG_EXPR_LIST_DECL_SINGLE(A3, RMII1RXD0, RMII1, RMII1_DESC); +SIG_EXPR_LIST_DECL_SINGLE(A3, RGMII1RXD0, RGMII1); +PIN_DECL_(A3, SIG_EXPR_LIST_PTR(A3, GPIOU6), SIG_EXPR_LIST_PTR(A3, RMII1RXD0), + SIG_EXPR_LIST_PTR(A3, RGMII1RXD0)); #define D6 167 -SIG_EXPR_LIST_DECL_SINGLE(GPIOU7, GPIOU7, SIG_DESC_SET(SCUA0, 15)); -SIG_EXPR_LIST_DECL_SINGLE(RMII1RXD1, RMII1, RMII1_DESC); -SIG_EXPR_LIST_DECL_SINGLE(RGMII1RXD1, RGMII1); -MS_PIN_DECL_(D6, SIG_EXPR_LIST_PTR(GPIOU7), SIG_EXPR_LIST_PTR(RMII1RXD1), - SIG_EXPR_LIST_PTR(RGMII1RXD1)); +SIG_EXPR_LIST_DECL_SINGLE(D6, GPIOU7, GPIOU7, SIG_DESC_SET(SCUA0, 15)); +SIG_EXPR_LIST_DECL_SINGLE(D6, RMII1RXD1, RMII1, RMII1_DESC); +SIG_EXPR_LIST_DECL_SINGLE(D6, RGMII1RXD1, RGMII1); +PIN_DECL_(D6, SIG_EXPR_LIST_PTR(D6, GPIOU7), SIG_EXPR_LIST_PTR(D6, RMII1RXD1), + SIG_EXPR_LIST_PTR(D6, RGMII1RXD1)); #define C5 168 -SIG_EXPR_LIST_DECL_SINGLE(GPIOV0, GPIOV0, SIG_DESC_SET(SCUA0, 16)); -SIG_EXPR_LIST_DECL_SINGLE(RMII1CRSDV, RMII1, RMII1_DESC); -SIG_EXPR_LIST_DECL_SINGLE(RGMII1RXD2, RGMII1); -MS_PIN_DECL_(C5, SIG_EXPR_LIST_PTR(GPIOV0), SIG_EXPR_LIST_PTR(RMII1CRSDV), - SIG_EXPR_LIST_PTR(RGMII1RXD2)); +SIG_EXPR_LIST_DECL_SINGLE(C5, GPIOV0, GPIOV0, SIG_DESC_SET(SCUA0, 16)); +SIG_EXPR_LIST_DECL_SINGLE(C5, RMII1CRSDV, RMII1, RMII1_DESC); +SIG_EXPR_LIST_DECL_SINGLE(C5, RGMII1RXD2, RGMII1); +PIN_DECL_(C5, SIG_EXPR_LIST_PTR(C5, GPIOV0), SIG_EXPR_LIST_PTR(C5, RMII1CRSDV), + SIG_EXPR_LIST_PTR(C5, RGMII1RXD2)); #define C4 169 -SIG_EXPR_LIST_DECL_SINGLE(GPIOV1, GPIOV1, SIG_DESC_SET(SCUA0, 17)); -SIG_EXPR_LIST_DECL_SINGLE(RMII1RXER, RMII1, RMII1_DESC); -SIG_EXPR_LIST_DECL_SINGLE(RGMII1RXD3, RGMII1); -MS_PIN_DECL_(C4, SIG_EXPR_LIST_PTR(GPIOV1), SIG_EXPR_LIST_PTR(RMII1RXER), - SIG_EXPR_LIST_PTR(RGMII1RXD3)); +SIG_EXPR_LIST_DECL_SINGLE(C4, GPIOV1, GPIOV1, SIG_DESC_SET(SCUA0, 17)); +SIG_EXPR_LIST_DECL_SINGLE(C4, RMII1RXER, RMII1, RMII1_DESC); +SIG_EXPR_LIST_DECL_SINGLE(C4, RGMII1RXD3, RGMII1); +PIN_DECL_(C4, SIG_EXPR_LIST_PTR(C4, GPIOV1), SIG_EXPR_LIST_PTR(C4, RMII1RXER), + SIG_EXPR_LIST_PTR(C4, RGMII1RXD3)); FUNC_GROUP_DECL(RGMII1, B4, A4, A3, D6, C5, C4, B5, E9, F9, A5, E7, D7); FUNC_GROUP_DECL(RMII1, B4, A3, D6, C5, C4, B5, E9, F9, A5); #define C2 170 -SIG_EXPR_LIST_DECL_SINGLE(GPIOV2, GPIOV2, SIG_DESC_SET(SCUA0, 18)); -SIG_EXPR_LIST_DECL_SINGLE(RMII2RCLKI, RMII2, RMII2_DESC); -SIG_EXPR_LIST_DECL_SINGLE(RGMII2RXCK, RGMII2); -MS_PIN_DECL_(C2, SIG_EXPR_LIST_PTR(GPIOV2), SIG_EXPR_LIST_PTR(RMII2RCLKI), - SIG_EXPR_LIST_PTR(RGMII2RXCK)); +SIG_EXPR_LIST_DECL_SINGLE(C2, GPIOV2, GPIOV2, SIG_DESC_SET(SCUA0, 18)); +SIG_EXPR_LIST_DECL_SINGLE(C2, RMII2RCLKI, RMII2, RMII2_DESC); +SIG_EXPR_LIST_DECL_SINGLE(C2, RGMII2RXCK, RGMII2); +PIN_DECL_(C2, SIG_EXPR_LIST_PTR(C2, GPIOV2), SIG_EXPR_LIST_PTR(C2, RMII2RCLKI), + SIG_EXPR_LIST_PTR(C2, RGMII2RXCK)); #define C1 171 -SIG_EXPR_LIST_DECL_SINGLE(GPIOV3, GPIOV3, SIG_DESC_SET(SCUA0, 19)); -SIG_EXPR_LIST_DECL_SINGLE(RMII2DASH2, RMII2, RMII2_DESC); -SIG_EXPR_LIST_DECL_SINGLE(RGMII2RXCTL, RGMII2); -MS_PIN_DECL_(C1, SIG_EXPR_LIST_PTR(GPIOV3), SIG_EXPR_LIST_PTR(RMII2DASH2), - SIG_EXPR_LIST_PTR(RGMII2RXCTL)); +SIG_EXPR_LIST_DECL_SINGLE(C1, GPIOV3, GPIOV3, SIG_DESC_SET(SCUA0, 19)); +SIG_EXPR_LIST_DECL_SINGLE(C1, RMII2DASH2, RMII2, RMII2_DESC); +SIG_EXPR_LIST_DECL_SINGLE(C1, RGMII2RXCTL, RGMII2); +PIN_DECL_(C1, SIG_EXPR_LIST_PTR(C1, GPIOV3), SIG_EXPR_LIST_PTR(C1, RMII2DASH2), + SIG_EXPR_LIST_PTR(C1, RGMII2RXCTL)); #define C3 172 -SIG_EXPR_LIST_DECL_SINGLE(GPIOV4, GPIOV4, SIG_DESC_SET(SCUA0, 20)); -SIG_EXPR_LIST_DECL_SINGLE(RMII2RXD0, RMII2, RMII2_DESC); -SIG_EXPR_LIST_DECL_SINGLE(RGMII2RXD0, RGMII2); -MS_PIN_DECL_(C3, SIG_EXPR_LIST_PTR(GPIOV4), SIG_EXPR_LIST_PTR(RMII2RXD0), - SIG_EXPR_LIST_PTR(RGMII2RXD0)); +SIG_EXPR_LIST_DECL_SINGLE(C3, GPIOV4, GPIOV4, SIG_DESC_SET(SCUA0, 20)); +SIG_EXPR_LIST_DECL_SINGLE(C3, RMII2RXD0, RMII2, RMII2_DESC); +SIG_EXPR_LIST_DECL_SINGLE(C3, RGMII2RXD0, RGMII2); +PIN_DECL_(C3, SIG_EXPR_LIST_PTR(C3, GPIOV4), SIG_EXPR_LIST_PTR(C3, RMII2RXD0), + SIG_EXPR_LIST_PTR(C3, RGMII2RXD0)); #define D1 173 -SIG_EXPR_LIST_DECL_SINGLE(GPIOV5, GPIOV5, SIG_DESC_SET(SCUA0, 21)); -SIG_EXPR_LIST_DECL_SINGLE(RMII2RXD1, RMII2, RMII2_DESC); -SIG_EXPR_LIST_DECL_SINGLE(RGMII2RXD1, RGMII2); -MS_PIN_DECL_(D1, SIG_EXPR_LIST_PTR(GPIOV5), SIG_EXPR_LIST_PTR(RMII2RXD1), - SIG_EXPR_LIST_PTR(RGMII2RXD1)); +SIG_EXPR_LIST_DECL_SINGLE(D1, GPIOV5, GPIOV5, SIG_DESC_SET(SCUA0, 21)); +SIG_EXPR_LIST_DECL_SINGLE(D1, RMII2RXD1, RMII2, RMII2_DESC); +SIG_EXPR_LIST_DECL_SINGLE(D1, RGMII2RXD1, RGMII2); +PIN_DECL_(D1, SIG_EXPR_LIST_PTR(D1, GPIOV5), SIG_EXPR_LIST_PTR(D1, RMII2RXD1), + SIG_EXPR_LIST_PTR(D1, RGMII2RXD1)); #define D2 174 -SIG_EXPR_LIST_DECL_SINGLE(GPIOV6, GPIOV6, SIG_DESC_SET(SCUA0, 22)); -SIG_EXPR_LIST_DECL_SINGLE(RMII2CRSDV, RMII2, RMII2_DESC); -SIG_EXPR_LIST_DECL_SINGLE(RGMII2RXD2, RGMII2); -MS_PIN_DECL_(D2, SIG_EXPR_LIST_PTR(GPIOV6), SIG_EXPR_LIST_PTR(RMII2CRSDV), - SIG_EXPR_LIST_PTR(RGMII2RXD2)); +SIG_EXPR_LIST_DECL_SINGLE(D2, GPIOV6, GPIOV6, SIG_DESC_SET(SCUA0, 22)); +SIG_EXPR_LIST_DECL_SINGLE(D2, RMII2CRSDV, RMII2, RMII2_DESC); +SIG_EXPR_LIST_DECL_SINGLE(D2, RGMII2RXD2, RGMII2); +PIN_DECL_(D2, SIG_EXPR_LIST_PTR(D2, GPIOV6), SIG_EXPR_LIST_PTR(D2, RMII2CRSDV), + SIG_EXPR_LIST_PTR(D2, RGMII2RXD2)); #define E6 175 -SIG_EXPR_LIST_DECL_SINGLE(GPIOV7, GPIOV7, SIG_DESC_SET(SCUA0, 23)); -SIG_EXPR_LIST_DECL_SINGLE(RMII2RXER, RMII2, RMII2_DESC); -SIG_EXPR_LIST_DECL_SINGLE(RGMII2RXD3, RGMII2); -MS_PIN_DECL_(E6, SIG_EXPR_LIST_PTR(GPIOV7), SIG_EXPR_LIST_PTR(RMII2RXER), - SIG_EXPR_LIST_PTR(RGMII2RXD3)); +SIG_EXPR_LIST_DECL_SINGLE(E6, GPIOV7, GPIOV7, SIG_DESC_SET(SCUA0, 23)); +SIG_EXPR_LIST_DECL_SINGLE(E6, RMII2RXER, RMII2, RMII2_DESC); +SIG_EXPR_LIST_DECL_SINGLE(E6, RGMII2RXD3, RGMII2); +PIN_DECL_(E6, SIG_EXPR_LIST_PTR(E6, GPIOV7), SIG_EXPR_LIST_PTR(E6, RMII2RXER), + SIG_EXPR_LIST_PTR(E6, RGMII2RXD3)); FUNC_GROUP_DECL(RGMII2, B2, B1, A2, B3, D5, D4, C2, C1, C3, D1, D2, E6); FUNC_GROUP_DECL(RMII2, B2, B1, A2, B3, C2, C3, D1, D2, E6); #define F4 176 -SIG_EXPR_LIST_DECL_SINGLE(GPIOW0, GPIOW0, SIG_DESC_SET(SCUA0, 24)); -SIG_EXPR_LIST_DECL_SINGLE(ADC0, ADC0); -MS_PIN_DECL_(F4, SIG_EXPR_LIST_PTR(GPIOW0), SIG_EXPR_LIST_PTR(ADC0)); +SIG_EXPR_LIST_DECL_SINGLE(F4, GPIOW0, GPIOW0, SIG_DESC_SET(SCUA0, 24)); +SIG_EXPR_LIST_DECL_SINGLE(F4, ADC0, ADC0); +PIN_DECL_(F4, SIG_EXPR_LIST_PTR(F4, GPIOW0), SIG_EXPR_LIST_PTR(F4, ADC0)); FUNC_GROUP_DECL(ADC0, F4); #define F5 177 -SIG_EXPR_LIST_DECL_SINGLE(GPIOW1, GPIOW1, SIG_DESC_SET(SCUA0, 25)); -SIG_EXPR_LIST_DECL_SINGLE(ADC1, ADC1); -MS_PIN_DECL_(F5, SIG_EXPR_LIST_PTR(GPIOW1), SIG_EXPR_LIST_PTR(ADC1)); +SIG_EXPR_LIST_DECL_SINGLE(F5, GPIOW1, GPIOW1, SIG_DESC_SET(SCUA0, 25)); +SIG_EXPR_LIST_DECL_SINGLE(F5, ADC1, ADC1); +PIN_DECL_(F5, SIG_EXPR_LIST_PTR(F5, GPIOW1), SIG_EXPR_LIST_PTR(F5, ADC1)); FUNC_GROUP_DECL(ADC1, F5); #define E2 178 -SIG_EXPR_LIST_DECL_SINGLE(GPIOW2, GPIOW2, SIG_DESC_SET(SCUA0, 26)); -SIG_EXPR_LIST_DECL_SINGLE(ADC2, ADC2); -MS_PIN_DECL_(E2, SIG_EXPR_LIST_PTR(GPIOW2), SIG_EXPR_LIST_PTR(ADC2)); +SIG_EXPR_LIST_DECL_SINGLE(E2, GPIOW2, GPIOW2, SIG_DESC_SET(SCUA0, 26)); +SIG_EXPR_LIST_DECL_SINGLE(E2, ADC2, ADC2); +PIN_DECL_(E2, SIG_EXPR_LIST_PTR(E2, GPIOW2), SIG_EXPR_LIST_PTR(E2, ADC2)); FUNC_GROUP_DECL(ADC2, E2); #define E1 179 -SIG_EXPR_LIST_DECL_SINGLE(GPIOW3, GPIOW3, SIG_DESC_SET(SCUA0, 27)); -SIG_EXPR_LIST_DECL_SINGLE(ADC3, ADC3); -MS_PIN_DECL_(E1, SIG_EXPR_LIST_PTR(GPIOW3), SIG_EXPR_LIST_PTR(ADC3)); +SIG_EXPR_LIST_DECL_SINGLE(E1, GPIOW3, GPIOW3, SIG_DESC_SET(SCUA0, 27)); +SIG_EXPR_LIST_DECL_SINGLE(E1, ADC3, ADC3); +PIN_DECL_(E1, SIG_EXPR_LIST_PTR(E1, GPIOW3), SIG_EXPR_LIST_PTR(E1, ADC3)); FUNC_GROUP_DECL(ADC3, E1); #define F3 180 -SIG_EXPR_LIST_DECL_SINGLE(GPIOW4, GPIOW4, SIG_DESC_SET(SCUA0, 28)); -SIG_EXPR_LIST_DECL_SINGLE(ADC4, ADC4); -MS_PIN_DECL_(F3, SIG_EXPR_LIST_PTR(GPIOW4), SIG_EXPR_LIST_PTR(ADC4)); +SIG_EXPR_LIST_DECL_SINGLE(F3, GPIOW4, GPIOW4, SIG_DESC_SET(SCUA0, 28)); +SIG_EXPR_LIST_DECL_SINGLE(F3, ADC4, ADC4); +PIN_DECL_(F3, SIG_EXPR_LIST_PTR(F3, GPIOW4), SIG_EXPR_LIST_PTR(F3, ADC4)); FUNC_GROUP_DECL(ADC4, F3); #define E3 181 -SIG_EXPR_LIST_DECL_SINGLE(GPIOW5, GPIOW5, SIG_DESC_SET(SCUA0, 29)); -SIG_EXPR_LIST_DECL_SINGLE(ADC5, ADC5); -MS_PIN_DECL_(E3, SIG_EXPR_LIST_PTR(GPIOW5), SIG_EXPR_LIST_PTR(ADC5)); +SIG_EXPR_LIST_DECL_SINGLE(E3, GPIOW5, GPIOW5, SIG_DESC_SET(SCUA0, 29)); +SIG_EXPR_LIST_DECL_SINGLE(E3, ADC5, ADC5); +PIN_DECL_(E3, SIG_EXPR_LIST_PTR(E3, GPIOW5), SIG_EXPR_LIST_PTR(E3, ADC5)); FUNC_GROUP_DECL(ADC5, E3); #define G5 182 -SIG_EXPR_LIST_DECL_SINGLE(GPIOW6, GPIOW6, SIG_DESC_SET(SCUA0, 30)); -SIG_EXPR_LIST_DECL_SINGLE(ADC6, ADC6); -MS_PIN_DECL_(G5, SIG_EXPR_LIST_PTR(GPIOW6), SIG_EXPR_LIST_PTR(ADC6)); +SIG_EXPR_LIST_DECL_SINGLE(G5, GPIOW6, GPIOW6, SIG_DESC_SET(SCUA0, 30)); +SIG_EXPR_LIST_DECL_SINGLE(G5, ADC6, ADC6); +PIN_DECL_(G5, SIG_EXPR_LIST_PTR(G5, GPIOW6), SIG_EXPR_LIST_PTR(G5, ADC6)); FUNC_GROUP_DECL(ADC6, G5); #define G4 183 -SIG_EXPR_LIST_DECL_SINGLE(GPIOW7, GPIOW7, SIG_DESC_SET(SCUA0, 31)); -SIG_EXPR_LIST_DECL_SINGLE(ADC7, ADC7); -MS_PIN_DECL_(G4, SIG_EXPR_LIST_PTR(GPIOW7), SIG_EXPR_LIST_PTR(ADC7)); +SIG_EXPR_LIST_DECL_SINGLE(G4, GPIOW7, GPIOW7, SIG_DESC_SET(SCUA0, 31)); +SIG_EXPR_LIST_DECL_SINGLE(G4, ADC7, ADC7); +PIN_DECL_(G4, SIG_EXPR_LIST_PTR(G4, GPIOW7), SIG_EXPR_LIST_PTR(G4, ADC7)); FUNC_GROUP_DECL(ADC7, G4); #define F2 184 -SIG_EXPR_LIST_DECL_SINGLE(GPIOX0, GPIOX0, SIG_DESC_SET(SCUA4, 0)); -SIG_EXPR_LIST_DECL_SINGLE(ADC8, ADC8); -MS_PIN_DECL_(F2, SIG_EXPR_LIST_PTR(GPIOX0), SIG_EXPR_LIST_PTR(ADC8)); +SIG_EXPR_LIST_DECL_SINGLE(F2, GPIOX0, GPIOX0, SIG_DESC_SET(SCUA4, 0)); +SIG_EXPR_LIST_DECL_SINGLE(F2, ADC8, ADC8); +PIN_DECL_(F2, SIG_EXPR_LIST_PTR(F2, GPIOX0), SIG_EXPR_LIST_PTR(F2, ADC8)); FUNC_GROUP_DECL(ADC8, F2); #define G3 185 -SIG_EXPR_LIST_DECL_SINGLE(GPIOX1, GPIOX1, SIG_DESC_SET(SCUA4, 1)); -SIG_EXPR_LIST_DECL_SINGLE(ADC9, ADC9); -MS_PIN_DECL_(G3, SIG_EXPR_LIST_PTR(GPIOX1), SIG_EXPR_LIST_PTR(ADC9)); +SIG_EXPR_LIST_DECL_SINGLE(G3, GPIOX1, GPIOX1, SIG_DESC_SET(SCUA4, 1)); +SIG_EXPR_LIST_DECL_SINGLE(G3, ADC9, ADC9); +PIN_DECL_(G3, SIG_EXPR_LIST_PTR(G3, GPIOX1), SIG_EXPR_LIST_PTR(G3, ADC9)); FUNC_GROUP_DECL(ADC9, G3); #define G2 186 -SIG_EXPR_LIST_DECL_SINGLE(GPIOX2, GPIOX2, SIG_DESC_SET(SCUA4, 2)); -SIG_EXPR_LIST_DECL_SINGLE(ADC10, ADC10); -MS_PIN_DECL_(G2, SIG_EXPR_LIST_PTR(GPIOX2), SIG_EXPR_LIST_PTR(ADC10)); +SIG_EXPR_LIST_DECL_SINGLE(G2, GPIOX2, GPIOX2, SIG_DESC_SET(SCUA4, 2)); +SIG_EXPR_LIST_DECL_SINGLE(G2, ADC10, ADC10); +PIN_DECL_(G2, SIG_EXPR_LIST_PTR(G2, GPIOX2), SIG_EXPR_LIST_PTR(G2, ADC10)); FUNC_GROUP_DECL(ADC10, G2); #define F1 187 -SIG_EXPR_LIST_DECL_SINGLE(GPIOX3, GPIOX3, SIG_DESC_SET(SCUA4, 3)); -SIG_EXPR_LIST_DECL_SINGLE(ADC11, ADC11); -MS_PIN_DECL_(F1, SIG_EXPR_LIST_PTR(GPIOX3), SIG_EXPR_LIST_PTR(ADC11)); +SIG_EXPR_LIST_DECL_SINGLE(F1, GPIOX3, GPIOX3, SIG_DESC_SET(SCUA4, 3)); +SIG_EXPR_LIST_DECL_SINGLE(F1, ADC11, ADC11); +PIN_DECL_(F1, SIG_EXPR_LIST_PTR(F1, GPIOX3), SIG_EXPR_LIST_PTR(F1, ADC11)); FUNC_GROUP_DECL(ADC11, F1); #define H5 188 -SIG_EXPR_LIST_DECL_SINGLE(GPIOX4, GPIOX4, SIG_DESC_SET(SCUA4, 4)); -SIG_EXPR_LIST_DECL_SINGLE(ADC12, ADC12); -MS_PIN_DECL_(H5, SIG_EXPR_LIST_PTR(GPIOX4), SIG_EXPR_LIST_PTR(ADC12)); +SIG_EXPR_LIST_DECL_SINGLE(H5, GPIOX4, GPIOX4, SIG_DESC_SET(SCUA4, 4)); +SIG_EXPR_LIST_DECL_SINGLE(H5, ADC12, ADC12); +PIN_DECL_(H5, SIG_EXPR_LIST_PTR(H5, GPIOX4), SIG_EXPR_LIST_PTR(H5, ADC12)); FUNC_GROUP_DECL(ADC12, H5); #define G1 189 -SIG_EXPR_LIST_DECL_SINGLE(GPIOX5, GPIOX5, SIG_DESC_SET(SCUA4, 5)); -SIG_EXPR_LIST_DECL_SINGLE(ADC13, ADC13); -MS_PIN_DECL_(G1, SIG_EXPR_LIST_PTR(GPIOX5), SIG_EXPR_LIST_PTR(ADC13)); +SIG_EXPR_LIST_DECL_SINGLE(G1, GPIOX5, GPIOX5, SIG_DESC_SET(SCUA4, 5)); +SIG_EXPR_LIST_DECL_SINGLE(G1, ADC13, ADC13); +PIN_DECL_(G1, SIG_EXPR_LIST_PTR(G1, GPIOX5), SIG_EXPR_LIST_PTR(G1, ADC13)); FUNC_GROUP_DECL(ADC13, G1); #define H3 190 -SIG_EXPR_LIST_DECL_SINGLE(GPIOX6, GPIOX6, SIG_DESC_SET(SCUA4, 6)); -SIG_EXPR_LIST_DECL_SINGLE(ADC14, ADC14); -MS_PIN_DECL_(H3, SIG_EXPR_LIST_PTR(GPIOX6), SIG_EXPR_LIST_PTR(ADC14)); +SIG_EXPR_LIST_DECL_SINGLE(H3, GPIOX6, GPIOX6, SIG_DESC_SET(SCUA4, 6)); +SIG_EXPR_LIST_DECL_SINGLE(H3, ADC14, ADC14); +PIN_DECL_(H3, SIG_EXPR_LIST_PTR(H3, GPIOX6), SIG_EXPR_LIST_PTR(H3, ADC14)); FUNC_GROUP_DECL(ADC14, H3); #define H4 191 -SIG_EXPR_LIST_DECL_SINGLE(GPIOX7, GPIOX7, SIG_DESC_SET(SCUA4, 7)); -SIG_EXPR_LIST_DECL_SINGLE(ADC15, ADC15); -MS_PIN_DECL_(H4, SIG_EXPR_LIST_PTR(GPIOX7), SIG_EXPR_LIST_PTR(ADC15)); +SIG_EXPR_LIST_DECL_SINGLE(H4, GPIOX7, GPIOX7, SIG_DESC_SET(SCUA4, 7)); +SIG_EXPR_LIST_DECL_SINGLE(H4, ADC15, ADC15); +PIN_DECL_(H4, SIG_EXPR_LIST_PTR(H4, GPIOX7), SIG_EXPR_LIST_PTR(H4, ADC15)); FUNC_GROUP_DECL(ADC15, H4); #define ACPI_DESC SIG_DESC_SET(HW_STRAP1, 19) #define R22 192 -SIG_EXPR_DECL(SIOS3, SIOS3, SIG_DESC_SET(SCUA4, 8)); -SIG_EXPR_DECL(SIOS3, ACPI, ACPI_DESC); -SIG_EXPR_LIST_DECL_DUAL(SIOS3, SIOS3, ACPI); -SIG_EXPR_LIST_DECL_SINGLE(DASHR22, DASHR22, SIG_DESC_SET(SCU94, 10)); -MS_PIN_DECL(R22, GPIOY0, SIOS3, DASHR22); +SIG_EXPR_DECL_SINGLE(SIOS3, SIOS3, SIG_DESC_SET(SCUA4, 8)); +SIG_EXPR_DECL_SINGLE(SIOS3, ACPI, ACPI_DESC); +SIG_EXPR_LIST_DECL_DUAL(R22, SIOS3, SIOS3, ACPI); +SIG_EXPR_LIST_DECL_SINGLE(R22, DASHR22, DASHR22, SIG_DESC_SET(SCU94, 10)); +PIN_DECL_2(R22, GPIOY0, SIOS3, DASHR22); FUNC_GROUP_DECL(SIOS3, R22); #define R21 193 -SIG_EXPR_DECL(SIOS5, SIOS5, SIG_DESC_SET(SCUA4, 9)); -SIG_EXPR_DECL(SIOS5, ACPI, ACPI_DESC); -SIG_EXPR_LIST_DECL_DUAL(SIOS5, SIOS5, ACPI); -SIG_EXPR_LIST_DECL_SINGLE(DASHR21, DASHR21, SIG_DESC_SET(SCU94, 10)); -MS_PIN_DECL(R21, GPIOY1, SIOS5, DASHR21); +SIG_EXPR_DECL_SINGLE(SIOS5, SIOS5, SIG_DESC_SET(SCUA4, 9)); +SIG_EXPR_DECL_SINGLE(SIOS5, ACPI, ACPI_DESC); +SIG_EXPR_LIST_DECL_DUAL(R21, SIOS5, SIOS5, ACPI); +SIG_EXPR_LIST_DECL_SINGLE(R21, DASHR21, DASHR21, SIG_DESC_SET(SCU94, 10)); +PIN_DECL_2(R21, GPIOY1, SIOS5, DASHR21); FUNC_GROUP_DECL(SIOS5, R21); #define P22 194 -SIG_EXPR_DECL(SIOPWREQ, SIOPWREQ, SIG_DESC_SET(SCUA4, 10)); -SIG_EXPR_DECL(SIOPWREQ, ACPI, ACPI_DESC); -SIG_EXPR_LIST_DECL_DUAL(SIOPWREQ, SIOPWREQ, ACPI); -SIG_EXPR_LIST_DECL_SINGLE(DASHP22, DASHP22, SIG_DESC_SET(SCU94, 11)); -MS_PIN_DECL(P22, GPIOY2, SIOPWREQ, DASHP22); +SIG_EXPR_DECL_SINGLE(SIOPWREQ, SIOPWREQ, SIG_DESC_SET(SCUA4, 10)); +SIG_EXPR_DECL_SINGLE(SIOPWREQ, ACPI, ACPI_DESC); +SIG_EXPR_LIST_DECL_DUAL(P22, SIOPWREQ, SIOPWREQ, ACPI); +SIG_EXPR_LIST_DECL_SINGLE(P22, DASHP22, DASHP22, SIG_DESC_SET(SCU94, 11)); +PIN_DECL_2(P22, GPIOY2, SIOPWREQ, DASHP22); FUNC_GROUP_DECL(SIOPWREQ, P22); #define P21 195 -SIG_EXPR_DECL(SIOONCTRL, SIOONCTRL, SIG_DESC_SET(SCUA4, 11)); -SIG_EXPR_DECL(SIOONCTRL, ACPI, ACPI_DESC); -SIG_EXPR_LIST_DECL_DUAL(SIOONCTRL, SIOONCTRL, ACPI); -SIG_EXPR_LIST_DECL_SINGLE(DASHP21, DASHP21, SIG_DESC_SET(SCU94, 11)); -MS_PIN_DECL(P21, GPIOY3, SIOONCTRL, DASHP21); +SIG_EXPR_DECL_SINGLE(SIOONCTRL, SIOONCTRL, SIG_DESC_SET(SCUA4, 11)); +SIG_EXPR_DECL_SINGLE(SIOONCTRL, ACPI, ACPI_DESC); +SIG_EXPR_LIST_DECL_DUAL(P21, SIOONCTRL, SIOONCTRL, ACPI); +SIG_EXPR_LIST_DECL_SINGLE(P21, DASHP21, DASHP21, SIG_DESC_SET(SCU94, 11)); +PIN_DECL_2(P21, GPIOY3, SIOONCTRL, DASHP21); FUNC_GROUP_DECL(SIOONCTRL, P21); #define M18 196 @@ -1419,66 +1458,81 @@ SSSF_PIN_DECL(P20, GPIOY7, SDA2, SIG_DESC_SET(SCUA4, 15)); #define Y20 200 #define Y20_DESC SIG_DESC_SET(SCUA4, 16) -SIG_EXPR_DECL(VPOG2, VPO, Y20_DESC, VPO_DESC, CRT_DVO_EN_DESC); -SIG_EXPR_DECL(VPOG2, VPOOFF1, Y20_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC); -SIG_EXPR_DECL(VPOG2, VPOOFF2, Y20_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC); -SIG_EXPR_LIST_DECL(VPOG2, SIG_EXPR_PTR(VPOG2, VPO), - SIG_EXPR_PTR(VPOG2, VPOOFF1), SIG_EXPR_PTR(VPOG2, VPOOFF2)); -SIG_EXPR_DECL(SIOPBI, SIOPBI, Y20_DESC); -SIG_EXPR_DECL(SIOPBI, ACPI, Y20_DESC); -SIG_EXPR_LIST_DECL_DUAL(SIOPBI, SIOPBI, ACPI); -SIG_EXPR_LIST_DECL_SINGLE(NORA0, PNOR, PNOR_DESC); -SIG_EXPR_LIST_DECL_SINGLE(GPIOZ0, GPIOZ0); -MS_PIN_DECL_(Y20, SIG_EXPR_LIST_PTR(VPOG2), SIG_EXPR_LIST_PTR(SIOPBI), - SIG_EXPR_LIST_PTR(NORA0), SIG_EXPR_LIST_PTR(GPIOZ0)); +SIG_EXPR_DECL_SINGLE(VPOG2, VPO, Y20_DESC, VPO_DESC, CRT_DVO_EN_DESC); +SIG_EXPR_DECL_SINGLE(VPOG2, VPOOFF1, Y20_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC); +SIG_EXPR_DECL_SINGLE(VPOG2, VPOOFF2, Y20_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC); +SIG_EXPR_LIST_DECL(VPOG2, VPO, + SIG_EXPR_PTR(VPOG2, VPO), + SIG_EXPR_PTR(VPOG2, VPOOFF1), + SIG_EXPR_PTR(VPOG2, VPOOFF2)); +SIG_EXPR_LIST_ALIAS(Y20, VPOG2, VPO); +SIG_EXPR_DECL_SINGLE(SIOPBI, SIOPBI, Y20_DESC); +SIG_EXPR_DECL_SINGLE(SIOPBI, ACPI, Y20_DESC); +SIG_EXPR_LIST_DECL_DUAL(Y20, SIOPBI, SIOPBI, ACPI); +SIG_EXPR_LIST_DECL_SINGLE(Y20, NORA0, PNOR, PNOR_DESC); +SIG_EXPR_LIST_DECL_SINGLE(Y20, GPIOZ0, GPIOZ0); +PIN_DECL_(Y20, SIG_EXPR_LIST_PTR(Y20, VPOG2), SIG_EXPR_LIST_PTR(Y20, SIOPBI), + SIG_EXPR_LIST_PTR(Y20, NORA0), SIG_EXPR_LIST_PTR(Y20, GPIOZ0)); FUNC_GROUP_DECL(SIOPBI, Y20); #define AB20 201 #define AB20_DESC SIG_DESC_SET(SCUA4, 17) -SIG_EXPR_DECL(VPOG3, VPO, AB20_DESC, VPO_DESC, CRT_DVO_EN_DESC); -SIG_EXPR_DECL(VPOG3, VPOOFF1, AB20_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC); -SIG_EXPR_DECL(VPOG3, VPOOFF2, AB20_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC); -SIG_EXPR_LIST_DECL(VPOG3, SIG_EXPR_PTR(VPOG3, VPO), - SIG_EXPR_PTR(VPOG3, VPOOFF1), SIG_EXPR_PTR(VPOG3, VPOOFF2)); -SIG_EXPR_DECL(SIOPWRGD, SIOPWRGD, AB20_DESC); -SIG_EXPR_DECL(SIOPWRGD, ACPI, AB20_DESC); -SIG_EXPR_LIST_DECL_DUAL(SIOPWRGD, SIOPWRGD, ACPI); -SIG_EXPR_LIST_DECL_SINGLE(NORA1, PNOR, PNOR_DESC); -SIG_EXPR_LIST_DECL_SINGLE(GPIOZ1, GPIOZ1); -MS_PIN_DECL_(AB20, SIG_EXPR_LIST_PTR(VPOG3), SIG_EXPR_LIST_PTR(SIOPWRGD), - SIG_EXPR_LIST_PTR(NORA1), SIG_EXPR_LIST_PTR(GPIOZ1)); +SIG_EXPR_DECL_SINGLE(VPOG3, VPO, AB20_DESC, VPO_DESC, CRT_DVO_EN_DESC); +SIG_EXPR_DECL_SINGLE(VPOG3, VPOOFF1, AB20_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC); +SIG_EXPR_DECL_SINGLE(VPOG3, VPOOFF2, AB20_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC); +SIG_EXPR_LIST_DECL(VPOG3, VPO, + SIG_EXPR_PTR(VPOG3, VPO), + SIG_EXPR_PTR(VPOG3, VPOOFF1), + SIG_EXPR_PTR(VPOG3, VPOOFF2)); +SIG_EXPR_LIST_ALIAS(AB20, VPOG3, VPO); +SIG_EXPR_DECL_SINGLE(SIOPWRGD, SIOPWRGD, AB20_DESC); +SIG_EXPR_DECL_SINGLE(SIOPWRGD, ACPI, AB20_DESC); +SIG_EXPR_LIST_DECL_DUAL(AB20, SIOPWRGD, SIOPWRGD, ACPI); +SIG_EXPR_LIST_DECL_SINGLE(AB20, NORA1, PNOR, PNOR_DESC); +SIG_EXPR_LIST_DECL_SINGLE(AB20, GPIOZ1, GPIOZ1); +PIN_DECL_(AB20, SIG_EXPR_LIST_PTR(AB20, VPOG3), + SIG_EXPR_LIST_PTR(AB20, SIOPWRGD), SIG_EXPR_LIST_PTR(AB20, NORA1), + SIG_EXPR_LIST_PTR(AB20, GPIOZ1)); FUNC_GROUP_DECL(SIOPWRGD, AB20); #define AB21 202 #define AB21_DESC SIG_DESC_SET(SCUA4, 18) -SIG_EXPR_DECL(VPOG4, VPO, AB21_DESC, VPO_DESC, CRT_DVO_EN_DESC); -SIG_EXPR_DECL(VPOG4, VPOOFF1, AB21_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC); -SIG_EXPR_DECL(VPOG4, VPOOFF2, AB21_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC); -SIG_EXPR_LIST_DECL(VPOG4, SIG_EXPR_PTR(VPOG4, VPO), - SIG_EXPR_PTR(VPOG4, VPOOFF1), SIG_EXPR_PTR(VPOG4, VPOOFF2)); -SIG_EXPR_DECL(SIOPBO, SIOPBO, AB21_DESC); -SIG_EXPR_DECL(SIOPBO, ACPI, AB21_DESC); -SIG_EXPR_LIST_DECL_DUAL(SIOPBO, SIOPBO, ACPI); -SIG_EXPR_LIST_DECL_SINGLE(NORA2, PNOR, PNOR_DESC); -SIG_EXPR_LIST_DECL_SINGLE(GPIOZ2, GPIOZ2); -MS_PIN_DECL_(AB21, SIG_EXPR_LIST_PTR(VPOG4), SIG_EXPR_LIST_PTR(SIOPBO), - SIG_EXPR_LIST_PTR(NORA2), SIG_EXPR_LIST_PTR(GPIOZ2)); +SIG_EXPR_DECL_SINGLE(VPOG4, VPO, AB21_DESC, VPO_DESC, CRT_DVO_EN_DESC); +SIG_EXPR_DECL_SINGLE(VPOG4, VPOOFF1, AB21_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC); +SIG_EXPR_DECL_SINGLE(VPOG4, VPOOFF2, AB21_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC); +SIG_EXPR_LIST_DECL(VPOG4, VPO, + SIG_EXPR_PTR(VPOG4, VPO), + SIG_EXPR_PTR(VPOG4, VPOOFF1), + SIG_EXPR_PTR(VPOG4, VPOOFF2)); +SIG_EXPR_LIST_ALIAS(AB21, VPOG4, VPO); +SIG_EXPR_DECL_SINGLE(SIOPBO, SIOPBO, AB21_DESC); +SIG_EXPR_DECL_SINGLE(SIOPBO, ACPI, AB21_DESC); +SIG_EXPR_LIST_DECL_DUAL(AB21, SIOPBO, SIOPBO, ACPI); +SIG_EXPR_LIST_DECL_SINGLE(AB21, NORA2, PNOR, PNOR_DESC); +SIG_EXPR_LIST_DECL_SINGLE(AB21, GPIOZ2, GPIOZ2); +PIN_DECL_(AB21, SIG_EXPR_LIST_PTR(AB21, VPOG4), + SIG_EXPR_LIST_PTR(AB21, SIOPBO), SIG_EXPR_LIST_PTR(AB21, NORA2), + SIG_EXPR_LIST_PTR(AB21, GPIOZ2)); FUNC_GROUP_DECL(SIOPBO, AB21); #define AA21 203 #define AA21_DESC SIG_DESC_SET(SCUA4, 19) -SIG_EXPR_DECL(VPOG5, VPO, AA21_DESC, VPO_DESC, CRT_DVO_EN_DESC); -SIG_EXPR_DECL(VPOG5, VPOOFF1, AA21_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC); -SIG_EXPR_DECL(VPOG5, VPOOFF2, AA21_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC); -SIG_EXPR_LIST_DECL(VPOG5, SIG_EXPR_PTR(VPOG5, VPO), - SIG_EXPR_PTR(VPOG5, VPOOFF1), SIG_EXPR_PTR(VPOG5, VPOOFF2)); -SIG_EXPR_DECL(SIOSCI, SIOSCI, AA21_DESC); -SIG_EXPR_DECL(SIOSCI, ACPI, AA21_DESC); -SIG_EXPR_LIST_DECL_DUAL(SIOSCI, SIOSCI, ACPI); -SIG_EXPR_LIST_DECL_SINGLE(NORA3, PNOR, PNOR_DESC); -SIG_EXPR_LIST_DECL_SINGLE(GPIOZ3, GPIOZ3); -MS_PIN_DECL_(AA21, SIG_EXPR_LIST_PTR(VPOG5), SIG_EXPR_LIST_PTR(SIOSCI), - SIG_EXPR_LIST_PTR(NORA3), SIG_EXPR_LIST_PTR(GPIOZ3)); +SIG_EXPR_DECL_SINGLE(VPOG5, VPO, AA21_DESC, VPO_DESC, CRT_DVO_EN_DESC); +SIG_EXPR_DECL_SINGLE(VPOG5, VPOOFF1, AA21_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC); +SIG_EXPR_DECL_SINGLE(VPOG5, VPOOFF2, AA21_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC); +SIG_EXPR_LIST_DECL(VPOG5, VPO, + SIG_EXPR_PTR(VPOG5, VPO), + SIG_EXPR_PTR(VPOG5, VPOOFF1), + SIG_EXPR_PTR(VPOG5, VPOOFF2)); +SIG_EXPR_LIST_ALIAS(AA21, VPOG5, VPO); +SIG_EXPR_DECL_SINGLE(SIOSCI, SIOSCI, AA21_DESC); +SIG_EXPR_DECL_SINGLE(SIOSCI, ACPI, AA21_DESC); +SIG_EXPR_LIST_DECL_DUAL(AA21, SIOSCI, SIOSCI, ACPI); +SIG_EXPR_LIST_DECL_SINGLE(AA21, NORA3, PNOR, PNOR_DESC); +SIG_EXPR_LIST_DECL_SINGLE(AA21, GPIOZ3, GPIOZ3); +PIN_DECL_(AA21, SIG_EXPR_LIST_PTR(AA21, VPOG5), + SIG_EXPR_LIST_PTR(AA21, SIOSCI), SIG_EXPR_LIST_PTR(AA21, NORA3), + SIG_EXPR_LIST_PTR(AA21, GPIOZ3)); FUNC_GROUP_DECL(SIOSCI, AA21); FUNC_GROUP_DECL(ACPI, R22, R21, P22, P21, Y20, AB20, AB21, AA21); @@ -1497,199 +1551,248 @@ FUNC_GROUP_DECL(ACPI, R22, R21, P22, P21, Y20, AB20, AB21, AA21); #define U21 204 #define U21_DESC SIG_DESC_SET(SCUA4, 20) -SIG_EXPR_DECL(VPOG6, VPO, U21_DESC, VPO_DESC, CRT_DVO_ES_DESC); -SIG_EXPR_DECL(VPOG6, VPOOFF1, U21_DESC, VPOOFF1_DESC, CRT_DVO_ES_DESC); -SIG_EXPR_DECL(VPOG6, VPOOFF2, U21_DESC, VPOOFF2_DESC, CRT_DVO_ES_DESC); -SIG_EXPR_LIST_DECL(VPOG6, SIG_EXPR_PTR(VPOG6, VPO), - SIG_EXPR_PTR(VPOG6, VPOOFF1), SIG_EXPR_PTR(VPOG6, VPOOFF2)); -SIG_EXPR_LIST_DECL_SINGLE(NORA4, PNOR, PNOR_DESC); -MS_PIN_DECL(U21, GPIOZ4, VPOG6, NORA4); +SIG_EXPR_DECL_SINGLE(VPOG6, VPO, U21_DESC, VPO_DESC, CRT_DVO_ES_DESC); +SIG_EXPR_DECL_SINGLE(VPOG6, VPOOFF1, U21_DESC, VPOOFF1_DESC, CRT_DVO_ES_DESC); +SIG_EXPR_DECL_SINGLE(VPOG6, VPOOFF2, U21_DESC, VPOOFF2_DESC, CRT_DVO_ES_DESC); +SIG_EXPR_LIST_DECL(VPOG6, VPO, + SIG_EXPR_PTR(VPOG6, VPO), + SIG_EXPR_PTR(VPOG6, VPOOFF1), + SIG_EXPR_PTR(VPOG6, VPOOFF2)); +SIG_EXPR_LIST_ALIAS(U21, VPOG6, VPO); +SIG_EXPR_LIST_DECL_SINGLE(U21, NORA4, PNOR, PNOR_DESC); +PIN_DECL_2(U21, GPIOZ4, VPOG6, NORA4); #define W22 205 #define W22_DESC SIG_DESC_SET(SCUA4, 21) -SIG_EXPR_DECL(VPOG7, VPO, W22_DESC, VPO_DESC, CRT_DVO_ES_DESC); -SIG_EXPR_DECL(VPOG7, VPOOFF1, W22_DESC, VPOOFF1_DESC, CRT_DVO_ES_DESC); -SIG_EXPR_DECL(VPOG7, VPOOFF2, W22_DESC, VPOOFF2_DESC, CRT_DVO_ES_DESC); -SIG_EXPR_LIST_DECL(VPOG7, SIG_EXPR_PTR(VPOG7, VPO), - SIG_EXPR_PTR(VPOG7, VPOOFF1), SIG_EXPR_PTR(VPOG7, VPOOFF2)); -SIG_EXPR_LIST_DECL_SINGLE(NORA5, PNOR, PNOR_DESC); -MS_PIN_DECL(W22, GPIOZ5, VPOG7, NORA5); +SIG_EXPR_DECL_SINGLE(VPOG7, VPO, W22_DESC, VPO_DESC, CRT_DVO_ES_DESC); +SIG_EXPR_DECL_SINGLE(VPOG7, VPOOFF1, W22_DESC, VPOOFF1_DESC, CRT_DVO_ES_DESC); +SIG_EXPR_DECL_SINGLE(VPOG7, VPOOFF2, W22_DESC, VPOOFF2_DESC, CRT_DVO_ES_DESC); +SIG_EXPR_LIST_DECL(VPOG7, VPO, + SIG_EXPR_PTR(VPOG7, VPO), + SIG_EXPR_PTR(VPOG7, VPOOFF1), + SIG_EXPR_PTR(VPOG7, VPOOFF2)); +SIG_EXPR_LIST_ALIAS(W22, VPOG7, VPO); +SIG_EXPR_LIST_DECL_SINGLE(W22, NORA5, PNOR, PNOR_DESC); +PIN_DECL_2(W22, GPIOZ5, VPOG7, NORA5); #define V22 206 #define V22_DESC SIG_DESC_SET(SCUA4, 22) -SIG_EXPR_DECL(VPOG8, VPO, V22_DESC, VPO_DESC, CRT_DVO_ES_DESC); -SIG_EXPR_DECL(VPOG8, VPOOFF1, V22_DESC, VPOOFF1_DESC, CRT_DVO_ES_DESC); -SIG_EXPR_DECL(VPOG8, VPOOFF2, V22_DESC, VPOOFF2_DESC, CRT_DVO_ES_DESC); -SIG_EXPR_LIST_DECL(VPOG8, SIG_EXPR_PTR(VPOG8, VPO), - SIG_EXPR_PTR(VPOG8, VPOOFF1), SIG_EXPR_PTR(VPOG8, VPOOFF2)); -SIG_EXPR_LIST_DECL_SINGLE(NORA6, PNOR, PNOR_DESC); -MS_PIN_DECL(V22, GPIOZ6, VPOG8, NORA6); +SIG_EXPR_DECL_SINGLE(VPOG8, VPO, V22_DESC, VPO_DESC, CRT_DVO_ES_DESC); +SIG_EXPR_DECL_SINGLE(VPOG8, VPOOFF1, V22_DESC, VPOOFF1_DESC, CRT_DVO_ES_DESC); +SIG_EXPR_DECL_SINGLE(VPOG8, VPOOFF2, V22_DESC, VPOOFF2_DESC, CRT_DVO_ES_DESC); +SIG_EXPR_LIST_DECL(VPOG8, VPO, + SIG_EXPR_PTR(VPOG8, VPO), + SIG_EXPR_PTR(VPOG8, VPOOFF1), + SIG_EXPR_PTR(VPOG8, VPOOFF2)); +SIG_EXPR_LIST_ALIAS(V22, VPOG8, VPO); +SIG_EXPR_LIST_DECL_SINGLE(V22, NORA6, PNOR, PNOR_DESC); +PIN_DECL_2(V22, GPIOZ6, VPOG8, NORA6); #define W21 207 #define W21_DESC SIG_DESC_SET(SCUA4, 23) -SIG_EXPR_DECL(VPOG9, VPO, W21_DESC, VPO_DESC, CRT_DVO_ES_DESC); -SIG_EXPR_DECL(VPOG9, VPOOFF1, W21_DESC, VPOOFF1_DESC, CRT_DVO_ES_DESC); -SIG_EXPR_DECL(VPOG9, VPOOFF2, W21_DESC, VPOOFF2_DESC, CRT_DVO_ES_DESC); -SIG_EXPR_LIST_DECL(VPOG9, SIG_EXPR_PTR(VPOG9, VPO), - SIG_EXPR_PTR(VPOG9, VPOOFF1), SIG_EXPR_PTR(VPOG9, VPOOFF2)); -SIG_EXPR_LIST_DECL_SINGLE(NORA7, PNOR, PNOR_DESC); -MS_PIN_DECL(W21, GPIOZ7, VPOG9, NORA7); +SIG_EXPR_DECL_SINGLE(VPOG9, VPO, W21_DESC, VPO_DESC, CRT_DVO_ES_DESC); +SIG_EXPR_DECL_SINGLE(VPOG9, VPOOFF1, W21_DESC, VPOOFF1_DESC, CRT_DVO_ES_DESC); +SIG_EXPR_DECL_SINGLE(VPOG9, VPOOFF2, W21_DESC, VPOOFF2_DESC, CRT_DVO_ES_DESC); +SIG_EXPR_LIST_DECL(VPOG9, VPO, + SIG_EXPR_PTR(VPOG9, VPO), + SIG_EXPR_PTR(VPOG9, VPOOFF1), + SIG_EXPR_PTR(VPOG9, VPOOFF2)); +SIG_EXPR_LIST_ALIAS(W21, VPOG9, VPO); +SIG_EXPR_LIST_DECL_SINGLE(W21, NORA7, PNOR, PNOR_DESC); +PIN_DECL_2(W21, GPIOZ7, VPOG9, NORA7); #define Y21 208 #define Y21_DESC SIG_DESC_SET(SCUA4, 24) -SIG_EXPR_DECL(VPOR2, VPO, Y21_DESC, VPO_DESC, CRT_DVO_ES_DESC); -SIG_EXPR_DECL(VPOR2, VPOOFF1, Y21_DESC, VPOOFF1_DESC, CRT_DVO_ES_DESC); -SIG_EXPR_DECL(VPOR2, VPOOFF2, Y21_DESC, VPOOFF2_DESC, CRT_DVO_ES_DESC); -SIG_EXPR_LIST_DECL(VPOR2, SIG_EXPR_PTR(VPOR2, VPO), - SIG_EXPR_PTR(VPOR2, VPOOFF1), SIG_EXPR_PTR(VPOR2, VPOOFF2)); -SIG_EXPR_LIST_DECL_SINGLE(SALT7, SALT7, Y21_DESC); -SIG_EXPR_LIST_DECL_SINGLE(NORD0, PNOR, PNOR_DESC); -SIG_EXPR_LIST_DECL_SINGLE(GPIOAA0, GPIOAA0); -MS_PIN_DECL_(Y21, SIG_EXPR_LIST_PTR(VPOR2), SIG_EXPR_LIST_PTR(SALT7), - SIG_EXPR_LIST_PTR(NORD0), SIG_EXPR_LIST_PTR(GPIOAA0)); +SIG_EXPR_DECL_SINGLE(VPOR2, VPO, Y21_DESC, VPO_DESC, CRT_DVO_ES_DESC); +SIG_EXPR_DECL_SINGLE(VPOR2, VPOOFF1, Y21_DESC, VPOOFF1_DESC, CRT_DVO_ES_DESC); +SIG_EXPR_DECL_SINGLE(VPOR2, VPOOFF2, Y21_DESC, VPOOFF2_DESC, CRT_DVO_ES_DESC); +SIG_EXPR_LIST_DECL(VPOR2, VPO, + SIG_EXPR_PTR(VPOR2, VPO), + SIG_EXPR_PTR(VPOR2, VPOOFF1), + SIG_EXPR_PTR(VPOR2, VPOOFF2)); +SIG_EXPR_LIST_ALIAS(Y21, VPOR2, VPO); +SIG_EXPR_LIST_DECL_SINGLE(Y21, SALT7, SALT7, Y21_DESC); +SIG_EXPR_LIST_DECL_SINGLE(Y21, NORD0, PNOR, PNOR_DESC); +SIG_EXPR_LIST_DECL_SINGLE(Y21, GPIOAA0, GPIOAA0); +PIN_DECL_(Y21, SIG_EXPR_LIST_PTR(Y21, VPOR2), SIG_EXPR_LIST_PTR(Y21, SALT7), + SIG_EXPR_LIST_PTR(Y21, NORD0), SIG_EXPR_LIST_PTR(Y21, GPIOAA0)); FUNC_GROUP_DECL(SALT7, Y21); #define V21 209 #define V21_DESC SIG_DESC_SET(SCUA4, 25) -SIG_EXPR_DECL(VPOR3, VPO, V21_DESC, VPO_DESC, CRT_DVO_ES_DESC); -SIG_EXPR_DECL(VPOR3, VPOOFF1, V21_DESC, VPOOFF1_DESC, CRT_DVO_ES_DESC); -SIG_EXPR_DECL(VPOR3, VPOOFF2, V21_DESC, VPOOFF2_DESC, CRT_DVO_ES_DESC); -SIG_EXPR_LIST_DECL(VPOR3, SIG_EXPR_PTR(VPOR3, VPO), - SIG_EXPR_PTR(VPOR3, VPOOFF1), SIG_EXPR_PTR(VPOR3, VPOOFF2)); -SIG_EXPR_LIST_DECL_SINGLE(SALT8, SALT8, V21_DESC); -SIG_EXPR_LIST_DECL_SINGLE(NORD1, PNOR, PNOR_DESC); -SIG_EXPR_LIST_DECL_SINGLE(GPIOAA1, GPIOAA1); -MS_PIN_DECL_(V21, SIG_EXPR_LIST_PTR(VPOR3), SIG_EXPR_LIST_PTR(SALT8), - SIG_EXPR_LIST_PTR(NORD1), SIG_EXPR_LIST_PTR(GPIOAA1)); +SIG_EXPR_DECL_SINGLE(VPOR3, VPO, V21_DESC, VPO_DESC, CRT_DVO_ES_DESC); +SIG_EXPR_DECL_SINGLE(VPOR3, VPOOFF1, V21_DESC, VPOOFF1_DESC, CRT_DVO_ES_DESC); +SIG_EXPR_DECL_SINGLE(VPOR3, VPOOFF2, V21_DESC, VPOOFF2_DESC, CRT_DVO_ES_DESC); +SIG_EXPR_LIST_DECL(VPOR3, VPO, + SIG_EXPR_PTR(VPOR3, VPO), + SIG_EXPR_PTR(VPOR3, VPOOFF1), + SIG_EXPR_PTR(VPOR3, VPOOFF2)); +SIG_EXPR_LIST_ALIAS(V21, VPOR3, VPO); +SIG_EXPR_LIST_DECL_SINGLE(V21, SALT8, SALT8, V21_DESC); +SIG_EXPR_LIST_DECL_SINGLE(V21, NORD1, PNOR, PNOR_DESC); +SIG_EXPR_LIST_DECL_SINGLE(V21, GPIOAA1, GPIOAA1); +PIN_DECL_(V21, SIG_EXPR_LIST_PTR(V21, VPOR3), SIG_EXPR_LIST_PTR(V21, SALT8), + SIG_EXPR_LIST_PTR(V21, NORD1), SIG_EXPR_LIST_PTR(V21, GPIOAA1)); FUNC_GROUP_DECL(SALT8, V21); #define Y22 210 #define Y22_DESC SIG_DESC_SET(SCUA4, 26) -SIG_EXPR_DECL(VPOR4, VPO, Y22_DESC, VPO_DESC, CRT_DVO_ES_DESC); -SIG_EXPR_DECL(VPOR4, VPOOFF1, Y22_DESC, VPOOFF1_DESC, CRT_DVO_ES_DESC); -SIG_EXPR_DECL(VPOR4, VPOOFF2, Y22_DESC, VPOOFF2_DESC, CRT_DVO_ES_DESC); -SIG_EXPR_LIST_DECL(VPOR4, SIG_EXPR_PTR(VPOR4, VPO), - SIG_EXPR_PTR(VPOR4, VPOOFF1), SIG_EXPR_PTR(VPOR4, VPOOFF2)); -SIG_EXPR_LIST_DECL_SINGLE(SALT9, SALT9, Y22_DESC); -SIG_EXPR_LIST_DECL_SINGLE(NORD2, PNOR, PNOR_DESC); -SIG_EXPR_LIST_DECL_SINGLE(GPIOAA2, GPIOAA2); -MS_PIN_DECL_(Y22, SIG_EXPR_LIST_PTR(VPOR4), SIG_EXPR_LIST_PTR(SALT9), - SIG_EXPR_LIST_PTR(NORD2), SIG_EXPR_LIST_PTR(GPIOAA2)); +SIG_EXPR_DECL_SINGLE(VPOR4, VPO, Y22_DESC, VPO_DESC, CRT_DVO_ES_DESC); +SIG_EXPR_DECL_SINGLE(VPOR4, VPOOFF1, Y22_DESC, VPOOFF1_DESC, CRT_DVO_ES_DESC); +SIG_EXPR_DECL_SINGLE(VPOR4, VPOOFF2, Y22_DESC, VPOOFF2_DESC, CRT_DVO_ES_DESC); +SIG_EXPR_LIST_DECL(VPOR4, VPO, + SIG_EXPR_PTR(VPOR4, VPO), + SIG_EXPR_PTR(VPOR4, VPOOFF1), + SIG_EXPR_PTR(VPOR4, VPOOFF2)); +SIG_EXPR_LIST_ALIAS(Y22, VPOR4, VPO); +SIG_EXPR_LIST_DECL_SINGLE(Y22, SALT9, SALT9, Y22_DESC); +SIG_EXPR_LIST_DECL_SINGLE(Y22, NORD2, PNOR, PNOR_DESC); +SIG_EXPR_LIST_DECL_SINGLE(Y22, GPIOAA2, GPIOAA2); +PIN_DECL_(Y22, SIG_EXPR_LIST_PTR(Y22, VPOR4), SIG_EXPR_LIST_PTR(Y22, SALT9), + SIG_EXPR_LIST_PTR(Y22, NORD2), SIG_EXPR_LIST_PTR(Y22, GPIOAA2)); FUNC_GROUP_DECL(SALT9, Y22); #define AA22 211 #define AA22_DESC SIG_DESC_SET(SCUA4, 27) -SIG_EXPR_DECL(VPOR5, VPO, AA22_DESC, VPO_DESC, CRT_DVO_ES_DESC); -SIG_EXPR_DECL(VPOR5, VPOOFF1, AA22_DESC, VPOOFF1_DESC, CRT_DVO_ES_DESC); -SIG_EXPR_DECL(VPOR5, VPOOFF2, AA22_DESC, VPOOFF2_DESC, CRT_DVO_ES_DESC); -SIG_EXPR_LIST_DECL(VPOR5, SIG_EXPR_PTR(VPOR5, VPO), - SIG_EXPR_PTR(VPOR5, VPOOFF1), SIG_EXPR_PTR(VPOR5, VPOOFF2)); -SIG_EXPR_LIST_DECL_SINGLE(SALT10, SALT10, AA22_DESC); -SIG_EXPR_LIST_DECL_SINGLE(NORD3, PNOR, PNOR_DESC); -SIG_EXPR_LIST_DECL_SINGLE(GPIOAA3, GPIOAA3); -MS_PIN_DECL_(AA22, SIG_EXPR_LIST_PTR(VPOR5), SIG_EXPR_LIST_PTR(SALT10), - SIG_EXPR_LIST_PTR(NORD3), SIG_EXPR_LIST_PTR(GPIOAA3)); +SIG_EXPR_DECL_SINGLE(VPOR5, VPO, AA22_DESC, VPO_DESC, CRT_DVO_ES_DESC); +SIG_EXPR_DECL_SINGLE(VPOR5, VPOOFF1, AA22_DESC, VPOOFF1_DESC, CRT_DVO_ES_DESC); +SIG_EXPR_DECL_SINGLE(VPOR5, VPOOFF2, AA22_DESC, VPOOFF2_DESC, CRT_DVO_ES_DESC); +SIG_EXPR_LIST_DECL(VPOR5, VPO, + SIG_EXPR_PTR(VPOR5, VPO), + SIG_EXPR_PTR(VPOR5, VPOOFF1), + SIG_EXPR_PTR(VPOR5, VPOOFF2)); +SIG_EXPR_LIST_ALIAS(AA22, VPOR5, VPO); +SIG_EXPR_LIST_DECL_SINGLE(AA22, SALT10, SALT10, AA22_DESC); +SIG_EXPR_LIST_DECL_SINGLE(AA22, NORD3, PNOR, PNOR_DESC); +SIG_EXPR_LIST_DECL_SINGLE(AA22, GPIOAA3, GPIOAA3); +PIN_DECL_(AA22, SIG_EXPR_LIST_PTR(AA22, VPOR5), + SIG_EXPR_LIST_PTR(AA22, SALT10), SIG_EXPR_LIST_PTR(AA22, NORD3), + SIG_EXPR_LIST_PTR(AA22, GPIOAA3)); FUNC_GROUP_DECL(SALT10, AA22); #define U22 212 #define U22_DESC SIG_DESC_SET(SCUA4, 28) -SIG_EXPR_DECL(VPOR6, VPO, U22_DESC, VPO_DESC, CRT_DVO_ES_DESC); -SIG_EXPR_DECL(VPOR6, VPOOFF1, U22_DESC, VPOOFF1_DESC, CRT_DVO_ES_DESC); -SIG_EXPR_DECL(VPOR6, VPOOFF2, U22_DESC, VPOOFF2_DESC, CRT_DVO_ES_DESC); -SIG_EXPR_LIST_DECL(VPOR6, SIG_EXPR_PTR(VPOR6, VPO), - SIG_EXPR_PTR(VPOR6, VPOOFF1), SIG_EXPR_PTR(VPOR6, VPOOFF2)); -SIG_EXPR_LIST_DECL_SINGLE(SALT11, SALT11, U22_DESC); -SIG_EXPR_LIST_DECL_SINGLE(NORD4, PNOR, PNOR_DESC); -SIG_EXPR_LIST_DECL_SINGLE(GPIOAA4, GPIOAA4); -MS_PIN_DECL_(U22, SIG_EXPR_LIST_PTR(VPOR6), SIG_EXPR_LIST_PTR(SALT11), - SIG_EXPR_LIST_PTR(NORD4), SIG_EXPR_LIST_PTR(GPIOAA4)); +SIG_EXPR_DECL_SINGLE(VPOR6, VPO, U22_DESC, VPO_DESC, CRT_DVO_ES_DESC); +SIG_EXPR_DECL_SINGLE(VPOR6, VPOOFF1, U22_DESC, VPOOFF1_DESC, CRT_DVO_ES_DESC); +SIG_EXPR_DECL_SINGLE(VPOR6, VPOOFF2, U22_DESC, VPOOFF2_DESC, CRT_DVO_ES_DESC); +SIG_EXPR_LIST_DECL(VPOR6, VPO, + SIG_EXPR_PTR(VPOR6, VPO), + SIG_EXPR_PTR(VPOR6, VPOOFF1), + SIG_EXPR_PTR(VPOR6, VPOOFF2)); +SIG_EXPR_LIST_ALIAS(U22, VPOR6, VPO); +SIG_EXPR_LIST_DECL_SINGLE(U22, SALT11, SALT11, U22_DESC); +SIG_EXPR_LIST_DECL_SINGLE(U22, NORD4, PNOR, PNOR_DESC); +SIG_EXPR_LIST_DECL_SINGLE(U22, GPIOAA4, GPIOAA4); +PIN_DECL_(U22, SIG_EXPR_LIST_PTR(U22, VPOR6), SIG_EXPR_LIST_PTR(U22, SALT11), + SIG_EXPR_LIST_PTR(U22, NORD4), SIG_EXPR_LIST_PTR(U22, GPIOAA4)); FUNC_GROUP_DECL(SALT11, U22); #define T20 213 #define T20_DESC SIG_DESC_SET(SCUA4, 29) -SIG_EXPR_DECL(VPOR7, VPO, T20_DESC, VPO_DESC, CRT_DVO_ES_DESC); -SIG_EXPR_DECL(VPOR7, VPOOFF1, T20_DESC, VPOOFF1_DESC, CRT_DVO_ES_DESC); -SIG_EXPR_DECL(VPOR7, VPOOFF2, T20_DESC, VPOOFF2_DESC, CRT_DVO_ES_DESC); -SIG_EXPR_LIST_DECL(VPOR7, SIG_EXPR_PTR(VPOR7, VPO), - SIG_EXPR_PTR(VPOR7, VPOOFF1), SIG_EXPR_PTR(VPOR7, VPOOFF2)); -SIG_EXPR_LIST_DECL_SINGLE(SALT12, SALT12, T20_DESC); -SIG_EXPR_LIST_DECL_SINGLE(NORD5, PNOR, PNOR_DESC); -SIG_EXPR_LIST_DECL_SINGLE(GPIOAA5, GPIOAA5); -MS_PIN_DECL_(T20, SIG_EXPR_LIST_PTR(VPOR7), SIG_EXPR_LIST_PTR(SALT12), - SIG_EXPR_LIST_PTR(NORD5), SIG_EXPR_LIST_PTR(GPIOAA5)); +SIG_EXPR_DECL_SINGLE(VPOR7, VPO, T20_DESC, VPO_DESC, CRT_DVO_ES_DESC); +SIG_EXPR_DECL_SINGLE(VPOR7, VPOOFF1, T20_DESC, VPOOFF1_DESC, CRT_DVO_ES_DESC); +SIG_EXPR_DECL_SINGLE(VPOR7, VPOOFF2, T20_DESC, VPOOFF2_DESC, CRT_DVO_ES_DESC); +SIG_EXPR_LIST_DECL(VPOR7, VPO, + SIG_EXPR_PTR(VPOR7, VPO), + SIG_EXPR_PTR(VPOR7, VPOOFF1), + SIG_EXPR_PTR(VPOR7, VPOOFF2)); +SIG_EXPR_LIST_ALIAS(T20, VPOR7, VPO); +SIG_EXPR_LIST_DECL_SINGLE(T20, SALT12, SALT12, T20_DESC); +SIG_EXPR_LIST_DECL_SINGLE(T20, NORD5, PNOR, PNOR_DESC); +SIG_EXPR_LIST_DECL_SINGLE(T20, GPIOAA5, GPIOAA5); +PIN_DECL_(T20, SIG_EXPR_LIST_PTR(T20, VPOR7), SIG_EXPR_LIST_PTR(T20, SALT12), + SIG_EXPR_LIST_PTR(T20, NORD5), SIG_EXPR_LIST_PTR(T20, GPIOAA5)); FUNC_GROUP_DECL(SALT12, T20); #define N18 214 #define N18_DESC SIG_DESC_SET(SCUA4, 30) -SIG_EXPR_DECL(VPOR8, VPO, N18_DESC, VPO_DESC, CRT_DVO_ES_DESC); -SIG_EXPR_DECL(VPOR8, VPOOFF1, N18_DESC, VPOOFF1_DESC, CRT_DVO_ES_DESC); -SIG_EXPR_DECL(VPOR8, VPOOFF2, N18_DESC, VPOOFF2_DESC, CRT_DVO_ES_DESC); -SIG_EXPR_LIST_DECL(VPOR8, SIG_EXPR_PTR(VPOR8, VPO), - SIG_EXPR_PTR(VPOR8, VPOOFF1), SIG_EXPR_PTR(VPOR8, VPOOFF2)); -SIG_EXPR_LIST_DECL_SINGLE(SALT13, SALT13, N18_DESC); -SIG_EXPR_LIST_DECL_SINGLE(NORD6, PNOR, PNOR_DESC); -SIG_EXPR_LIST_DECL_SINGLE(GPIOAA6, GPIOAA6); -MS_PIN_DECL_(N18, SIG_EXPR_LIST_PTR(VPOR8), SIG_EXPR_LIST_PTR(SALT13), - SIG_EXPR_LIST_PTR(NORD6), SIG_EXPR_LIST_PTR(GPIOAA6)); +SIG_EXPR_DECL_SINGLE(VPOR8, VPO, N18_DESC, VPO_DESC, CRT_DVO_ES_DESC); +SIG_EXPR_DECL_SINGLE(VPOR8, VPOOFF1, N18_DESC, VPOOFF1_DESC, CRT_DVO_ES_DESC); +SIG_EXPR_DECL_SINGLE(VPOR8, VPOOFF2, N18_DESC, VPOOFF2_DESC, CRT_DVO_ES_DESC); +SIG_EXPR_LIST_DECL(VPOR8, VPO, + SIG_EXPR_PTR(VPOR8, VPO), + SIG_EXPR_PTR(VPOR8, VPOOFF1), + SIG_EXPR_PTR(VPOR8, VPOOFF2)); +SIG_EXPR_LIST_ALIAS(N18, VPOR8, VPO); +SIG_EXPR_LIST_DECL_SINGLE(N18, SALT13, SALT13, N18_DESC); +SIG_EXPR_LIST_DECL_SINGLE(N18, NORD6, PNOR, PNOR_DESC); +SIG_EXPR_LIST_DECL_SINGLE(N18, GPIOAA6, GPIOAA6); +PIN_DECL_(N18, SIG_EXPR_LIST_PTR(N18, VPOR8), SIG_EXPR_LIST_PTR(N18, SALT13), + SIG_EXPR_LIST_PTR(N18, NORD6), SIG_EXPR_LIST_PTR(N18, GPIOAA6)); FUNC_GROUP_DECL(SALT13, N18); #define P19 215 #define P19_DESC SIG_DESC_SET(SCUA4, 31) -SIG_EXPR_DECL(VPOR9, VPO, P19_DESC, VPO_DESC, CRT_DVO_ES_DESC); -SIG_EXPR_DECL(VPOR9, VPOOFF1, P19_DESC, VPOOFF1_DESC, CRT_DVO_ES_DESC); -SIG_EXPR_DECL(VPOR9, VPOOFF2, P19_DESC, VPOOFF2_DESC, CRT_DVO_ES_DESC); -SIG_EXPR_LIST_DECL(VPOR9, SIG_EXPR_PTR(VPOR9, VPO), - SIG_EXPR_PTR(VPOR9, VPOOFF1), SIG_EXPR_PTR(VPOR9, VPOOFF2)); -SIG_EXPR_LIST_DECL_SINGLE(SALT14, SALT14, P19_DESC); -SIG_EXPR_LIST_DECL_SINGLE(NORD7, PNOR, PNOR_DESC); -SIG_EXPR_LIST_DECL_SINGLE(GPIOAA7, GPIOAA7); -MS_PIN_DECL_(P19, SIG_EXPR_LIST_PTR(VPOR9), SIG_EXPR_LIST_PTR(SALT14), - SIG_EXPR_LIST_PTR(NORD7), SIG_EXPR_LIST_PTR(GPIOAA7)); +SIG_EXPR_DECL_SINGLE(VPOR9, VPO, P19_DESC, VPO_DESC, CRT_DVO_ES_DESC); +SIG_EXPR_DECL_SINGLE(VPOR9, VPOOFF1, P19_DESC, VPOOFF1_DESC, CRT_DVO_ES_DESC); +SIG_EXPR_DECL_SINGLE(VPOR9, VPOOFF2, P19_DESC, VPOOFF2_DESC, CRT_DVO_ES_DESC); +SIG_EXPR_LIST_DECL(VPOR9, VPO, + SIG_EXPR_PTR(VPOR9, VPO), + SIG_EXPR_PTR(VPOR9, VPOOFF1), + SIG_EXPR_PTR(VPOR9, VPOOFF2)); +SIG_EXPR_LIST_ALIAS(P19, VPOR9, VPO); +SIG_EXPR_LIST_DECL_SINGLE(P19, SALT14, SALT14, P19_DESC); +SIG_EXPR_LIST_DECL_SINGLE(P19, NORD7, PNOR, PNOR_DESC); +SIG_EXPR_LIST_DECL_SINGLE(P19, GPIOAA7, GPIOAA7); +PIN_DECL_(P19, SIG_EXPR_LIST_PTR(P19, VPOR9), SIG_EXPR_LIST_PTR(P19, SALT14), + SIG_EXPR_LIST_PTR(P19, NORD7), SIG_EXPR_LIST_PTR(P19, GPIOAA7)); FUNC_GROUP_DECL(SALT14, P19); #define N19 216 #define N19_DESC SIG_DESC_SET(SCUA8, 0) -SIG_EXPR_DECL(VPODE, VPO, N19_DESC, VPO_DESC, CRT_DVO_EN_DESC); -SIG_EXPR_DECL(VPODE, VPOOFF1, N19_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC); -SIG_EXPR_DECL(VPODE, VPOOFF2, N19_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC); -SIG_EXPR_LIST_DECL(VPODE, SIG_EXPR_PTR(VPODE, VPO), - SIG_EXPR_PTR(VPODE, VPOOFF1), SIG_EXPR_PTR(VPODE, VPOOFF2)); -SIG_EXPR_LIST_DECL_SINGLE(NOROE, PNOR, PNOR_DESC); -MS_PIN_DECL(N19, GPIOAB0, VPODE, NOROE); +SIG_EXPR_DECL_SINGLE(VPODE, VPO, N19_DESC, VPO_DESC, CRT_DVO_EN_DESC); +SIG_EXPR_DECL_SINGLE(VPODE, VPOOFF1, N19_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC); +SIG_EXPR_DECL_SINGLE(VPODE, VPOOFF2, N19_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC); +SIG_EXPR_LIST_DECL(VPODE, VPO, + SIG_EXPR_PTR(VPODE, VPO), + SIG_EXPR_PTR(VPODE, VPOOFF1), + SIG_EXPR_PTR(VPODE, VPOOFF2)); +SIG_EXPR_LIST_ALIAS(N19, VPODE, VPO); +SIG_EXPR_LIST_DECL_SINGLE(N19, NOROE, PNOR, PNOR_DESC); +PIN_DECL_2(N19, GPIOAB0, VPODE, NOROE); #define T21 217 #define T21_DESC SIG_DESC_SET(SCUA8, 1) -SIG_EXPR_DECL(VPOHS, VPO, T21_DESC, VPO_DESC, CRT_DVO_EN_DESC); -SIG_EXPR_DECL(VPOHS, VPOOFF1, T21_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC); -SIG_EXPR_DECL(VPOHS, VPOOFF2, T21_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC); -SIG_EXPR_LIST_DECL(VPOHS, SIG_EXPR_PTR(VPOHS, VPO), - SIG_EXPR_PTR(VPOHS, VPOOFF1), SIG_EXPR_PTR(VPOHS, VPOOFF2)); -SIG_EXPR_LIST_DECL_SINGLE(NORWE, PNOR, PNOR_DESC); -MS_PIN_DECL(T21, GPIOAB1, VPOHS, NORWE); +SIG_EXPR_DECL_SINGLE(VPOHS, VPO, T21_DESC, VPO_DESC, CRT_DVO_EN_DESC); +SIG_EXPR_DECL_SINGLE(VPOHS, VPOOFF1, T21_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC); +SIG_EXPR_DECL_SINGLE(VPOHS, VPOOFF2, T21_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC); +SIG_EXPR_LIST_DECL(VPOHS, VPO, + SIG_EXPR_PTR(VPOHS, VPO), + SIG_EXPR_PTR(VPOHS, VPOOFF1), + SIG_EXPR_PTR(VPOHS, VPOOFF2)); +SIG_EXPR_LIST_ALIAS(T21, VPOHS, VPO); +SIG_EXPR_LIST_DECL_SINGLE(T21, NORWE, PNOR, PNOR_DESC); +PIN_DECL_2(T21, GPIOAB1, VPOHS, NORWE); FUNC_GROUP_DECL(PNOR, Y20, AB20, AB21, AA21, U21, W22, V22, W21, Y21, V21, Y22, AA22, U22, T20, N18, P19, N19, T21); #define T22 218 #define T22_DESC SIG_DESC_SET(SCUA8, 2) -SIG_EXPR_DECL(VPOVS, VPO, T22_DESC, VPO_DESC, CRT_DVO_EN_DESC); -SIG_EXPR_DECL(VPOVS, VPOOFF1, T22_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC); -SIG_EXPR_DECL(VPOVS, VPOOFF2, T22_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC); -SIG_EXPR_LIST_DECL(VPOVS, SIG_EXPR_PTR(VPOVS, VPO), - SIG_EXPR_PTR(VPOVS, VPOOFF1), SIG_EXPR_PTR(VPOVS, VPOOFF2)); -SIG_EXPR_LIST_DECL_SINGLE(WDTRST1, WDTRST1, T22_DESC); -MS_PIN_DECL(T22, GPIOAB2, VPOVS, WDTRST1); +SIG_EXPR_DECL_SINGLE(VPOVS, VPO, T22_DESC, VPO_DESC, CRT_DVO_EN_DESC); +SIG_EXPR_DECL_SINGLE(VPOVS, VPOOFF1, T22_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC); +SIG_EXPR_DECL_SINGLE(VPOVS, VPOOFF2, T22_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC); +SIG_EXPR_LIST_DECL(VPOVS, VPO, + SIG_EXPR_PTR(VPOVS, VPO), + SIG_EXPR_PTR(VPOVS, VPOOFF1), + SIG_EXPR_PTR(VPOVS, VPOOFF2)); +SIG_EXPR_LIST_ALIAS(T22, VPOVS, VPO); +SIG_EXPR_LIST_DECL_SINGLE(T22, WDTRST1, WDTRST1, T22_DESC); +PIN_DECL_2(T22, GPIOAB2, VPOVS, WDTRST1); FUNC_GROUP_DECL(WDTRST1, T22); #define R20 219 #define R20_DESC SIG_DESC_SET(SCUA8, 3) -SIG_EXPR_DECL(VPOCLK, VPO, R20_DESC, VPO_DESC, CRT_DVO_EN_DESC); -SIG_EXPR_DECL(VPOCLK, VPOOFF1, R20_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC); -SIG_EXPR_DECL(VPOCLK, VPOOFF2, R20_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC); -SIG_EXPR_LIST_DECL(VPOCLK, SIG_EXPR_PTR(VPOCLK, VPO), - SIG_EXPR_PTR(VPOCLK, VPOOFF1), SIG_EXPR_PTR(VPOCLK, VPOOFF2)); -SIG_EXPR_LIST_DECL_SINGLE(WDTRST2, WDTRST2, R20_DESC); -MS_PIN_DECL(R20, GPIOAB3, VPOCLK, WDTRST2); +SIG_EXPR_DECL_SINGLE(VPOCLK, VPO, R20_DESC, VPO_DESC, CRT_DVO_EN_DESC); +SIG_EXPR_DECL_SINGLE(VPOCLK, VPOOFF1, R20_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC); +SIG_EXPR_DECL_SINGLE(VPOCLK, VPOOFF2, R20_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC); +SIG_EXPR_LIST_DECL(VPOCLK, VPO, + SIG_EXPR_PTR(VPOCLK, VPO), + SIG_EXPR_PTR(VPOCLK, VPOOFF1), + SIG_EXPR_PTR(VPOCLK, VPOOFF2)); +SIG_EXPR_LIST_ALIAS(R20, VPOCLK, VPO); +SIG_EXPR_LIST_DECL_SINGLE(R20, WDTRST2, WDTRST2, R20_DESC); +PIN_DECL_2(R20, GPIOAB3, VPOCLK, WDTRST2); FUNC_GROUP_DECL(WDTRST2, R20); FUNC_GROUP_DECL(VPO, V20, U19, R18, P18, R19, W20, U20, AA20, Y20, AB20, @@ -1699,64 +1802,64 @@ FUNC_GROUP_DECL(VPO, V20, U19, R18, P18, R19, W20, U20, AA20, Y20, AB20, #define ESPI_DESC SIG_DESC_SET(HW_STRAP1, 25) #define G21 224 -SIG_EXPR_LIST_DECL_SINGLE(ESPID0, ESPI, ESPI_DESC); -SIG_EXPR_LIST_DECL_SINGLE(LAD0, LAD0, SIG_DESC_SET(SCUAC, 0)); -MS_PIN_DECL(G21, GPIOAC0, ESPID0, LAD0); +SIG_EXPR_LIST_DECL_SINGLE(G21, ESPID0, ESPI, ESPI_DESC); +SIG_EXPR_LIST_DECL_SINGLE(G21, LAD0, LAD0, SIG_DESC_SET(SCUAC, 0)); +PIN_DECL_2(G21, GPIOAC0, ESPID0, LAD0); FUNC_GROUP_DECL(LAD0, G21); #define G20 225 -SIG_EXPR_LIST_DECL_SINGLE(ESPID1, ESPI, ESPI_DESC); -SIG_EXPR_LIST_DECL_SINGLE(LAD1, LAD1, SIG_DESC_SET(SCUAC, 1)); -MS_PIN_DECL(G20, GPIOAC1, ESPID1, LAD1); +SIG_EXPR_LIST_DECL_SINGLE(G20, ESPID1, ESPI, ESPI_DESC); +SIG_EXPR_LIST_DECL_SINGLE(G20, LAD1, LAD1, SIG_DESC_SET(SCUAC, 1)); +PIN_DECL_2(G20, GPIOAC1, ESPID1, LAD1); FUNC_GROUP_DECL(LAD1, G20); #define D22 226 -SIG_EXPR_LIST_DECL_SINGLE(ESPID2, ESPI, ESPI_DESC); -SIG_EXPR_LIST_DECL_SINGLE(LAD2, LAD2, SIG_DESC_SET(SCUAC, 2)); -MS_PIN_DECL(D22, GPIOAC2, ESPID2, LAD2); +SIG_EXPR_LIST_DECL_SINGLE(D22, ESPID2, ESPI, ESPI_DESC); +SIG_EXPR_LIST_DECL_SINGLE(D22, LAD2, LAD2, SIG_DESC_SET(SCUAC, 2)); +PIN_DECL_2(D22, GPIOAC2, ESPID2, LAD2); FUNC_GROUP_DECL(LAD2, D22); #define E22 227 -SIG_EXPR_LIST_DECL_SINGLE(ESPID3, ESPI, ESPI_DESC); -SIG_EXPR_LIST_DECL_SINGLE(LAD3, LAD3, SIG_DESC_SET(SCUAC, 3)); -MS_PIN_DECL(E22, GPIOAC3, ESPID3, LAD3); +SIG_EXPR_LIST_DECL_SINGLE(E22, ESPID3, ESPI, ESPI_DESC); +SIG_EXPR_LIST_DECL_SINGLE(E22, LAD3, LAD3, SIG_DESC_SET(SCUAC, 3)); +PIN_DECL_2(E22, GPIOAC3, ESPID3, LAD3); FUNC_GROUP_DECL(LAD3, E22); #define C22 228 -SIG_EXPR_LIST_DECL_SINGLE(ESPICK, ESPI, ESPI_DESC); -SIG_EXPR_LIST_DECL_SINGLE(LCLK, LCLK, SIG_DESC_SET(SCUAC, 4)); -MS_PIN_DECL(C22, GPIOAC4, ESPICK, LCLK); +SIG_EXPR_LIST_DECL_SINGLE(C22, ESPICK, ESPI, ESPI_DESC); +SIG_EXPR_LIST_DECL_SINGLE(C22, LCLK, LCLK, SIG_DESC_SET(SCUAC, 4)); +PIN_DECL_2(C22, GPIOAC4, ESPICK, LCLK); FUNC_GROUP_DECL(LCLK, C22); #define F21 229 -SIG_EXPR_LIST_DECL_SINGLE(ESPICS, ESPI, ESPI_DESC); -SIG_EXPR_LIST_DECL_SINGLE(LFRAME, LFRAME, SIG_DESC_SET(SCUAC, 5)); -MS_PIN_DECL(F21, GPIOAC5, ESPICS, LFRAME); +SIG_EXPR_LIST_DECL_SINGLE(F21, ESPICS, ESPI, ESPI_DESC); +SIG_EXPR_LIST_DECL_SINGLE(F21, LFRAME, LFRAME, SIG_DESC_SET(SCUAC, 5)); +PIN_DECL_2(F21, GPIOAC5, ESPICS, LFRAME); FUNC_GROUP_DECL(LFRAME, F21); #define F22 230 -SIG_EXPR_LIST_DECL_SINGLE(ESPIALT, ESPI, ESPI_DESC); -SIG_EXPR_LIST_DECL_SINGLE(LSIRQ, LSIRQ, SIG_DESC_SET(SCUAC, 6)); -MS_PIN_DECL(F22, GPIOAC6, ESPIALT, LSIRQ); +SIG_EXPR_LIST_DECL_SINGLE(F22, ESPIALT, ESPI, ESPI_DESC); +SIG_EXPR_LIST_DECL_SINGLE(F22, LSIRQ, LSIRQ, SIG_DESC_SET(SCUAC, 6)); +PIN_DECL_2(F22, GPIOAC6, ESPIALT, LSIRQ); FUNC_GROUP_DECL(LSIRQ, F22); #define G22 231 -SIG_EXPR_LIST_DECL_SINGLE(ESPIRST, ESPI, ESPI_DESC); -SIG_EXPR_LIST_DECL_SINGLE(LPCRST, LPCRST, SIG_DESC_SET(SCUAC, 7)); -MS_PIN_DECL(G22, GPIOAC7, ESPIRST, LPCRST); +SIG_EXPR_LIST_DECL_SINGLE(G22, ESPIRST, ESPI, ESPI_DESC); +SIG_EXPR_LIST_DECL_SINGLE(G22, LPCRST, LPCRST, SIG_DESC_SET(SCUAC, 7)); +PIN_DECL_2(G22, GPIOAC7, ESPIRST, LPCRST); FUNC_GROUP_DECL(LPCRST, G22); FUNC_GROUP_DECL(ESPI, G21, G20, D22, E22, C22, F21, F22, G22); #define A7 232 -SIG_EXPR_LIST_DECL_SINGLE(USB2AHDP, USB2AH, SIG_DESC_SET(SCU90, 29)); -SIG_EXPR_LIST_DECL_SINGLE(USB2ADDP, USB2AD, SIG_DESC_BIT(SCU90, 29, 0)); -MS_PIN_DECL_(A7, SIG_EXPR_LIST_PTR(USB2AHDP), SIG_EXPR_LIST_PTR(USB2ADDP)); +SIG_EXPR_LIST_DECL_SINGLE(A7, USB2AHDP, USB2AH, SIG_DESC_SET(SCU90, 29)); +SIG_EXPR_LIST_DECL_SINGLE(A7, USB2ADDP, USB2AD, SIG_DESC_BIT(SCU90, 29, 0)); +PIN_DECL_(A7, SIG_EXPR_LIST_PTR(A7, USB2AHDP), SIG_EXPR_LIST_PTR(A7, USB2ADDP)); #define A8 233 -SIG_EXPR_LIST_DECL_SINGLE(USB2AHDN, USB2AH, SIG_DESC_SET(SCU90, 29)); -SIG_EXPR_LIST_DECL_SINGLE(USB2ADDN, USB2AD, SIG_DESC_BIT(SCU90, 29, 0)); -MS_PIN_DECL_(A8, SIG_EXPR_LIST_PTR(USB2AHDN), SIG_EXPR_LIST_PTR(USB2ADDN)); +SIG_EXPR_LIST_DECL_SINGLE(A8, USB2AHDN, USB2AH, SIG_DESC_SET(SCU90, 29)); +SIG_EXPR_LIST_DECL_SINGLE(A8, USB2ADDN, USB2AD, SIG_DESC_BIT(SCU90, 29, 0)); +PIN_DECL_(A8, SIG_EXPR_LIST_PTR(A8, USB2AHDN), SIG_EXPR_LIST_PTR(A8, USB2ADDN)); FUNC_GROUP_DECL(USB2AH, A7, A8); FUNC_GROUP_DECL(USB2AD, A7, A8); @@ -1767,24 +1870,28 @@ FUNC_GROUP_DECL(USB2AD, A7, A8); #define USB2BH2_DESC { ASPEED_IP_SCU, SCU94, GENMASK(14, 13), 3, 0 } #define B6 234 -SIG_EXPR_LIST_DECL_SINGLE(USB11BDP, USB11BHID, USB11BHID_DESC); -SIG_EXPR_LIST_DECL_SINGLE(USB2BDDP, USB2BD, USB2BD_DESC); -SIG_EXPR_DECL(USB2BHDP1, USB2BH, USB2BH1_DESC); -SIG_EXPR_DECL(USB2BHDP2, USB2BH, USB2BH2_DESC); -SIG_EXPR_LIST_DECL(USB2BHDP, SIG_EXPR_PTR(USB2BHDP1, USB2BH), +SIG_EXPR_LIST_DECL_SINGLE(B6, USB11BDP, USB11BHID, USB11BHID_DESC); +SIG_EXPR_LIST_DECL_SINGLE(B6, USB2BDDP, USB2BD, USB2BD_DESC); +SIG_EXPR_DECL_SINGLE(USB2BHDP1, USB2BH, USB2BH1_DESC); +SIG_EXPR_DECL_SINGLE(USB2BHDP2, USB2BH, USB2BH2_DESC); +SIG_EXPR_LIST_DECL(USB2BHDP, USB2BH, + SIG_EXPR_PTR(USB2BHDP1, USB2BH), SIG_EXPR_PTR(USB2BHDP2, USB2BH)); -MS_PIN_DECL_(B6, SIG_EXPR_LIST_PTR(USB11BDP), SIG_EXPR_LIST_PTR(USB2BDDP), - SIG_EXPR_LIST_PTR(USB2BHDP)); +SIG_EXPR_LIST_ALIAS(B6, USB2BHDP, USB2BH); +PIN_DECL_(B6, SIG_EXPR_LIST_PTR(B6, USB11BDP), SIG_EXPR_LIST_PTR(B6, USB2BDDP), + SIG_EXPR_LIST_PTR(B6, USB2BHDP)); #define A6 235 -SIG_EXPR_LIST_DECL_SINGLE(USB11BDN, USB11BHID, USB11BHID_DESC); -SIG_EXPR_LIST_DECL_SINGLE(USB2BDN, USB2BD, USB2BD_DESC); -SIG_EXPR_DECL(USB2BHDN1, USB2BH, USB2BH1_DESC); -SIG_EXPR_DECL(USB2BHDN2, USB2BH, USB2BH2_DESC); -SIG_EXPR_LIST_DECL(USB2BHDN, SIG_EXPR_PTR(USB2BHDN1, USB2BH), +SIG_EXPR_LIST_DECL_SINGLE(A6, USB11BDN, USB11BHID, USB11BHID_DESC); +SIG_EXPR_LIST_DECL_SINGLE(A6, USB2BDN, USB2BD, USB2BD_DESC); +SIG_EXPR_DECL_SINGLE(USB2BHDN1, USB2BH, USB2BH1_DESC); +SIG_EXPR_DECL_SINGLE(USB2BHDN2, USB2BH, USB2BH2_DESC); +SIG_EXPR_LIST_DECL(USB2BHDN, USB2BH, + SIG_EXPR_PTR(USB2BHDN1, USB2BH), SIG_EXPR_PTR(USB2BHDN2, USB2BH)); -MS_PIN_DECL_(A6, SIG_EXPR_LIST_PTR(USB11BDN), SIG_EXPR_LIST_PTR(USB2BDN), - SIG_EXPR_LIST_PTR(USB2BHDN)); +SIG_EXPR_LIST_ALIAS(A6, USB2BHDN, USB2BH); +PIN_DECL_(A6, SIG_EXPR_LIST_PTR(A6, USB11BDN), SIG_EXPR_LIST_PTR(A6, USB2BDN), + SIG_EXPR_LIST_PTR(A6, USB2BHDN)); FUNC_GROUP_DECL(USB11BHID, B6, A6); FUNC_GROUP_DECL(USB2BD, B6, A6); @@ -2742,6 +2849,10 @@ static int aspeed_g5_pinctrl_probe(struct platform_device *pdev) static const struct of_device_id aspeed_g5_pinctrl_of_match[] = { { .compatible = "aspeed,ast2500-pinctrl", }, + /* + * The aspeed,g5-pinctrl compatible has been removed the from the + * bindings, but keep the match in case of old devicetrees. + */ { .compatible = "aspeed,g5-pinctrl", }, { }, }; diff --git a/drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c b/drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c new file mode 100644 index 000000000000..648ddb7f038a --- /dev/null +++ b/drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c @@ -0,0 +1,2395 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* Copyright (C) 2019 IBM Corp. */ +#include <linux/bitops.h> +#include <linux/init.h> +#include <linux/io.h> +#include <linux/kernel.h> +#include <linux/mfd/syscon.h> +#include <linux/mutex.h> +#include <linux/of.h> +#include <linux/platform_device.h> +#include <linux/pinctrl/pinctrl.h> +#include <linux/pinctrl/pinmux.h> +#include <linux/string.h> +#include <linux/types.h> + +#include "../core.h" +#include "../pinctrl-utils.h" +#include "pinctrl-aspeed.h" + +#define SCU400 0x400 /* Multi-function Pin Control #1 */ +#define SCU404 0x404 /* Multi-function Pin Control #2 */ +#define SCU410 0x410 /* Multi-function Pin Control #4 */ +#define SCU414 0x414 /* Multi-function Pin Control #5 */ +#define SCU418 0x418 /* Multi-function Pin Control #6 */ +#define SCU41C 0x41C /* Multi-function Pin Control #7 */ +#define SCU430 0x430 /* Multi-function Pin Control #8 */ +#define SCU434 0x434 /* Multi-function Pin Control #9 */ +#define SCU438 0x438 /* Multi-function Pin Control #10 */ +#define SCU450 0x450 /* Multi-function Pin Control #14 */ +#define SCU4B0 0x4B0 /* Multi-function Pin Control #17 */ +#define SCU4B4 0x4B4 /* Multi-function Pin Control #18 */ +#define SCU4B8 0x4B8 /* Multi-function Pin Control #19 */ +#define SCU4BC 0x4BC /* Multi-function Pin Control #20 */ +#define SCU4D4 0x4D4 /* Multi-function Pin Control #22 */ +#define SCU4D8 0x4D8 /* Multi-function Pin Control #23 */ +#define SCU500 0x500 /* Hardware Strap 1 */ +#define SCU510 0x510 /* Hardware Strap 2 */ +#define SCU694 0x694 /* Multi-function Pin Control #25 */ + +#define ASPEED_G6_NR_PINS 248 + +#define M24 0 +SIG_EXPR_LIST_DECL_SESG(M24, MDC3, MDIO3, SIG_DESC_SET(SCU410, 0)); +SIG_EXPR_LIST_DECL_SESG(M24, SCL11, I2C11, SIG_DESC_SET(SCU4B0, 0)); +PIN_DECL_2(M24, GPIOA0, MDC3, SCL11); + +#define M25 1 +SIG_EXPR_LIST_DECL_SESG(M25, MDIO3, MDIO3, SIG_DESC_SET(SCU410, 1)); +SIG_EXPR_LIST_DECL_SESG(M25, SDA11, I2C11, SIG_DESC_SET(SCU4B0, 1)); +PIN_DECL_2(M25, GPIOA1, MDIO3, SDA11); + +FUNC_GROUP_DECL(MDIO3, M24, M25); +FUNC_GROUP_DECL(I2C11, M24, M25); + +#define L26 2 +SIG_EXPR_LIST_DECL_SESG(L26, MDC4, MDIO4, SIG_DESC_SET(SCU410, 2)); +SIG_EXPR_LIST_DECL_SESG(L26, SCL12, I2C12, SIG_DESC_SET(SCU4B0, 2)); +PIN_DECL_2(L26, GPIOA2, MDC4, SCL12); + +#define K24 3 +SIG_EXPR_LIST_DECL_SESG(K24, MDIO4, MDIO4, SIG_DESC_SET(SCU410, 3)); +SIG_EXPR_LIST_DECL_SESG(K24, SDA12, I2C12, SIG_DESC_SET(SCU4B0, 3)); +PIN_DECL_2(K24, GPIOA3, MDIO4, SDA12); + +FUNC_GROUP_DECL(MDIO4, L26, K24); +FUNC_GROUP_DECL(I2C12, L26, K24); + +#define K26 4 +SIG_EXPR_LIST_DECL_SESG(K26, MACLINK1, MACLINK1, SIG_DESC_SET(SCU410, 4)); +SIG_EXPR_LIST_DECL_SESG(K26, SCL13, I2C13, SIG_DESC_SET(SCU4B0, 4)); +PIN_DECL_2(K26, GPIOA4, MACLINK1, SCL13); +FUNC_GROUP_DECL(MACLINK1, K26); + +#define L24 5 +SIG_EXPR_LIST_DECL_SESG(L24, MACLINK2, MACLINK2, SIG_DESC_SET(SCU410, 5)); +SIG_EXPR_LIST_DECL_SESG(L24, SDA13, I2C13, SIG_DESC_SET(SCU4B0, 5)); +PIN_DECL_2(L24, GPIOA5, MACLINK2, SDA13); +FUNC_GROUP_DECL(MACLINK2, L24); + +FUNC_GROUP_DECL(I2C13, K26, L24); + +#define L23 6 +SIG_EXPR_LIST_DECL_SESG(L23, MACLINK3, MACLINK3, SIG_DESC_SET(SCU410, 6)); +SIG_EXPR_LIST_DECL_SESG(L23, SCL14, I2C14, SIG_DESC_SET(SCU4B0, 6)); +PIN_DECL_2(L23, GPIOA6, MACLINK3, SCL14); +FUNC_GROUP_DECL(MACLINK3, L23); + +#define K25 7 +SIG_EXPR_LIST_DECL_SESG(K25, MACLINK4, MACLINK4, SIG_DESC_SET(SCU410, 7)); +SIG_EXPR_LIST_DECL_SESG(K25, SDA14, SDA14, SIG_DESC_SET(SCU4B0, 7)); +PIN_DECL_2(K25, GPIOA7, MACLINK4, SDA14); +FUNC_GROUP_DECL(MACLINK4, K25); + +FUNC_GROUP_DECL(I2C14, L23, K25); + +#define J26 8 +SIG_EXPR_LIST_DECL_SESG(J26, SALT1, SALT1, SIG_DESC_SET(SCU410, 8)); +SIG_EXPR_LIST_DECL_SESG(J26, LHAD0, LPCHC, SIG_DESC_SET(SCU4B0, 8)); +PIN_DECL_2(J26, GPIOB0, SALT1, LHAD0); +FUNC_GROUP_DECL(SALT1, J26); + +#define K23 9 +SIG_EXPR_LIST_DECL_SESG(K23, SALT2, SALT2, SIG_DESC_SET(SCU410, 9)); +SIG_EXPR_LIST_DECL_SESG(K23, LHAD1, LPCHC, SIG_DESC_SET(SCU4B0, 9)); +PIN_DECL_2(K23, GPIOB1, SALT2, LHAD1); +FUNC_GROUP_DECL(SALT2, K23); + +#define H26 10 +SIG_EXPR_LIST_DECL_SESG(H26, SALT3, SALT3, SIG_DESC_SET(SCU410, 10)); +SIG_EXPR_LIST_DECL_SESG(H26, LHAD2, LPCHC, SIG_DESC_SET(SCU4B0, 10)); +PIN_DECL_2(H26, GPIOB2, SALT3, LHAD2); +FUNC_GROUP_DECL(SALT3, H26); + +#define J25 11 +SIG_EXPR_LIST_DECL_SESG(J25, SALT4, SALT4, SIG_DESC_SET(SCU410, 11)); +SIG_EXPR_LIST_DECL_SESG(J25, LHAD3, LPCHC, SIG_DESC_SET(SCU4B0, 11)); +PIN_DECL_2(J25, GPIOB3, SALT4, LHAD3); +FUNC_GROUP_DECL(SALT4, J25); + +#define J23 12 +SIG_EXPR_LIST_DECL_SESG(J23, MDC2, MDIO2, SIG_DESC_SET(SCU410, 12)); +SIG_EXPR_LIST_DECL_SESG(J23, LHCLK, LPCHC, SIG_DESC_SET(SCU4B0, 12)); +PIN_DECL_2(J23, GPIOB4, MDC2, LHCLK); + +#define G26 13 +SIG_EXPR_LIST_DECL_SESG(G26, MDIO2, MDIO2, SIG_DESC_SET(SCU410, 13)); +SIG_EXPR_LIST_DECL_SESG(G26, LHFRAME, LPCHC, SIG_DESC_SET(SCU4B0, 13)); +PIN_DECL_2(G26, GPIOB5, MDIO2, LHFRAME); + +FUNC_GROUP_DECL(MDIO2, J23, G26); + +#define H25 14 +SIG_EXPR_LIST_DECL_SESG(H25, TXD4, TXD4, SIG_DESC_SET(SCU410, 14)); +SIG_EXPR_LIST_DECL_SESG(H25, LHSIRQ, LHSIRQ, SIG_DESC_SET(SCU4B0, 14)); +PIN_DECL_2(H25, GPIOB6, TXD4, LHSIRQ); +FUNC_GROUP_DECL(TXD4, H25); +FUNC_GROUP_DECL(LHSIRQ, H25); + +#define J24 15 +SIG_EXPR_LIST_DECL_SESG(J24, RXD4, RXD4, SIG_DESC_SET(SCU410, 15)); +SIG_EXPR_LIST_DECL_SESG(J24, LHRST, LPCHC, SIG_DESC_SET(SCU4B0, 15)); +PIN_DECL_2(J24, GPIOB7, RXD4, LHRST); +FUNC_GROUP_DECL(RXD4, J24); + +FUNC_GROUP_DECL(LPCHC, J26, K23, H26, J25, J23, G26, H25, J24); + +#define H24 16 +SIG_EXPR_LIST_DECL_SESG(H24, RGMII3TXCK, RGMII3, SIG_DESC_SET(SCU410, 16), + SIG_DESC_SET(SCU510, 0)); +SIG_EXPR_LIST_DECL_SESG(H24, RMII3RCLKO, RMII3, SIG_DESC_SET(SCU410, 16), + SIG_DESC_CLEAR(SCU510, 0)); +PIN_DECL_2(H24, GPIOC0, RGMII3TXCK, RMII3RCLKO); + +#define J22 17 +SIG_EXPR_LIST_DECL_SESG(J22, RGMII3TXCTL, RGMII3, SIG_DESC_SET(SCU410, 17), + SIG_DESC_SET(SCU510, 0)); +SIG_EXPR_LIST_DECL_SESG(J22, RMII3TXEN, RMII3, SIG_DESC_SET(SCU410, 17), + SIG_DESC_CLEAR(SCU510, 0)); +PIN_DECL_2(J22, GPIOC1, RGMII3TXCTL, RMII3TXEN); + +#define H22 18 +SIG_EXPR_LIST_DECL_SESG(H22, RGMII3TXD0, RGMII3, SIG_DESC_SET(SCU410, 18), + SIG_DESC_SET(SCU510, 0)); +SIG_EXPR_LIST_DECL_SESG(H22, RMII3TXD0, RMII3, SIG_DESC_SET(SCU410, 18), + SIG_DESC_CLEAR(SCU510, 0)); +PIN_DECL_2(H22, GPIOC2, RGMII3TXD0, RMII3TXD0); + +#define H23 19 +SIG_EXPR_LIST_DECL_SESG(H23, RGMII3TXD1, RGMII3, SIG_DESC_SET(SCU410, 19), + SIG_DESC_SET(SCU510, 0)); +SIG_EXPR_LIST_DECL_SESG(H23, RMII3TXD1, RMII3, SIG_DESC_SET(SCU410, 19), + SIG_DESC_CLEAR(SCU510, 0)); +PIN_DECL_2(H23, GPIOC3, RGMII3TXD1, RMII3TXD1); + +#define G22 20 +SIG_EXPR_LIST_DECL_SESG(G22, RGMII3TXD2, RGMII3, SIG_DESC_SET(SCU410, 20), + SIG_DESC_SET(SCU510, 0)); +PIN_DECL_1(G22, GPIOC4, RGMII3TXD2); + +#define F22 21 +SIG_EXPR_LIST_DECL_SESG(F22, RGMII3TXD3, RGMII3, SIG_DESC_SET(SCU410, 21), + SIG_DESC_SET(SCU510, 0)); +PIN_DECL_1(F22, GPIOC5, RGMII3TXD3); + +#define G23 22 +SIG_EXPR_LIST_DECL_SESG(G23, RGMII3RXCK, RGMII3, SIG_DESC_SET(SCU410, 22), + SIG_DESC_SET(SCU510, 0)); +SIG_EXPR_LIST_DECL_SESG(G23, RMII3RCLKI, RMII3, SIG_DESC_SET(SCU410, 22), + SIG_DESC_CLEAR(SCU510, 0)); +PIN_DECL_2(G23, GPIOC6, RGMII3RXCK, RMII3RCLKI); + +#define G24 23 +SIG_EXPR_LIST_DECL_SESG(G24, RGMII3RXCTL, RGMII3, SIG_DESC_SET(SCU410, 23), + SIG_DESC_SET(SCU510, 0)); +PIN_DECL_1(G24, GPIOC7, RGMII3RXCTL); + +#define F23 24 +SIG_EXPR_LIST_DECL_SESG(F23, RGMII3RXD0, RGMII3, SIG_DESC_SET(SCU410, 24), + SIG_DESC_SET(SCU510, 0)); +SIG_EXPR_LIST_DECL_SESG(F23, RMII3RXD0, RMII3, SIG_DESC_SET(SCU410, 24), + SIG_DESC_CLEAR(SCU510, 0)); +PIN_DECL_2(F23, GPIOD0, RGMII3RXD0, RMII3RXD0); + +#define F26 25 +SIG_EXPR_LIST_DECL_SESG(F26, RGMII3RXD1, RGMII3, SIG_DESC_SET(SCU410, 25), + SIG_DESC_SET(SCU510, 0)); +SIG_EXPR_LIST_DECL_SESG(F26, RMII3RXD1, RMII3, SIG_DESC_SET(SCU410, 25), + SIG_DESC_CLEAR(SCU510, 0)); +PIN_DECL_2(F26, GPIOD1, RGMII3RXD1, RMII3RXD1); + +#define F25 26 +SIG_EXPR_LIST_DECL_SESG(F25, RGMII3RXD2, RGMII3, SIG_DESC_SET(SCU410, 26), + SIG_DESC_SET(SCU510, 0)); +SIG_EXPR_LIST_DECL_SESG(F25, RMII3CRSDV, RMII3, SIG_DESC_SET(SCU410, 26), + SIG_DESC_CLEAR(SCU510, 0)); +PIN_DECL_2(F25, GPIOD2, RGMII3RXD2, RMII3CRSDV); + +#define E26 27 +SIG_EXPR_LIST_DECL_SESG(E26, RGMII3RXD3, RGMII3, SIG_DESC_SET(SCU410, 27), + SIG_DESC_SET(SCU510, 0)); +SIG_EXPR_LIST_DECL_SESG(E26, RMII3RXER, RMII3, SIG_DESC_SET(SCU410, 27), + SIG_DESC_CLEAR(SCU510, 0)); +PIN_DECL_2(E26, GPIOD3, RGMII3RXD3, RMII3RXER); + +FUNC_GROUP_DECL(RGMII3, H24, J22, H22, H23, G22, F22, G23, G24, F23, F26, F25, + E26); +FUNC_GROUP_DECL(RMII3, H24, J22, H22, H23, G23, F23, F26, F25, E26); + +#define F24 28 +SIG_EXPR_LIST_DECL_SESG(F24, NCTS3, NCTS3, SIG_DESC_SET(SCU410, 28)); +SIG_EXPR_LIST_DECL_SESG(F24, RGMII4TXCK, RGMII4, SIG_DESC_SET(SCU4B0, 28), + SIG_DESC_SET(SCU510, 1)); +SIG_EXPR_LIST_DECL_SESG(F24, RMII4RCLKO, RMII4, SIG_DESC_SET(SCU4B0, 28), + SIG_DESC_CLEAR(SCU510, 1)); +PIN_DECL_3(F24, GPIOD4, NCTS3, RGMII4TXCK, RMII4RCLKO); +FUNC_GROUP_DECL(NCTS3, F24); + +#define E23 29 +SIG_EXPR_LIST_DECL_SESG(E23, NDCD3, NDCD3, SIG_DESC_SET(SCU410, 29)); +SIG_EXPR_LIST_DECL_SESG(E23, RGMII4TXCTL, RGMII4, SIG_DESC_SET(SCU4B0, 29), + SIG_DESC_SET(SCU510, 1)); +SIG_EXPR_LIST_DECL_SESG(E23, RMII4TXEN, RMII4, SIG_DESC_SET(SCU4B0, 29), + SIG_DESC_CLEAR(SCU510, 1)); +PIN_DECL_3(E23, GPIOD5, NDCD3, RGMII4TXCTL, RMII4TXEN); +FUNC_GROUP_DECL(NDCD3, E23); + +#define E24 30 +SIG_EXPR_LIST_DECL_SESG(E24, NDSR3, NDSR3, SIG_DESC_SET(SCU410, 30)); +SIG_EXPR_LIST_DECL_SESG(E24, RGMII4TXD0, RGMII4, SIG_DESC_SET(SCU4B0, 30), + SIG_DESC_SET(SCU510, 1)); +SIG_EXPR_LIST_DECL_SESG(E24, RMII4TXD0, RMII4, SIG_DESC_SET(SCU4B0, 30), + SIG_DESC_CLEAR(SCU510, 1)); +PIN_DECL_3(E24, GPIOD6, NDSR3, RGMII4TXD0, RMII4TXD0); +FUNC_GROUP_DECL(NDSR3, E24); + +#define E25 31 +SIG_EXPR_LIST_DECL_SESG(E25, NRI3, NRI3, SIG_DESC_SET(SCU410, 31)); +SIG_EXPR_LIST_DECL_SESG(E25, RGMII4TXD1, RGMII4, SIG_DESC_SET(SCU4B0, 31), + SIG_DESC_SET(SCU510, 1)); +SIG_EXPR_LIST_DECL_SESG(E25, RMII4TXD1, RMII4, SIG_DESC_SET(SCU4B0, 31), + SIG_DESC_CLEAR(SCU510, 1)); +PIN_DECL_3(E25, GPIOD7, NRI3, RGMII4TXD1, RMII4TXD1); +FUNC_GROUP_DECL(NRI3, E25); + +#define D26 32 +SIG_EXPR_LIST_DECL_SESG(D26, NDTR3, NDTR3, SIG_DESC_SET(SCU414, 0)); +SIG_EXPR_LIST_DECL_SESG(D26, RGMII4TXD2, RGMII4, SIG_DESC_SET(SCU4B4, 0), + SIG_DESC_SET(SCU510, 1)); +PIN_DECL_2(D26, GPIOE0, NDTR3, RGMII4TXD2); +FUNC_GROUP_DECL(NDTR3, D26); + +#define D24 33 +SIG_EXPR_LIST_DECL_SESG(D24, NRTS3, NRTS3, SIG_DESC_SET(SCU414, 1)); +SIG_EXPR_LIST_DECL_SESG(D24, RGMII4TXD3, RGMII4, SIG_DESC_SET(SCU4B4, 1), + SIG_DESC_SET(SCU510, 1)); +PIN_DECL_2(D24, GPIOE1, NRTS3, RGMII4TXD3); +FUNC_GROUP_DECL(NRTS3, D24); + +#define C25 34 +SIG_EXPR_LIST_DECL_SESG(C25, NCTS4, NCTS4, SIG_DESC_SET(SCU414, 2)); +SIG_EXPR_LIST_DECL_SESG(C25, RGMII4RXCK, RGMII4, SIG_DESC_SET(SCU4B4, 2), + SIG_DESC_SET(SCU510, 1)); +SIG_EXPR_LIST_DECL_SESG(C25, RMII4RCLKI, RMII4, SIG_DESC_SET(SCU4B4, 2), + SIG_DESC_CLEAR(SCU510, 1)); +PIN_DECL_3(C25, GPIOE2, NCTS4, RGMII4RXCK, RMII4RCLKI); +FUNC_GROUP_DECL(NCTS4, C25); + +#define C26 35 +SIG_EXPR_LIST_DECL_SESG(C26, NDCD4, NDCD4, SIG_DESC_SET(SCU414, 3)); +SIG_EXPR_LIST_DECL_SESG(C26, RGMII4RXCTL, RGMII4, SIG_DESC_SET(SCU4B4, 3), + SIG_DESC_SET(SCU510, 1)); +PIN_DECL_2(C26, GPIOE3, NDCD4, RGMII4RXCTL); +FUNC_GROUP_DECL(NDCD4, C26); + +#define C24 36 +SIG_EXPR_LIST_DECL_SESG(C24, NDSR4, NDSR4, SIG_DESC_SET(SCU414, 4)); +SIG_EXPR_LIST_DECL_SESG(C24, RGMII4RXD0, RGMII4, SIG_DESC_SET(SCU4B4, 4), + SIG_DESC_SET(SCU510, 1)); +SIG_EXPR_LIST_DECL_SESG(C24, RMII4RXD0, RMII4, SIG_DESC_SET(SCU4B4, 4), + SIG_DESC_CLEAR(SCU510, 1)); +PIN_DECL_3(C24, GPIOE4, NDSR4, RGMII4RXD0, RMII4RXD0); +FUNC_GROUP_DECL(NDSR4, C24); + +#define B26 37 +SIG_EXPR_LIST_DECL_SESG(B26, NRI4, NRI4, SIG_DESC_SET(SCU414, 5)); +SIG_EXPR_LIST_DECL_SESG(B26, RGMII4RXD1, RGMII4, SIG_DESC_SET(SCU4B4, 5), + SIG_DESC_SET(SCU510, 1)); +SIG_EXPR_LIST_DECL_SESG(B26, RMII4RXD1, RMII4, SIG_DESC_SET(SCU4B4, 5), + SIG_DESC_CLEAR(SCU510, 1)); +PIN_DECL_3(B26, GPIOE5, NRI4, RGMII4RXD1, RMII4RXD1); +FUNC_GROUP_DECL(NRI4, B26); + +#define B25 38 +SIG_EXPR_LIST_DECL_SESG(B25, NDTR4, NDTR4, SIG_DESC_SET(SCU414, 6)); +SIG_EXPR_LIST_DECL_SESG(B25, RGMII4RXD2, RGMII4, SIG_DESC_SET(SCU4B4, 6), + SIG_DESC_SET(SCU510, 1)); +SIG_EXPR_LIST_DECL_SESG(B25, RMII4CRSDV, RMII4, SIG_DESC_SET(SCU4B4, 6), + SIG_DESC_CLEAR(SCU510, 1)); +PIN_DECL_3(B25, GPIOE6, NDTR4, RGMII4RXD2, RMII4CRSDV); +FUNC_GROUP_DECL(NDTR4, B25); + +#define B24 39 +SIG_EXPR_LIST_DECL_SESG(B24, NRTS4, NRTS4, SIG_DESC_SET(SCU414, 7)); +SIG_EXPR_LIST_DECL_SESG(B24, RGMII4RXD3, RGMII4, SIG_DESC_SET(SCU4B4, 7), + SIG_DESC_SET(SCU510, 1)); +SIG_EXPR_LIST_DECL_SESG(B24, RMII4RXER, RMII4, SIG_DESC_SET(SCU4B4, 7), + SIG_DESC_CLEAR(SCU510, 1)); +PIN_DECL_3(B24, GPIOE7, NRTS4, RGMII4RXD3, RMII4RXER); +FUNC_GROUP_DECL(NRTS4, B24); + +FUNC_GROUP_DECL(RGMII4, F24, E23, E24, E25, D26, D24, C25, C26, C24, B26, B25, + B24); +FUNC_GROUP_DECL(RMII4, F24, E23, E24, E25, C25, C24, B26, B25, B24); + +#define D22 40 +SIG_EXPR_LIST_DECL_SESG(D22, SD1CLK, SD1, SIG_DESC_SET(SCU414, 8)); +SIG_EXPR_LIST_DECL_SEMG(D22, PWM8, PWM8G0, PWM8, SIG_DESC_SET(SCU414, 8)); +PIN_DECL_2(D22, GPIOF0, SD1CLK, PWM8); +GROUP_DECL(PWM8G0, D22); + +#define E22 41 +SIG_EXPR_LIST_DECL_SESG(E22, SD1CMD, SD1, SIG_DESC_SET(SCU414, 9)); +SIG_EXPR_LIST_DECL_SEMG(E22, PWM9, PWM9G0, PWM9, SIG_DESC_SET(SCU4B4, 9)); +PIN_DECL_2(E22, GPIOF1, SD1CMD, PWM9); +GROUP_DECL(PWM9G0, E22); + +#define D23 42 +SIG_EXPR_LIST_DECL_SESG(D23, SD1DAT0, SD1, SIG_DESC_SET(SCU414, 10)); +SIG_EXPR_LIST_DECL_SEMG(D23, PWM10, PWM10G0, PWM10, SIG_DESC_SET(SCU4B4, 10)); +PIN_DECL_2(D23, GPIOF2, SD1DAT0, PWM10); +GROUP_DECL(PWM10G0, D23); + +#define C23 43 +SIG_EXPR_LIST_DECL_SESG(C23, SD1DAT1, SD1, SIG_DESC_SET(SCU414, 11)); +SIG_EXPR_LIST_DECL_SEMG(C23, PWM11, PWM11G0, PWM11, SIG_DESC_SET(SCU4B4, 11)); +PIN_DECL_2(C23, GPIOF3, SD1DAT1, PWM11); +GROUP_DECL(PWM11G0, C23); + +#define C22 44 +SIG_EXPR_LIST_DECL_SESG(C22, SD1DAT2, SD1, SIG_DESC_SET(SCU414, 12)); +SIG_EXPR_LIST_DECL_SEMG(C22, PWM12, PWM12G0, PWM12, SIG_DESC_SET(SCU4B4, 12)); +PIN_DECL_2(C22, GPIOF4, SD1DAT2, PWM12); +GROUP_DECL(PWM12G0, C22); + +#define A25 45 +SIG_EXPR_LIST_DECL_SESG(A25, SD1DAT3, SD1, SIG_DESC_SET(SCU414, 13)); +SIG_EXPR_LIST_DECL_SEMG(A25, PWM13, PWM13G0, PWM13, SIG_DESC_SET(SCU4B4, 13)); +PIN_DECL_2(A25, GPIOF5, SD1DAT3, PWM13); +GROUP_DECL(PWM13G0, A25); + +#define A24 46 +SIG_EXPR_LIST_DECL_SESG(A24, SD1CD, SD1, SIG_DESC_SET(SCU414, 14)); +SIG_EXPR_LIST_DECL_SEMG(A24, PWM14, PWM14G0, PWM14, SIG_DESC_SET(SCU4B4, 14)); +PIN_DECL_2(A24, GPIOF6, SD1CD, PWM14); +GROUP_DECL(PWM14G0, A24); + +#define A23 47 +SIG_EXPR_LIST_DECL_SESG(A23, SD1WP, SD1, SIG_DESC_SET(SCU414, 15)); +SIG_EXPR_LIST_DECL_SEMG(A23, PWM15, PWM15G0, PWM15, SIG_DESC_SET(SCU4B4, 15)); +PIN_DECL_2(A23, GPIOF7, SD1WP, PWM15); +GROUP_DECL(PWM15G0, A23); + +FUNC_GROUP_DECL(SD1, D22, E22, D23, C23, C22, A25, A24, A23); + +#define E21 48 +SIG_EXPR_LIST_DECL_SESG(E21, TXD6, UART6, SIG_DESC_SET(SCU414, 16)); +SIG_EXPR_LIST_DECL_SESG(E21, SD2CLK, SD2, SIG_DESC_SET(SCU4B4, 16), + SIG_DESC_SET(SCU450, 1)); +SIG_EXPR_LIST_DECL_SEMG(E21, SALT9, SALT9G0, SALT9, SIG_DESC_SET(SCU694, 16)); +PIN_DECL_3(E21, GPIOG0, TXD6, SD2CLK, SALT9); +GROUP_DECL(SALT9G0, E21); + +#define B22 49 +SIG_EXPR_LIST_DECL_SESG(B22, RXD6, UART6, SIG_DESC_SET(SCU414, 17)); +SIG_EXPR_LIST_DECL_SESG(B22, SD2CMD, SD2, SIG_DESC_SET(SCU4B4, 17), + SIG_DESC_SET(SCU450, 1)); +SIG_EXPR_LIST_DECL_SEMG(B22, SALT10, SALT10G0, SALT10, + SIG_DESC_SET(SCU694, 17)); +PIN_DECL_3(B22, GPIOG1, RXD6, SD2CMD, SALT10); +GROUP_DECL(SALT10G0, B22); + +FUNC_GROUP_DECL(UART6, E21, B22); + +#define C21 50 +SIG_EXPR_LIST_DECL_SESG(C21, TXD7, UART7, SIG_DESC_SET(SCU414, 18)); +SIG_EXPR_LIST_DECL_SESG(C21, SD2DAT0, SD2, SIG_DESC_SET(SCU4B4, 18), + SIG_DESC_SET(SCU450, 1)); +SIG_EXPR_LIST_DECL_SEMG(C21, SALT11, SALT11G0, SALT11, + SIG_DESC_SET(SCU694, 18)); +PIN_DECL_3(C21, GPIOG2, TXD7, SD2DAT0, SALT11); +GROUP_DECL(SALT11G0, C21); + +#define A22 51 +SIG_EXPR_LIST_DECL_SESG(A22, RXD7, UART7, SIG_DESC_SET(SCU414, 19)); +SIG_EXPR_LIST_DECL_SESG(A22, SD2DAT1, SD2, SIG_DESC_SET(SCU4B4, 19), + SIG_DESC_SET(SCU450, 1)); +SIG_EXPR_LIST_DECL_SEMG(A22, SALT12, SALT12G0, SALT12, + SIG_DESC_SET(SCU694, 19)); +PIN_DECL_3(A22, GPIOG3, RXD7, SD2DAT1, SALT12); +GROUP_DECL(SALT12G0, A22); + +FUNC_GROUP_DECL(UART7, C21, A22); + +#define A21 52 +SIG_EXPR_LIST_DECL_SESG(A21, TXD8, UART8, SIG_DESC_SET(SCU414, 20)); +SIG_EXPR_LIST_DECL_SESG(A21, SD2DAT2, SD2, SIG_DESC_SET(SCU4B4, 20), + SIG_DESC_SET(SCU450, 1)); +SIG_EXPR_LIST_DECL_SEMG(A21, SALT13, SALT13G0, SALT13, + SIG_DESC_SET(SCU694, 20)); +PIN_DECL_3(A21, GPIOG4, TXD8, SD2DAT2, SALT13); +GROUP_DECL(SALT13G0, A21); + +#define E20 53 +SIG_EXPR_LIST_DECL_SESG(E20, RXD8, UART8, SIG_DESC_SET(SCU414, 21)); +SIG_EXPR_LIST_DECL_SESG(E20, SD2DAT3, SD2, SIG_DESC_SET(SCU4B4, 21), + SIG_DESC_SET(SCU450, 1)); +SIG_EXPR_LIST_DECL_SEMG(E20, SALT14, SALT14G0, SALT14, + SIG_DESC_SET(SCU694, 21)); +PIN_DECL_3(E20, GPIOG5, RXD8, SD2DAT3, SALT14); +GROUP_DECL(SALT14G0, E20); + +FUNC_GROUP_DECL(UART8, A21, E20); + +#define D21 54 +SIG_EXPR_LIST_DECL_SESG(D21, TXD9, UART9, SIG_DESC_SET(SCU414, 22)); +SIG_EXPR_LIST_DECL_SESG(D21, SD2CD, SD2, SIG_DESC_SET(SCU4B4, 22), + SIG_DESC_SET(SCU450, 1)); +SIG_EXPR_LIST_DECL_SEMG(D21, SALT15, SALT15G0, SALT15, + SIG_DESC_SET(SCU694, 22)); +PIN_DECL_3(D21, GPIOG6, TXD9, SD2CD, SALT15); +GROUP_DECL(SALT15G0, D21); + +#define B21 55 +SIG_EXPR_LIST_DECL_SESG(B21, RXD9, UART9, SIG_DESC_SET(SCU414, 23)); +SIG_EXPR_LIST_DECL_SESG(B21, SD2WP, SD2, SIG_DESC_SET(SCU4B4, 23), + SIG_DESC_SET(SCU450, 1)); +SIG_EXPR_LIST_DECL_SEMG(B21, SALT16, SALT16G0, SALT16, + SIG_DESC_SET(SCU694, 23)); +PIN_DECL_3(B21, GPIOG7, RXD9, SD2WP, SALT16); +GROUP_DECL(SALT16G0, B21); + +FUNC_GROUP_DECL(UART9, D21, B21); + +FUNC_GROUP_DECL(SD2, E21, B22, C21, A22, A21, E20, D21, B21); + +#define A18 56 +SIG_EXPR_LIST_DECL_SESG(A18, SGPM1CLK, SGPM1, SIG_DESC_SET(SCU414, 24)); +PIN_DECL_1(A18, GPIOH0, SGPM1CLK); + +#define B18 57 +SIG_EXPR_LIST_DECL_SESG(B18, SGPM1LD, SGPM1, SIG_DESC_SET(SCU414, 25)); +PIN_DECL_1(B18, GPIOH1, SGPM1LD); + +#define C18 58 +SIG_EXPR_LIST_DECL_SESG(C18, SGPM1O, SGPM1, SIG_DESC_SET(SCU414, 26)); +PIN_DECL_1(C18, GPIOH2, SGPM1O); + +#define A17 59 +SIG_EXPR_LIST_DECL_SESG(A17, SGPM1I, SGPM1, SIG_DESC_SET(SCU414, 27)); +PIN_DECL_1(A17, GPIOH3, SGPM1I); + +FUNC_GROUP_DECL(SGPM1, A18, B18, C18, A17); + +#define D18 60 +SIG_EXPR_LIST_DECL_SESG(D18, SGPS1CK, SGPS1, SIG_DESC_SET(SCU414, 28)); +SIG_EXPR_LIST_DECL_SESG(D18, SCL15, I2C15, SIG_DESC_SET(SCU4B4, 28)); +PIN_DECL_2(D18, GPIOH4, SGPS1CK, SCL15); + +#define B17 61 +SIG_EXPR_LIST_DECL_SESG(B17, SGPS1LD, SGPS1, SIG_DESC_SET(SCU414, 29)); +SIG_EXPR_LIST_DECL_SESG(B17, SDA15, I2C15, SIG_DESC_SET(SCU4B4, 29)); +PIN_DECL_2(B17, GPIOH5, SGPS1LD, SDA15); + +FUNC_GROUP_DECL(I2C15, D18, B17); + +#define C17 62 +SIG_EXPR_LIST_DECL_SESG(C17, SGPS1O, SGPS1, SIG_DESC_SET(SCU414, 30)); +SIG_EXPR_LIST_DECL_SESG(C17, SCL16, I2C16, SIG_DESC_SET(SCU4B4, 30)); +PIN_DECL_2(C17, GPIOH6, SGPS1O, SCL16); + +#define E18 63 +SIG_EXPR_LIST_DECL_SESG(E18, SGPS1I, SGPS1, SIG_DESC_SET(SCU414, 31)); +SIG_EXPR_LIST_DECL_SESG(E18, SDA16, I2C16, SIG_DESC_SET(SCU4B4, 31)); +PIN_DECL_2(E18, GPIOH7, SGPS1I, SDA16); + +FUNC_GROUP_DECL(I2C16, C17, E18); +FUNC_GROUP_DECL(SGPS1, D18, B17, C17, E18); + +#define D17 64 +SIG_EXPR_LIST_DECL_SESG(D17, MTRSTN, JTAGM, SIG_DESC_SET(SCU418, 0)); +SIG_EXPR_LIST_DECL_SEMG(D17, TXD12, UART12G0, UART12, SIG_DESC_SET(SCU4B8, 0)); +PIN_DECL_2(D17, GPIOI0, MTRSTN, TXD12); + +#define A16 65 +SIG_EXPR_LIST_DECL_SESG(A16, MTDI, JTAGM, SIG_DESC_SET(SCU418, 1)); +SIG_EXPR_LIST_DECL_SEMG(A16, RXD12, UART12G0, UART12, SIG_DESC_SET(SCU4B8, 1)); +PIN_DECL_2(A16, GPIOI1, MTDI, RXD12); + +GROUP_DECL(UART12G0, D17, A16); + +#define E17 66 +SIG_EXPR_LIST_DECL_SESG(E17, MTCK, JTAGM, SIG_DESC_SET(SCU418, 2)); +SIG_EXPR_LIST_DECL_SEMG(E17, TXD13, UART13G0, UART13, SIG_DESC_SET(SCU4B8, 2)); +PIN_DECL_2(E17, GPIOI2, MTCK, TXD13); + +#define D16 67 +SIG_EXPR_LIST_DECL_SESG(D16, MTMS, JTAGM, SIG_DESC_SET(SCU418, 3)); +SIG_EXPR_LIST_DECL_SEMG(D16, RXD13, UART13G0, UART13, SIG_DESC_SET(SCU4B8, 3)); +PIN_DECL_2(D16, GPIOI3, MTMS, RXD13); + +GROUP_DECL(UART13G0, E17, D16); + +#define C16 68 +SIG_EXPR_LIST_DECL_SESG(C16, MTDO, JTAGM, SIG_DESC_SET(SCU418, 4)); +PIN_DECL_1(C16, GPIOI4, MTDO); + +FUNC_GROUP_DECL(JTAGM, D17, A16, E17, D16, C16); + +#define E16 69 +SIG_EXPR_LIST_DECL_SESG(E16, SIOPBO, SIOPBO, SIG_DESC_SET(SCU418, 5)); +PIN_DECL_1(E16, GPIOI5, SIOPBO); +FUNC_GROUP_DECL(SIOPBO, E16); + +#define B16 70 +SIG_EXPR_LIST_DECL_SESG(B16, SIOPBI, SIOPBI, SIG_DESC_SET(SCU418, 6)); +PIN_DECL_1(B16, GPIOI6, SIOPBI); +FUNC_GROUP_DECL(SIOPBI, B16); + +#define A15 71 +SIG_EXPR_LIST_DECL_SESG(A15, BMCINT, BMCINT, SIG_DESC_SET(SCU418, 7)); +SIG_EXPR_LIST_DECL_SESG(A15, SIOSCI, SIOSCI, SIG_DESC_SET(SCU4B8, 7)); +PIN_DECL_2(A15, GPIOI7, BMCINT, SIOSCI); +FUNC_GROUP_DECL(BMCINT, A15); +FUNC_GROUP_DECL(SIOSCI, A15); + +#define B20 72 +SIG_EXPR_LIST_DECL_SEMG(B20, I3C3SCL, HVI3C3, I3C3, SIG_DESC_SET(SCU418, 8)); +SIG_EXPR_LIST_DECL_SESG(B20, SCL1, I2C1, SIG_DESC_SET(SCU4B8, 8)); +PIN_DECL_2(B20, GPIOJ0, I3C3SCL, SCL1); + +#define A20 73 +SIG_EXPR_LIST_DECL_SEMG(A20, I3C3SDA, HVI3C3, I3C3, SIG_DESC_SET(SCU418, 9)); +SIG_EXPR_LIST_DECL_SESG(A20, SDA1, I2C1, SIG_DESC_SET(SCU4B8, 9)); +PIN_DECL_2(A20, GPIOJ1, I3C3SDA, SDA1); + +GROUP_DECL(HVI3C3, B20, A20); +FUNC_GROUP_DECL(I2C1, B20, A20); + +#define E19 74 +SIG_EXPR_LIST_DECL_SEMG(E19, I3C4SCL, HVI3C4, I3C4, SIG_DESC_SET(SCU418, 10)); +SIG_EXPR_LIST_DECL_SESG(E19, SCL2, I2C2, SIG_DESC_SET(SCU4B8, 10)); +PIN_DECL_2(E19, GPIOJ2, I3C4SCL, SCL2); + +#define D20 75 +SIG_EXPR_LIST_DECL_SEMG(D20, I3C4SDA, HVI3C4, I3C4, SIG_DESC_SET(SCU418, 11)); +SIG_EXPR_LIST_DECL_SESG(D20, SDA2, I2C2, SIG_DESC_SET(SCU4B8, 11)); +PIN_DECL_2(D20, GPIOJ3, I3C4SDA, SDA2); + +GROUP_DECL(HVI3C4, E19, D20); +FUNC_GROUP_DECL(I2C2, E19, D20); + +#define C19 76 +SIG_EXPR_LIST_DECL_SESG(C19, I3C5SCL, I3C5, SIG_DESC_SET(SCU418, 12)); +SIG_EXPR_LIST_DECL_SESG(C19, SCL3, I2C3, SIG_DESC_SET(SCU4B8, 12)); +PIN_DECL_2(C19, GPIOJ4, I3C5SCL, SCL3); + +#define A19 77 +SIG_EXPR_LIST_DECL_SESG(A19, I3C5SDA, I3C5, SIG_DESC_SET(SCU418, 13)); +SIG_EXPR_LIST_DECL_SESG(A19, SDA3, I2C3, SIG_DESC_SET(SCU4B8, 13)); +PIN_DECL_2(A19, GPIOJ5, I3C5SDA, SDA3); + +FUNC_GROUP_DECL(I3C5, C19, A19); +FUNC_GROUP_DECL(I2C3, C19, A19); + +#define C20 78 +SIG_EXPR_LIST_DECL_SESG(C20, I3C6SCL, I3C6, SIG_DESC_SET(SCU418, 14)); +SIG_EXPR_LIST_DECL_SESG(C20, SCL4, I2C4, SIG_DESC_SET(SCU4B8, 14)); +PIN_DECL_2(C20, GPIOJ6, I3C6SCL, SCL4); + +#define D19 79 +SIG_EXPR_LIST_DECL_SESG(D19, I3C6SDA, I3C6, SIG_DESC_SET(SCU418, 15)); +SIG_EXPR_LIST_DECL_SESG(D19, SDA4, I2C4, SIG_DESC_SET(SCU4B8, 15)); +PIN_DECL_2(D19, GPIOJ7, I3C6SDA, SDA4); + +FUNC_GROUP_DECL(I3C6, C20, D19); +FUNC_GROUP_DECL(I2C4, C20, D19); + +#define A11 80 +SIG_EXPR_LIST_DECL_SESG(A11, SCL5, I2C5, SIG_DESC_SET(SCU418, 16)); +PIN_DECL_1(A11, GPIOK0, SCL5); + +#define C11 81 +SIG_EXPR_LIST_DECL_SESG(C11, SDA5, I2C5, SIG_DESC_SET(SCU418, 17)); +PIN_DECL_1(C11, GPIOK1, SDA5); + +FUNC_GROUP_DECL(I2C5, A11, C11); + +#define D12 82 +SIG_EXPR_LIST_DECL_SESG(D12, SCL6, I2C6, SIG_DESC_SET(SCU418, 18)); +PIN_DECL_1(D12, GPIOK2, SCL6); + +#define E13 83 +SIG_EXPR_LIST_DECL_SESG(E13, SDA6, I2C6, SIG_DESC_SET(SCU418, 19)); +PIN_DECL_1(E13, GPIOK3, SDA6); + +FUNC_GROUP_DECL(I2C6, D12, E13); + +#define D11 84 +SIG_EXPR_LIST_DECL_SESG(D11, SCL7, I2C7, SIG_DESC_SET(SCU418, 20)); +PIN_DECL_1(D11, GPIOK4, SCL7); + +#define E11 85 +SIG_EXPR_LIST_DECL_SESG(E11, SDA7, I2C7, SIG_DESC_SET(SCU418, 21)); +PIN_DECL_1(E11, GPIOK5, SDA7); + +FUNC_GROUP_DECL(I2C7, D11, E11); + +#define F13 86 +SIG_EXPR_LIST_DECL_SESG(F13, SCL8, I2C8, SIG_DESC_SET(SCU418, 22)); +PIN_DECL_1(F13, GPIOK6, SCL8); + +#define E12 87 +SIG_EXPR_LIST_DECL_SESG(E12, SDA8, I2C8, SIG_DESC_SET(SCU418, 23)); +PIN_DECL_1(E12, GPIOK7, SDA8); + +FUNC_GROUP_DECL(I2C8, F13, E12); + +#define D15 88 +SIG_EXPR_LIST_DECL_SESG(D15, SCL9, I2C9, SIG_DESC_SET(SCU418, 24)); +PIN_DECL_1(D15, GPIOL0, SCL9); + +#define A14 89 +SIG_EXPR_LIST_DECL_SESG(A14, SDA9, I2C9, SIG_DESC_SET(SCU418, 25)); +PIN_DECL_1(A14, GPIOL1, SDA9); + +FUNC_GROUP_DECL(I2C9, D15, A14); + +#define E15 90 +SIG_EXPR_LIST_DECL_SESG(E15, SCL10, I2C10, SIG_DESC_SET(SCU418, 26)); +PIN_DECL_1(E15, GPIOL2, SCL10); + +#define A13 91 +SIG_EXPR_LIST_DECL_SESG(A13, SDA10, I2C10, SIG_DESC_SET(SCU418, 27)); +PIN_DECL_1(A13, GPIOL3, SDA10); + +FUNC_GROUP_DECL(I2C10, E15, A13); + +#define C15 92 +SSSF_PIN_DECL(C15, GPIOL4, TXD3, SIG_DESC_SET(SCU418, 28)); + +#define F15 93 +SSSF_PIN_DECL(F15, GPIOL5, RXD3, SIG_DESC_SET(SCU418, 29)); + +#define B14 94 +SSSF_PIN_DECL(B14, GPIOL6, VGAHS, SIG_DESC_SET(SCU418, 30)); + +#define C14 95 +SSSF_PIN_DECL(C14, GPIOL7, VGAVS, SIG_DESC_SET(SCU418, 31)); + +#define D14 96 +SSSF_PIN_DECL(D14, GPIOM0, NCTS1, SIG_DESC_SET(SCU41C, 0)); + +#define B13 97 +SSSF_PIN_DECL(B13, GPIOM1, NDCD1, SIG_DESC_SET(SCU41C, 1)); + +#define A12 98 +SSSF_PIN_DECL(A12, GPIOM2, NDSR1, SIG_DESC_SET(SCU41C, 2)); + +#define E14 99 +SSSF_PIN_DECL(E14, GPIOM3, NRI1, SIG_DESC_SET(SCU41C, 3)); + +#define B12 100 +SSSF_PIN_DECL(B12, GPIOM4, NDTR1, SIG_DESC_SET(SCU41C, 4)); + +#define C12 101 +SSSF_PIN_DECL(C12, GPIOM5, NRTS1, SIG_DESC_SET(SCU41C, 5)); + +#define C13 102 +SSSF_PIN_DECL(C13, GPIOM6, TXD1, SIG_DESC_SET(SCU41C, 6)); + +#define D13 103 +SSSF_PIN_DECL(D13, GPIOM7, RXD1, SIG_DESC_SET(SCU41C, 7)); + +#define P25 104 +SSSF_PIN_DECL(P25, GPION0, NCTS2, SIG_DESC_SET(SCU41C, 8)); + +#define N23 105 +SSSF_PIN_DECL(N23, GPION1, NDCD2, SIG_DESC_SET(SCU41C, 9)); + +#define N25 106 +SSSF_PIN_DECL(N25, GPION2, NDSR2, SIG_DESC_SET(SCU41C, 10)); + +#define N24 107 +SSSF_PIN_DECL(N24, GPION3, NRI2, SIG_DESC_SET(SCU41C, 11)); + +#define P26 108 +SSSF_PIN_DECL(P26, GPION4, NDTR2, SIG_DESC_SET(SCU41C, 12)); + +#define M23 109 +SSSF_PIN_DECL(M23, GPION5, NRTS2, SIG_DESC_SET(SCU41C, 13)); + +#define N26 110 +SSSF_PIN_DECL(N26, GPION6, TXD2, SIG_DESC_SET(SCU41C, 14)); + +#define M26 111 +SSSF_PIN_DECL(M26, GPION7, RXD2, SIG_DESC_SET(SCU41C, 15)); + +#define AD26 112 +SSSF_PIN_DECL(AD26, GPIOO0, PWM0, SIG_DESC_SET(SCU41C, 16)); + +#define AD22 113 +SSSF_PIN_DECL(AD22, GPIOO1, PWM1, SIG_DESC_SET(SCU41C, 17)); + +#define AD23 114 +SSSF_PIN_DECL(AD23, GPIOO2, PWM2, SIG_DESC_SET(SCU41C, 18)); + +#define AD24 115 +SSSF_PIN_DECL(AD24, GPIOO3, PWM3, SIG_DESC_SET(SCU41C, 19)); + +#define AD25 116 +SSSF_PIN_DECL(AD25, GPIOO4, PWM4, SIG_DESC_SET(SCU41C, 20)); + +#define AC22 117 +SSSF_PIN_DECL(AC22, GPIOO5, PWM5, SIG_DESC_SET(SCU41C, 21)); + +#define AC24 118 +SSSF_PIN_DECL(AC24, GPIOO6, PWM6, SIG_DESC_SET(SCU41C, 22)); + +#define AC23 119 +SSSF_PIN_DECL(AC23, GPIOO7, PWM7, SIG_DESC_SET(SCU41C, 23)); + +#define AB22 120 +SIG_EXPR_LIST_DECL_SEMG(AB22, PWM8, PWM8G1, PWM8, SIG_DESC_SET(SCU41C, 24)); +SIG_EXPR_LIST_DECL_SESG(AB22, THRUIN0, THRU0, SIG_DESC_SET(SCU4BC, 24)); +PIN_DECL_2(AB22, GPIOP0, PWM8, THRUIN0); +GROUP_DECL(PWM8G1, AB22); +FUNC_DECL_2(PWM8, PWM8G0, PWM8G1); + +#define W24 121 +SIG_EXPR_LIST_DECL_SEMG(W24, PWM9, PWM9G1, PWM9, SIG_DESC_SET(SCU41C, 25)); +SIG_EXPR_LIST_DECL_SESG(W24, THRUOUT0, THRU0, SIG_DESC_SET(SCU4BC, 25)); +PIN_DECL_2(W24, GPIOP1, PWM9, THRUOUT0); + +FUNC_GROUP_DECL(THRU0, AB22, W24); + +GROUP_DECL(PWM9G1, W24); +FUNC_DECL_2(PWM9, PWM9G0, PWM9G1); + +#define AA23 122 +SIG_EXPR_LIST_DECL_SEMG(AA23, PWM10, PWM10G1, PWM10, SIG_DESC_SET(SCU41C, 26)); +SIG_EXPR_LIST_DECL_SESG(AA23, THRUIN1, THRU1, SIG_DESC_SET(SCU4BC, 26)); +PIN_DECL_2(AA23, GPIOP2, PWM10, THRUIN1); +GROUP_DECL(PWM10G1, AA23); +FUNC_DECL_2(PWM10, PWM10G0, PWM10G1); + +#define AA24 123 +SIG_EXPR_LIST_DECL_SEMG(AA24, PWM11, PWM11G1, PWM11, SIG_DESC_SET(SCU41C, 27)); +SIG_EXPR_LIST_DECL_SESG(AA24, THRUOUT1, THRU1, SIG_DESC_SET(SCU4BC, 27)); +PIN_DECL_2(AA24, GPIOP3, PWM11, THRUOUT1); +GROUP_DECL(PWM11G1, AA24); +FUNC_DECL_2(PWM11, PWM11G0, PWM11G1); + +FUNC_GROUP_DECL(THRU1, AA23, AA24); + +#define W23 124 +SIG_EXPR_LIST_DECL_SEMG(W23, PWM12, PWM12G1, PWM12, SIG_DESC_SET(SCU41C, 28)); +SIG_EXPR_LIST_DECL_SESG(W23, THRUIN2, THRU2, SIG_DESC_SET(SCU4BC, 28)); +PIN_DECL_2(W23, GPIOP4, PWM12, THRUIN2); +GROUP_DECL(PWM12G1, W23); +FUNC_DECL_2(PWM12, PWM12G0, PWM12G1); + +#define AB23 125 +SIG_EXPR_LIST_DECL_SEMG(AB23, PWM13, PWM13G1, PWM13, SIG_DESC_SET(SCU41C, 29)); +SIG_EXPR_LIST_DECL_SESG(AB23, THRUOUT2, THRU2, SIG_DESC_SET(SCU4BC, 29)); +PIN_DECL_2(AB23, GPIOP5, PWM13, THRUOUT2); +GROUP_DECL(PWM13G1, AB23); +FUNC_DECL_2(PWM13, PWM13G0, PWM13G1); + +FUNC_GROUP_DECL(THRU2, W23, AB23); + +#define AB24 126 +SIG_EXPR_LIST_DECL_SEMG(AB24, PWM14, PWM14G1, PWM14, SIG_DESC_SET(SCU41C, 30)); +SIG_EXPR_LIST_DECL_SESG(AB24, THRUIN3, THRU3, SIG_DESC_SET(SCU4BC, 30)); +PIN_DECL_2(AB24, GPIOP6, PWM14, THRUIN3); +GROUP_DECL(PWM14G1, AB24); +FUNC_DECL_2(PWM14, PWM14G0, PWM14G1); + +#define Y23 127 +SIG_EXPR_LIST_DECL_SEMG(Y23, PWM15, PWM15G1, PWM15, SIG_DESC_SET(SCU41C, 31)); +SIG_EXPR_LIST_DECL_SESG(Y23, THRUOUT3, THRU3, SIG_DESC_SET(SCU4BC, 31)); +PIN_DECL_2(Y23, GPIOP7, PWM15, THRUOUT3); +GROUP_DECL(PWM15G1, Y23); +FUNC_DECL_2(PWM15, PWM15G0, PWM15G1); + +FUNC_GROUP_DECL(THRU3, AB24, Y23); + +#define AA25 128 +SSSF_PIN_DECL(AA25, GPIOQ0, TACH0, SIG_DESC_SET(SCU430, 0)); + +#define AB25 129 +SSSF_PIN_DECL(AB25, GPIOQ1, TACH1, SIG_DESC_SET(SCU430, 1)); + +#define Y24 130 +SSSF_PIN_DECL(Y24, GPIOQ2, TACH2, SIG_DESC_SET(SCU430, 2)); + +#define AB26 131 +SSSF_PIN_DECL(AB26, GPIOQ3, TACH3, SIG_DESC_SET(SCU430, 3)); + +#define Y26 132 +SSSF_PIN_DECL(Y26, GPIOQ4, TACH4, SIG_DESC_SET(SCU430, 4)); + +#define AC26 133 +SSSF_PIN_DECL(AC26, GPIOQ5, TACH5, SIG_DESC_SET(SCU430, 5)); + +#define Y25 134 +SSSF_PIN_DECL(Y25, GPIOQ6, TACH6, SIG_DESC_SET(SCU430, 6)); + +#define AA26 135 +SSSF_PIN_DECL(AA26, GPIOQ7, TACH7, SIG_DESC_SET(SCU430, 7)); + +#define V25 136 +SSSF_PIN_DECL(V25, GPIOR0, TACH8, SIG_DESC_SET(SCU430, 8)); + +#define U24 137 +SSSF_PIN_DECL(U24, GPIOR1, TACH9, SIG_DESC_SET(SCU430, 9)); + +#define V24 138 +SSSF_PIN_DECL(V24, GPIOR2, TACH10, SIG_DESC_SET(SCU430, 10)); + +#define V26 139 +SSSF_PIN_DECL(V26, GPIOR3, TACH11, SIG_DESC_SET(SCU430, 11)); + +#define U25 140 +SSSF_PIN_DECL(U25, GPIOR4, TACH12, SIG_DESC_SET(SCU430, 12)); + +#define T23 141 +SSSF_PIN_DECL(T23, GPIOR5, TACH13, SIG_DESC_SET(SCU430, 13)); + +#define W26 142 +SSSF_PIN_DECL(W26, GPIOR6, TACH14, SIG_DESC_SET(SCU430, 14)); + +#define U26 143 +SSSF_PIN_DECL(U26, GPIOR7, TACH15, SIG_DESC_SET(SCU430, 15)); + +#define R23 144 +SIG_EXPR_LIST_DECL_SESG(R23, MDC1, MDIO1, SIG_DESC_SET(SCU430, 16)); +PIN_DECL_1(R23, GPIOS0, MDC1); + +#define T25 145 +SIG_EXPR_LIST_DECL_SESG(T25, MDIO1, MDIO1, SIG_DESC_SET(SCU430, 17)); +PIN_DECL_1(T25, GPIOS1, MDIO1); + +FUNC_GROUP_DECL(MDIO1, R23, T25); + +#define T26 146 +SSSF_PIN_DECL(T26, GPIOS2, PEWAKE, SIG_DESC_SET(SCU430, 18)); + +#define R24 147 +SSSF_PIN_DECL(R24, GPIOS3, OSCCLK, SIG_DESC_SET(SCU430, 19)); + +#define R26 148 +SIG_EXPR_LIST_DECL_SESG(R26, TXD10, UART10, SIG_DESC_SET(SCU430, 20)); +PIN_DECL_1(R26, GPIOS4, TXD10); + +#define P24 149 +SIG_EXPR_LIST_DECL_SESG(P24, RXD10, UART10, SIG_DESC_SET(SCU430, 21)); +PIN_DECL_1(P24, GPIOS5, RXD10); + +FUNC_GROUP_DECL(UART10, R26, P24); + +#define P23 150 +SIG_EXPR_LIST_DECL_SESG(P23, TXD11, UART11, SIG_DESC_SET(SCU430, 22)); +PIN_DECL_1(P23, GPIOS6, TXD11); + +#define T24 151 +SIG_EXPR_LIST_DECL_SESG(T24, RXD11, UART11, SIG_DESC_SET(SCU430, 23)); +PIN_DECL_1(T24, GPIOS7, RXD11); + +FUNC_GROUP_DECL(UART11, P23, T24); + +#define AD20 152 +SIG_EXPR_LIST_DECL_SESG(AD20, GPIT0, GPIT0, SIG_DESC_SET(SCU430, 24)); +SIG_EXPR_LIST_DECL_SESG(AD20, ADC0, ADC0); +PIN_DECL_(AD20, SIG_EXPR_LIST_PTR(AD20, GPIT0), SIG_EXPR_LIST_PTR(AD20, ADC0)); +FUNC_GROUP_DECL(GPIT0, AD20); +FUNC_GROUP_DECL(ADC0, AD20); + +#define AC18 153 +SIG_EXPR_LIST_DECL_SESG(AC18, GPIT1, GPIT1, SIG_DESC_SET(SCU430, 25)); +SIG_EXPR_LIST_DECL_SESG(AC18, ADC1, ADC1); +PIN_DECL_(AC18, SIG_EXPR_LIST_PTR(AC18, GPIT1), SIG_EXPR_LIST_PTR(AC18, ADC1)); +FUNC_GROUP_DECL(GPIT1, AC18); +FUNC_GROUP_DECL(ADC1, AC18); + +#define AE19 154 +SIG_EXPR_LIST_DECL_SESG(AE19, GPIT2, GPIT2, SIG_DESC_SET(SCU430, 26)); +SIG_EXPR_LIST_DECL_SESG(AE19, ADC2, ADC2); +PIN_DECL_(AE19, SIG_EXPR_LIST_PTR(AE19, GPIT2), SIG_EXPR_LIST_PTR(AE19, ADC2)); +FUNC_GROUP_DECL(GPIT2, AE19); +FUNC_GROUP_DECL(ADC2, AE19); + +#define AD19 155 +SIG_EXPR_LIST_DECL_SESG(AD19, GPIT3, GPIT3, SIG_DESC_SET(SCU430, 27)); +SIG_EXPR_LIST_DECL_SESG(AD19, ADC3, ADC3); +PIN_DECL_(AD19, SIG_EXPR_LIST_PTR(AD19, GPIT3), SIG_EXPR_LIST_PTR(AD19, ADC3)); +FUNC_GROUP_DECL(GPIT3, AD19); +FUNC_GROUP_DECL(ADC3, AD19); + +#define AC19 156 +SIG_EXPR_LIST_DECL_SESG(AC19, GPIT4, GPIT4, SIG_DESC_SET(SCU430, 28)); +SIG_EXPR_LIST_DECL_SESG(AC19, ADC4, ADC4); +PIN_DECL_(AC19, SIG_EXPR_LIST_PTR(AC19, GPIT4), SIG_EXPR_LIST_PTR(AC19, ADC4)); +FUNC_GROUP_DECL(GPIT4, AC19); +FUNC_GROUP_DECL(ADC4, AC19); + +#define AB19 157 +SIG_EXPR_LIST_DECL_SESG(AB19, GPIT5, GPIT5, SIG_DESC_SET(SCU430, 29)); +SIG_EXPR_LIST_DECL_SESG(AB19, ADC5, ADC5); +PIN_DECL_(AB19, SIG_EXPR_LIST_PTR(AB19, GPIT5), SIG_EXPR_LIST_PTR(AB19, ADC5)); +FUNC_GROUP_DECL(GPIT5, AB19); +FUNC_GROUP_DECL(ADC5, AB19); + +#define AB18 158 +SIG_EXPR_LIST_DECL_SESG(AB18, GPIT6, GPIT6, SIG_DESC_SET(SCU430, 30)); +SIG_EXPR_LIST_DECL_SESG(AB18, ADC6, ADC6); +PIN_DECL_(AB18, SIG_EXPR_LIST_PTR(AB18, GPIT6), SIG_EXPR_LIST_PTR(AB18, ADC6)); +FUNC_GROUP_DECL(GPIT6, AB18); +FUNC_GROUP_DECL(ADC6, AB18); + +#define AE18 159 +SIG_EXPR_LIST_DECL_SESG(AE18, GPIT7, GPIT7, SIG_DESC_SET(SCU430, 31)); +SIG_EXPR_LIST_DECL_SESG(AE18, ADC7, ADC7); +PIN_DECL_(AE18, SIG_EXPR_LIST_PTR(AE18, GPIT7), SIG_EXPR_LIST_PTR(AE18, ADC7)); +FUNC_GROUP_DECL(GPIT7, AE18); +FUNC_GROUP_DECL(ADC7, AE18); + +#define AB16 160 +SIG_EXPR_LIST_DECL_SEMG(AB16, SALT9, SALT9G1, SALT9, SIG_DESC_SET(SCU434, 0), + SIG_DESC_CLEAR(SCU694, 16)); +SIG_EXPR_LIST_DECL_SESG(AB16, GPIU0, GPIU0, SIG_DESC_SET(SCU434, 0), + SIG_DESC_SET(SCU694, 16)); +SIG_EXPR_LIST_DECL_SESG(AB16, ADC8, ADC8); +PIN_DECL_(AB16, SIG_EXPR_LIST_PTR(AB16, SALT9), SIG_EXPR_LIST_PTR(AB16, GPIU0), + SIG_EXPR_LIST_PTR(AB16, ADC8)); +GROUP_DECL(SALT9G1, AB16); +FUNC_DECL_2(SALT9, SALT9G0, SALT9G1); +FUNC_GROUP_DECL(GPIU0, AB16); +FUNC_GROUP_DECL(ADC8, AB16); + +#define AA17 161 +SIG_EXPR_LIST_DECL_SEMG(AA17, SALT10, SALT10G1, SALT10, SIG_DESC_SET(SCU434, 1), + SIG_DESC_CLEAR(SCU694, 17)); +SIG_EXPR_LIST_DECL_SESG(AA17, GPIU1, GPIU1, SIG_DESC_SET(SCU434, 1), + SIG_DESC_SET(SCU694, 17)); +SIG_EXPR_LIST_DECL_SESG(AA17, ADC9, ADC9); +PIN_DECL_(AA17, SIG_EXPR_LIST_PTR(AA17, SALT10), SIG_EXPR_LIST_PTR(AA17, GPIU1), + SIG_EXPR_LIST_PTR(AA17, ADC9)); +GROUP_DECL(SALT10G1, AA17); +FUNC_DECL_2(SALT10, SALT10G0, SALT10G1); +FUNC_GROUP_DECL(GPIU1, AA17); +FUNC_GROUP_DECL(ADC9, AA17); + +#define AB17 162 +SIG_EXPR_LIST_DECL_SEMG(AB17, SALT11, SALT11G1, SALT11, SIG_DESC_SET(SCU434, 2), + SIG_DESC_CLEAR(SCU694, 18)); +SIG_EXPR_LIST_DECL_SESG(AB17, GPIU2, GPIU2, SIG_DESC_SET(SCU434, 2), + SIG_DESC_SET(SCU694, 18)); +SIG_EXPR_LIST_DECL_SESG(AB17, ADC10, ADC10); +PIN_DECL_(AB17, SIG_EXPR_LIST_PTR(AB17, SALT11), SIG_EXPR_LIST_PTR(AB17, GPIU2), + SIG_EXPR_LIST_PTR(AB17, ADC10)); +GROUP_DECL(SALT11G1, AB17); +FUNC_DECL_2(SALT11, SALT11G0, SALT11G1); +FUNC_GROUP_DECL(GPIU2, AB17); +FUNC_GROUP_DECL(ADC10, AB17); + +#define AE16 163 +SIG_EXPR_LIST_DECL_SEMG(AE16, SALT12, SALT12G1, SALT12, SIG_DESC_SET(SCU434, 3), + SIG_DESC_CLEAR(SCU694, 19)); +SIG_EXPR_LIST_DECL_SESG(AE16, GPIU3, GPIU3, SIG_DESC_SET(SCU434, 3), + SIG_DESC_SET(SCU694, 19)); +SIG_EXPR_LIST_DECL_SESG(AE16, ADC11, ADC11); +PIN_DECL_(AE16, SIG_EXPR_LIST_PTR(AE16, SALT12), SIG_EXPR_LIST_PTR(AE16, GPIU3), + SIG_EXPR_LIST_PTR(AE16, ADC11)); +GROUP_DECL(SALT12G1, AE16); +FUNC_DECL_2(SALT12, SALT12G0, SALT12G1); +FUNC_GROUP_DECL(GPIU3, AE16); +FUNC_GROUP_DECL(ADC11, AE16); + +#define AC16 164 +SIG_EXPR_LIST_DECL_SEMG(AC16, SALT13, SALT13G1, SALT13, SIG_DESC_SET(SCU434, 4), + SIG_DESC_CLEAR(SCU694, 20)); +SIG_EXPR_LIST_DECL_SESG(AC16, GPIU4, GPIU4, SIG_DESC_SET(SCU434, 4), + SIG_DESC_SET(SCU694, 20)); +SIG_EXPR_LIST_DECL_SESG(AC16, ADC12, ADC12); +PIN_DECL_(AC16, SIG_EXPR_LIST_PTR(AC16, SALT13), SIG_EXPR_LIST_PTR(AC16, GPIU4), + SIG_EXPR_LIST_PTR(AC16, ADC12)); +GROUP_DECL(SALT13G1, AC16); +FUNC_DECL_2(SALT13, SALT13G0, SALT13G1); +FUNC_GROUP_DECL(GPIU4, AC16); +FUNC_GROUP_DECL(ADC12, AC16); + +#define AA16 165 +SIG_EXPR_LIST_DECL_SEMG(AA16, SALT14, SALT14G1, SALT14, SIG_DESC_SET(SCU434, 5), + SIG_DESC_CLEAR(SCU694, 21)); +SIG_EXPR_LIST_DECL_SESG(AA16, GPIU5, GPIU5, SIG_DESC_SET(SCU434, 5), + SIG_DESC_SET(SCU694, 21)); +SIG_EXPR_LIST_DECL_SESG(AA16, ADC13, ADC13); +PIN_DECL_(AA16, SIG_EXPR_LIST_PTR(AA16, SALT14), SIG_EXPR_LIST_PTR(AA16, GPIU5), + SIG_EXPR_LIST_PTR(AA16, ADC13)); +GROUP_DECL(SALT14G1, AA16); +FUNC_DECL_2(SALT14, SALT14G0, SALT14G1); +FUNC_GROUP_DECL(GPIU5, AA16); +FUNC_GROUP_DECL(ADC13, AA16); + +#define AD16 166 +SIG_EXPR_LIST_DECL_SEMG(AD16, SALT15, SALT15G1, SALT15, SIG_DESC_SET(SCU434, 6), + SIG_DESC_CLEAR(SCU694, 22)); +SIG_EXPR_LIST_DECL_SESG(AD16, GPIU6, GPIU6, SIG_DESC_SET(SCU434, 6), + SIG_DESC_SET(SCU694, 22)); +SIG_EXPR_LIST_DECL_SESG(AD16, ADC14, ADC14); +PIN_DECL_(AD16, SIG_EXPR_LIST_PTR(AD16, SALT15), SIG_EXPR_LIST_PTR(AD16, GPIU6), + SIG_EXPR_LIST_PTR(AD16, ADC14)); +GROUP_DECL(SALT15G1, AD16); +FUNC_DECL_2(SALT15, SALT15G0, SALT15G1); +FUNC_GROUP_DECL(GPIU6, AD16); +FUNC_GROUP_DECL(ADC14, AD16); + +#define AC17 167 +SIG_EXPR_LIST_DECL_SEMG(AC17, SALT16, SALT16G1, SALT16, SIG_DESC_SET(SCU434, 7), + SIG_DESC_CLEAR(SCU694, 23)); +SIG_EXPR_LIST_DECL_SESG(AC17, GPIU7, GPIU7, SIG_DESC_SET(SCU434, 7), + SIG_DESC_SET(SCU694, 23)); +SIG_EXPR_LIST_DECL_SESG(AC17, ADC15, ADC15); +PIN_DECL_(AC17, SIG_EXPR_LIST_PTR(AC17, SALT16), SIG_EXPR_LIST_PTR(AC17, GPIU7), + SIG_EXPR_LIST_PTR(AC17, ADC15)); +GROUP_DECL(SALT16G1, AC17); +FUNC_DECL_2(SALT16, SALT16G0, SALT16G1); +FUNC_GROUP_DECL(GPIU7, AC17); +FUNC_GROUP_DECL(ADC15, AC17); + +#define AB15 168 +SSSF_PIN_DECL(AB15, GPIOV0, SIOS3, SIG_DESC_SET(SCU434, 8)); + +#define AF14 169 +SSSF_PIN_DECL(AF14, GPIOV1, SIOS5, SIG_DESC_SET(SCU434, 9)); + +#define AD14 170 +SSSF_PIN_DECL(AD14, GPIOV2, SIOPWREQ, SIG_DESC_SET(SCU434, 10)); + +#define AC15 171 +SSSF_PIN_DECL(AC15, GPIOV3, SIOONCTRL, SIG_DESC_SET(SCU434, 11)); + +#define AE15 172 +SSSF_PIN_DECL(AE15, GPIOV4, SIOPWRGD, SIG_DESC_SET(SCU434, 12)); + +#define AE14 173 +SIG_EXPR_LIST_DECL_SESG(AE14, LPCPD, LPCPD, SIG_DESC_SET(SCU434, 13)); +SIG_EXPR_LIST_DECL_SESG(AE14, LHPD, LHPD, SIG_DESC_SET(SCU4D4, 13)); +PIN_DECL_2(AE14, GPIOV5, LPCPD, LHPD); +FUNC_GROUP_DECL(LPCPD, AE14); +FUNC_GROUP_DECL(LHPD, AE14); + +#define AD15 174 +SSSF_PIN_DECL(AD15, GPIOV6, LPCPME, SIG_DESC_SET(SCU434, 14)); + +#define AF15 175 +SSSF_PIN_DECL(AF15, GPIOV7, LPCSMI, SIG_DESC_SET(SCU434, 15)); + +#define AB7 176 +SIG_EXPR_LIST_DECL_SESG(AB7, LAD0, LPC, SIG_DESC_SET(SCU434, 16), + SIG_DESC_CLEAR(SCU510, 6)); +SIG_EXPR_LIST_DECL_SESG(AB7, ESPID0, ESPI, SIG_DESC_SET(SCU434, 16), + SIG_DESC_SET(SCU510, 6)); +PIN_DECL_2(AB7, GPIOW0, LAD0, ESPID0); + +#define AB8 177 +SIG_EXPR_LIST_DECL_SESG(AB8, LAD1, LPC, SIG_DESC_SET(SCU434, 17), + SIG_DESC_CLEAR(SCU510, 6)); +SIG_EXPR_LIST_DECL_SESG(AB8, ESPID1, ESPI, SIG_DESC_SET(SCU434, 17), + SIG_DESC_SET(SCU510, 6)); +PIN_DECL_2(AB8, GPIOW1, LAD1, ESPID1); + +#define AC8 178 +SIG_EXPR_LIST_DECL_SESG(AC8, LAD2, LPC, SIG_DESC_SET(SCU434, 18), + SIG_DESC_CLEAR(SCU510, 6)); +SIG_EXPR_LIST_DECL_SESG(AC8, ESPID2, ESPI, SIG_DESC_SET(SCU434, 18), + SIG_DESC_SET(SCU510, 6)); +PIN_DECL_2(AC8, GPIOW2, LAD2, ESPID2); + +#define AC7 179 +SIG_EXPR_LIST_DECL_SESG(AC7, LAD3, LPC, SIG_DESC_SET(SCU434, 19), + SIG_DESC_CLEAR(SCU510, 6)); +SIG_EXPR_LIST_DECL_SESG(AC7, ESPID3, ESPI, SIG_DESC_SET(SCU434, 19), + SIG_DESC_SET(SCU510, 6)); +PIN_DECL_2(AC7, GPIOW3, LAD3, ESPID3); + +#define AE7 180 +SIG_EXPR_LIST_DECL_SESG(AE7, LCLK, LPC, SIG_DESC_SET(SCU434, 20), + SIG_DESC_CLEAR(SCU510, 6)); +SIG_EXPR_LIST_DECL_SESG(AE7, ESPICK, ESPI, SIG_DESC_SET(SCU434, 20), + SIG_DESC_SET(SCU510, 6)); +PIN_DECL_2(AE7, GPIOW4, LCLK, ESPICK); + +#define AF7 181 +SIG_EXPR_LIST_DECL_SESG(AF7, LFRAME, LPC, SIG_DESC_SET(SCU434, 21), + SIG_DESC_CLEAR(SCU510, 6)); +SIG_EXPR_LIST_DECL_SESG(AF7, ESPICS, ESPI, SIG_DESC_SET(SCU434, 21), + SIG_DESC_SET(SCU510, 6)); +PIN_DECL_2(AF7, GPIOW5, LFRAME, ESPICS); + +#define AD7 182 +SIG_EXPR_LIST_DECL_SESG(AD7, LSIRQ, LSIRQ, SIG_DESC_SET(SCU434, 22), + SIG_DESC_CLEAR(SCU510, 6)); +SIG_EXPR_LIST_DECL_SESG(AD7, ESPIALT, ESPIALT, SIG_DESC_SET(SCU434, 22), + SIG_DESC_SET(SCU510, 6)); +PIN_DECL_2(AD7, GPIOW6, LSIRQ, ESPIALT); +FUNC_GROUP_DECL(LSIRQ, AD7); +FUNC_GROUP_DECL(ESPIALT, AD7); + +#define AD8 183 +SIG_EXPR_LIST_DECL_SESG(AD8, LPCRST, LPC, SIG_DESC_SET(SCU434, 23), + SIG_DESC_CLEAR(SCU510, 6)); +SIG_EXPR_LIST_DECL_SESG(AD8, ESPIRST, ESPI, SIG_DESC_SET(SCU434, 23), + SIG_DESC_SET(SCU510, 6)); +PIN_DECL_2(AD8, GPIOW7, LPCRST, ESPIRST); + +FUNC_GROUP_DECL(LPC, AB7, AB8, AC8, AC7, AE7, AF7, AD8); +FUNC_GROUP_DECL(ESPI, AB7, AB8, AC8, AC7, AE7, AF7, AD8); + +#define AE8 184 +SIG_EXPR_LIST_DECL_SEMG(AE8, SPI2CS0, SPI2, SPI2, SIG_DESC_SET(SCU434, 24)); +PIN_DECL_1(AE8, GPIOX0, SPI2CS0); + +#define AA9 185 +SSSF_PIN_DECL(AA9, GPIOX1, SPI2CS1, SIG_DESC_SET(SCU434, 25)); + +#define AC9 186 +SSSF_PIN_DECL(AC9, GPIOX2, SPI2CS2, SIG_DESC_SET(SCU434, 26)); + +#define AF8 187 +SIG_EXPR_LIST_DECL_SEMG(AF8, SPI2CK, SPI2, SPI2, SIG_DESC_SET(SCU434, 27)); +PIN_DECL_1(AF8, GPIOX3, SPI2CK); + +#define AB9 188 +SIG_EXPR_LIST_DECL_SEMG(AB9, SPI2MOSI, SPI2, SPI2, SIG_DESC_SET(SCU434, 28)); +PIN_DECL_1(AB9, GPIOX4, SPI2MOSI); + +#define AD9 189 +SIG_EXPR_LIST_DECL_SEMG(AD9, SPI2MISO, SPI2, SPI2, SIG_DESC_SET(SCU434, 29)); +PIN_DECL_1(AD9, GPIOX5, SPI2MISO); + +GROUP_DECL(SPI2, AE8, AF8, AB9, AD9); + +#define AF9 190 +SIG_EXPR_LIST_DECL_SEMG(AF9, SPI2DQ2, QSPI2, SPI2, SIG_DESC_SET(SCU434, 30)); +SIG_EXPR_LIST_DECL_SEMG(AF9, TXD12, UART12G1, UART12, SIG_DESC_SET(SCU4D4, 30)); +PIN_DECL_2(AF9, GPIOX6, SPI2DQ2, TXD12); + +#define AB10 191 +SIG_EXPR_LIST_DECL_SEMG(AB10, SPI2DQ3, QSPI2, SPI2, SIG_DESC_SET(SCU434, 31)); +SIG_EXPR_LIST_DECL_SEMG(AB10, RXD12, UART12G1, UART12, + SIG_DESC_SET(SCU4D4, 31)); +PIN_DECL_2(AB10, GPIOX7, SPI2DQ3, RXD12); + +GROUP_DECL(QSPI2, AE8, AF8, AB9, AD9, AF9, AB10); +FUNC_DECL_2(SPI2, SPI2, QSPI2); + +GROUP_DECL(UART12G1, AF9, AB10); +FUNC_DECL_2(UART12, UART12G0, UART12G1); + +#define AF11 192 +SIG_EXPR_LIST_DECL_SESG(AF11, SALT5, SALT5, SIG_DESC_SET(SCU438, 0)); +SIG_EXPR_LIST_DECL_SESG(AF11, WDTRST1, WDTRST1, SIG_DESC_SET(SCU4D8, 0)); +PIN_DECL_2(AF11, GPIOY0, SALT5, WDTRST1); +FUNC_GROUP_DECL(SALT5, AF11); +FUNC_GROUP_DECL(WDTRST1, AF11); + +#define AD12 193 +SIG_EXPR_LIST_DECL_SESG(AD12, SALT6, SALT6, SIG_DESC_SET(SCU438, 1)); +SIG_EXPR_LIST_DECL_SESG(AD12, WDTRST2, WDTRST2, SIG_DESC_SET(SCU4D8, 1)); +PIN_DECL_2(AD12, GPIOY1, SALT6, WDTRST2); +FUNC_GROUP_DECL(SALT6, AD12); +FUNC_GROUP_DECL(WDTRST2, AD12); + +#define AE11 194 +SIG_EXPR_LIST_DECL_SESG(AE11, SALT7, SALT7, SIG_DESC_SET(SCU438, 2)); +SIG_EXPR_LIST_DECL_SESG(AE11, WDTRST3, WDTRST3, SIG_DESC_SET(SCU4D8, 2)); +PIN_DECL_2(AE11, GPIOY2, SALT7, WDTRST3); +FUNC_GROUP_DECL(SALT7, AE11); +FUNC_GROUP_DECL(WDTRST3, AE11); + +#define AA12 195 +SIG_EXPR_LIST_DECL_SESG(AA12, SALT8, SALT8, SIG_DESC_SET(SCU438, 3)); +SIG_EXPR_LIST_DECL_SESG(AA12, WDTRST4, WDTRST4, SIG_DESC_SET(SCU4D8, 3)); +PIN_DECL_2(AA12, GPIOY3, SALT8, WDTRST4); +FUNC_GROUP_DECL(SALT8, AA12); +FUNC_GROUP_DECL(WDTRST4, AA12); + +#define AE12 196 +SIG_EXPR_LIST_DECL_SEMG(AE12, FWSPIDQ2, FWQSPID, FWSPID, + SIG_DESC_SET(SCU438, 4)); +SIG_EXPR_LIST_DECL_SESG(AE12, GPIOY4, GPIOY4); +PIN_DECL_(AE12, SIG_EXPR_LIST_PTR(AE12, FWSPIDQ2), + SIG_EXPR_LIST_PTR(AE12, GPIOY4)); + +#define AF12 197 +SIG_EXPR_LIST_DECL_SEMG(AF12, FWSPIDQ3, FWQSPID, FWSPID, + SIG_DESC_SET(SCU438, 5)); +SIG_EXPR_LIST_DECL_SESG(AF12, GPIOY5, GPIOY5); +PIN_DECL_(AF12, SIG_EXPR_LIST_PTR(AF12, FWSPIDQ3), + SIG_EXPR_LIST_PTR(AF12, GPIOY5)); + +#define AC12 198 +SSSF_PIN_DECL(AC12, GPIOY6, FWSPIABR, SIG_DESC_SET(SCU438, 6)); + +#define AB12 199 +SSSF_PIN_DECL(AB12, GPIOY7, FWSPIWP, SIG_DESC_SET(SCU438, 7)); + +#define AC10 200 +SSSF_PIN_DECL(AC10, GPIOZ0, SPI1CS1, SIG_DESC_SET(SCU438, 8)); + +#define AD10 201 +SSSF_PIN_DECL(AD10, GPIOZ1, SPI1ABR, SIG_DESC_SET(SCU438, 9)); + +#define AE10 202 +SSSF_PIN_DECL(AE10, GPIOZ2, SPI1WP, SIG_DESC_SET(SCU438, 10)); + +#define AB11 203 +SIG_EXPR_LIST_DECL_SEMG(AB11, SPI1CK, SPI1, SPI1, SIG_DESC_SET(SCU438, 11)); +PIN_DECL_1(AB11, GPIOZ3, SPI1CK); + +#define AC11 204 +SIG_EXPR_LIST_DECL_SEMG(AC11, SPI1MOSI, SPI1, SPI1, SIG_DESC_SET(SCU438, 12)); +PIN_DECL_1(AC11, GPIOZ4, SPI1MOSI); + +#define AA11 205 +SIG_EXPR_LIST_DECL_SEMG(AA11, SPI1MISO, SPI1, SPI1, SIG_DESC_SET(SCU438, 13)); +PIN_DECL_1(AA11, GPIOZ5, SPI1MISO); + +GROUP_DECL(SPI1, AB11, AC11, AA11); + +#define AD11 206 +SIG_EXPR_LIST_DECL_SEMG(AD11, SPI1DQ2, QSPI1, SPI1, SIG_DESC_SET(SCU438, 14)); +SIG_EXPR_LIST_DECL_SEMG(AD11, TXD13, UART13G1, UART13, + SIG_DESC_SET(SCU438, 14)); +PIN_DECL_2(AD11, GPIOZ6, SPI1DQ2, TXD13); + +#define AF10 207 +SIG_EXPR_LIST_DECL_SEMG(AF10, SPI1DQ3, QSPI1, SPI1, SIG_DESC_SET(SCU438, 15)); +SIG_EXPR_LIST_DECL_SEMG(AF10, RXD13, UART13G1, UART13, + SIG_DESC_SET(SCU438, 15)); +PIN_DECL_2(AF10, GPIOZ7, SPI1DQ3, RXD13); + +GROUP_DECL(QSPI1, AB11, AC11, AA11, AD11, AF10); +FUNC_DECL_2(SPI1, SPI1, QSPI1); + +GROUP_DECL(UART13G1, AD11, AF10); +FUNC_DECL_2(UART13, UART13G0, UART13G1); + +#define C6 208 +SIG_EXPR_LIST_DECL_SESG(C6, RGMII1TXCK, RGMII1, SIG_DESC_SET(SCU400, 0), + SIG_DESC_SET(SCU500, 6)); +SIG_EXPR_LIST_DECL_SESG(C6, RMII1RCLKO, RMII1, SIG_DESC_SET(SCU400, 0), + SIG_DESC_CLEAR(SCU500, 6)); +PIN_DECL_2(C6, GPIO18A0, RGMII1TXCK, RMII1RCLKO); + +#define D6 209 +SIG_EXPR_LIST_DECL_SESG(D6, RGMII1TXCTL, RGMII1, SIG_DESC_SET(SCU400, 1), + SIG_DESC_SET(SCU500, 6)); +SIG_EXPR_LIST_DECL_SESG(D6, RMII1TXEN, RMII1, SIG_DESC_SET(SCU400, 1), + SIG_DESC_CLEAR(SCU500, 6)); +PIN_DECL_2(D6, GPIO18A1, RGMII1TXCTL, RMII1TXEN); + +#define D5 210 +SIG_EXPR_LIST_DECL_SESG(D5, RGMII1TXD0, RGMII1, SIG_DESC_SET(SCU400, 2), + SIG_DESC_SET(SCU500, 6)); +SIG_EXPR_LIST_DECL_SESG(D5, RMII1TXD0, RMII1, SIG_DESC_SET(SCU400, 2), + SIG_DESC_CLEAR(SCU500, 6)); +PIN_DECL_2(D5, GPIO18A2, RGMII1TXD0, RMII1TXD0); + +#define A3 211 +SIG_EXPR_LIST_DECL_SESG(A3, RGMII1TXD1, RGMII1, SIG_DESC_SET(SCU400, 3), + SIG_DESC_SET(SCU500, 6)); +SIG_EXPR_LIST_DECL_SESG(A3, RMII1TXD1, RMII1, SIG_DESC_SET(SCU400, 3), + SIG_DESC_CLEAR(SCU500, 6)); +PIN_DECL_2(A3, GPIO18A3, RGMII1TXD1, RMII1TXD1); + +#define C5 212 +SIG_EXPR_LIST_DECL_SESG(C5, RGMII1TXD2, RGMII1, SIG_DESC_SET(SCU400, 4), + SIG_DESC_SET(SCU500, 6)); +PIN_DECL_1(C5, GPIO18A4, RGMII1TXD2); + +#define E6 213 +SIG_EXPR_LIST_DECL_SESG(E6, RGMII1TXD3, RGMII1, SIG_DESC_SET(SCU400, 5), + SIG_DESC_SET(SCU500, 6)); +PIN_DECL_1(E6, GPIO18A5, RGMII1TXD3); + +#define B3 214 +SIG_EXPR_LIST_DECL_SESG(B3, RGMII1RXCK, RGMII1, SIG_DESC_SET(SCU400, 6), + SIG_DESC_SET(SCU500, 6)); +SIG_EXPR_LIST_DECL_SESG(B3, RMII1RCLKI, RMII1, SIG_DESC_SET(SCU400, 6), + SIG_DESC_CLEAR(SCU500, 6)); +PIN_DECL_2(B3, GPIO18A6, RGMII1RXCK, RMII1RCLKI); + +#define A2 215 +SIG_EXPR_LIST_DECL_SESG(A2, RGMII1RXCTL, RGMII1, SIG_DESC_SET(SCU400, 7), + SIG_DESC_SET(SCU500, 6)); +PIN_DECL_1(A2, GPIO18A7, RGMII1RXCTL); + +#define B2 216 +SIG_EXPR_LIST_DECL_SESG(B2, RGMII1RXD0, RGMII1, SIG_DESC_SET(SCU400, 8), + SIG_DESC_SET(SCU500, 6)); +SIG_EXPR_LIST_DECL_SESG(B2, RMII1RXD0, RMII1, SIG_DESC_SET(SCU400, 8), + SIG_DESC_CLEAR(SCU500, 6)); +PIN_DECL_2(B2, GPIO18B0, RGMII1RXD0, RMII1RXD0); + +#define B1 217 +SIG_EXPR_LIST_DECL_SESG(B1, RGMII1RXD1, RGMII1, SIG_DESC_SET(SCU400, 9), + SIG_DESC_SET(SCU500, 6)); +SIG_EXPR_LIST_DECL_SESG(B1, RMII1RXD1, RMII1, SIG_DESC_SET(SCU400, 9), + SIG_DESC_CLEAR(SCU500, 6)); +PIN_DECL_2(B1, GPIO18B1, RGMII1RXD1, RMII1RXD1); + +#define C4 218 +SIG_EXPR_LIST_DECL_SESG(C4, RGMII1RXD2, RGMII1, SIG_DESC_SET(SCU400, 10), + SIG_DESC_SET(SCU500, 6)); +SIG_EXPR_LIST_DECL_SESG(C4, RMII1CRSDV, RMII1, SIG_DESC_SET(SCU400, 10), + SIG_DESC_CLEAR(SCU500, 6)); +PIN_DECL_2(C4, GPIO18B2, RGMII1RXD2, RMII1CRSDV); + +#define E5 219 +SIG_EXPR_LIST_DECL_SESG(E5, RGMII1RXD3, RGMII1, SIG_DESC_SET(SCU400, 11), + SIG_DESC_SET(SCU500, 6)); +SIG_EXPR_LIST_DECL_SESG(E5, RMII1RXER, RMII1, SIG_DESC_SET(SCU400, 11), + SIG_DESC_CLEAR(SCU500, 6)); +PIN_DECL_2(E5, GPIO18B3, RGMII1RXD3, RMII1RXER); + +FUNC_GROUP_DECL(RGMII1, C6, D6, D5, A3, C5, E6, B3, A2, B2, B1, C4, E5); +FUNC_GROUP_DECL(RMII1, C6, D6, D5, A3, B3, B2, B1, C4, E5); + +#define D4 220 +SIG_EXPR_LIST_DECL_SESG(D4, RGMII2TXCK, RGMII2, SIG_DESC_SET(SCU400, 12), + SIG_DESC_SET(SCU500, 7)); +SIG_EXPR_LIST_DECL_SESG(D4, RMII2RCLKO, RMII2, SIG_DESC_SET(SCU400, 12), + SIG_DESC_CLEAR(SCU500, 7)); +PIN_DECL_2(D4, GPIO18B4, RGMII2TXCK, RMII2RCLKO); + +#define C2 221 +SIG_EXPR_LIST_DECL_SESG(C2, RGMII2TXCTL, RGMII2, SIG_DESC_SET(SCU400, 13), + SIG_DESC_SET(SCU500, 7)); +SIG_EXPR_LIST_DECL_SESG(C2, RMII2TXEN, RMII2, SIG_DESC_SET(SCU400, 13), + SIG_DESC_CLEAR(SCU500, 7)); +PIN_DECL_2(C2, GPIO18B5, RGMII2TXCTL, RMII2TXEN); + +#define C1 222 +SIG_EXPR_LIST_DECL_SESG(C1, RGMII2TXD0, RGMII2, SIG_DESC_SET(SCU400, 14), + SIG_DESC_SET(SCU500, 7)); +SIG_EXPR_LIST_DECL_SESG(C1, RMII2TXD0, RMII2, SIG_DESC_SET(SCU400, 14), + SIG_DESC_CLEAR(SCU500, 7)); +PIN_DECL_2(C1, GPIO18B6, RGMII2TXD0, RMII2TXD0); + +#define D3 223 +SIG_EXPR_LIST_DECL_SESG(D3, RGMII2TXD1, RGMII2, SIG_DESC_SET(SCU400, 15), + SIG_DESC_SET(SCU500, 7)); +SIG_EXPR_LIST_DECL_SESG(D3, RMII2TXD1, RMII2, SIG_DESC_SET(SCU400, 15), + SIG_DESC_CLEAR(SCU500, 7)); +PIN_DECL_2(D3, GPIO18B7, RGMII2TXD1, RMII2TXD1); + +#define E4 224 +SIG_EXPR_LIST_DECL_SESG(E4, RGMII2TXD2, RGMII2, SIG_DESC_SET(SCU400, 16), + SIG_DESC_SET(SCU500, 7)); +PIN_DECL_1(E4, GPIO18C0, RGMII2TXD2); + +#define F5 225 +SIG_EXPR_LIST_DECL_SESG(F5, RGMII2TXD3, RGMII2, SIG_DESC_SET(SCU400, 17), + SIG_DESC_SET(SCU500, 7)); +PIN_DECL_1(F5, GPIO18C1, RGMII2TXD3); + +#define D2 226 +SIG_EXPR_LIST_DECL_SESG(D2, RGMII2RXCK, RGMII2, SIG_DESC_SET(SCU400, 18), + SIG_DESC_SET(SCU500, 7)); +SIG_EXPR_LIST_DECL_SESG(D2, RMII2RCLKI, RMII2, SIG_DESC_SET(SCU400, 18), + SIG_DESC_CLEAR(SCU500, 7)); +PIN_DECL_2(D2, GPIO18C2, RGMII2RXCK, RMII2RCLKI); + +#define E3 227 +SIG_EXPR_LIST_DECL_SESG(E3, RGMII2RXCTL, RGMII2, SIG_DESC_SET(SCU400, 19), + SIG_DESC_SET(SCU500, 7)); +PIN_DECL_1(E3, GPIO18C3, RGMII2RXCTL); + +#define D1 228 +SIG_EXPR_LIST_DECL_SESG(D1, RGMII2RXD0, RGMII2, SIG_DESC_SET(SCU400, 20), + SIG_DESC_SET(SCU500, 7)); +SIG_EXPR_LIST_DECL_SESG(D1, RMII2RXD0, RMII2, SIG_DESC_SET(SCU400, 20), + SIG_DESC_CLEAR(SCU500, 7)); +PIN_DECL_2(D1, GPIO18C4, RGMII2RXD0, RMII2RXD0); + +#define F4 229 +SIG_EXPR_LIST_DECL_SESG(F4, RGMII2RXD1, RGMII2, SIG_DESC_SET(SCU400, 21), + SIG_DESC_SET(SCU500, 7)); +SIG_EXPR_LIST_DECL_SESG(F4, RMII2RXD1, RMII2, SIG_DESC_SET(SCU400, 21), + SIG_DESC_CLEAR(SCU500, 7)); +PIN_DECL_2(F4, GPIO18C5, RGMII2RXD1, RMII2RXD1); + +#define E2 230 +SIG_EXPR_LIST_DECL_SESG(E2, RGMII2RXD2, RGMII2, SIG_DESC_SET(SCU400, 22), + SIG_DESC_SET(SCU500, 7)); +SIG_EXPR_LIST_DECL_SESG(E2, RMII2CRSDV, RMII2, SIG_DESC_SET(SCU400, 22), + SIG_DESC_CLEAR(SCU500, 7)); +PIN_DECL_2(E2, GPIO18C6, RGMII2RXD2, RMII2CRSDV); + +#define E1 231 +SIG_EXPR_LIST_DECL_SESG(E1, RGMII2RXD3, RGMII2, SIG_DESC_SET(SCU400, 23), + SIG_DESC_SET(SCU500, 7)); +SIG_EXPR_LIST_DECL_SESG(E1, RMII2RXER, RMII2, SIG_DESC_SET(SCU400, 23), + SIG_DESC_CLEAR(SCU500, 7)); +PIN_DECL_2(E1, GPIO18C7, RGMII2RXD3, RMII2RXER); + +FUNC_GROUP_DECL(RGMII2, D4, C2, C1, D3, E4, F5, D2, E3, D1, F4, E2, E1); +FUNC_GROUP_DECL(RMII2, D4, C2, C1, D3, D2, D1, F4, E2, E1); + +#define AB4 232 +SIG_EXPR_LIST_DECL_SESG(AB4, SD3CLK, SD3, SIG_DESC_SET(SCU400, 24)); +PIN_DECL_1(AB4, GPIO18D0, SD3CLK); + +#define AA4 233 +SIG_EXPR_LIST_DECL_SESG(AA4, SD3CMD, SD3, SIG_DESC_SET(SCU400, 25)); +PIN_DECL_1(AA4, GPIO18D1, SD3CMD); + +#define AC4 234 +SIG_EXPR_LIST_DECL_SESG(AC4, SD3DAT0, SD3, SIG_DESC_SET(SCU400, 26)); +PIN_DECL_1(AC4, GPIO18D2, SD3DAT0); + +#define AA5 235 +SIG_EXPR_LIST_DECL_SESG(AA5, SD3DAT1, SD3, SIG_DESC_SET(SCU400, 27)); +PIN_DECL_1(AA5, GPIO18D3, SD3DAT1); + +#define Y5 236 +SIG_EXPR_LIST_DECL_SESG(Y5, SD3DAT2, SD3, SIG_DESC_SET(SCU400, 28)); +PIN_DECL_1(Y5, GPIO18D4, SD3DAT2); + +#define AB5 237 +SIG_EXPR_LIST_DECL_SESG(AB5, SD3DAT3, SD3, SIG_DESC_SET(SCU400, 29)); +PIN_DECL_1(AB5, GPIO18D5, SD3DAT3); + +#define AB6 238 +SIG_EXPR_LIST_DECL_SESG(AB6, SD3CD, SD3, SIG_DESC_SET(SCU400, 30)); +PIN_DECL_1(AB6, GPIO18D6, SD3CD); + +#define AC5 239 +SIG_EXPR_LIST_DECL_SESG(AC5, SD3WP, SD3, SIG_DESC_SET(SCU400, 31)); +PIN_DECL_1(AC5, GPIO18D7, SD3WP); + +FUNC_GROUP_DECL(SD3, AB4, AA4, AC4, AA5, Y5, AB5, AB6, AC5); + +#define Y1 240 +SIG_EXPR_LIST_DECL_SEMG(Y1, FWSPIDCS, FWSPID, FWSPID, SIG_DESC_SET(SCU500, 3)); +SIG_EXPR_LIST_DECL_SESG(Y1, VBCS, VB, SIG_DESC_SET(SCU500, 5)); +SIG_EXPR_LIST_DECL_SESG(Y1, SD3DAT4, SD3DAT4, SIG_DESC_SET(SCU404, 0)); +PIN_DECL_3(Y1, GPIO18E0, FWSPIDCS, VBCS, SD3DAT4); +FUNC_GROUP_DECL(SD3DAT4, Y1); + +#define Y2 241 +SIG_EXPR_LIST_DECL_SEMG(Y2, FWSPIDCK, FWSPID, FWSPID, SIG_DESC_SET(SCU500, 3)); +SIG_EXPR_LIST_DECL_SESG(Y2, VBCK, VB, SIG_DESC_SET(SCU500, 5)); +SIG_EXPR_LIST_DECL_SESG(Y2, SD3DAT5, SD3DAT5, SIG_DESC_SET(SCU404, 1)); +PIN_DECL_3(Y2, GPIO18E1, FWSPIDCK, VBCK, SD3DAT5); +FUNC_GROUP_DECL(SD3DAT5, Y2); + +#define Y3 242 +SIG_EXPR_LIST_DECL_SEMG(Y3, FWSPIDMOSI, FWSPID, FWSPID, + SIG_DESC_SET(SCU500, 3)); +SIG_EXPR_LIST_DECL_SESG(Y3, VBMOSI, VB, SIG_DESC_SET(SCU500, 5)); +SIG_EXPR_LIST_DECL_SESG(Y3, SD3DAT6, SD3DAT6, SIG_DESC_SET(SCU404, 2)); +PIN_DECL_3(Y3, GPIO18E2, FWSPIDMOSI, VBMOSI, SD3DAT6); +FUNC_GROUP_DECL(SD3DAT6, Y3); + +#define Y4 243 +SIG_EXPR_LIST_DECL_SEMG(Y4, FWSPIDMISO, FWSPID, FWSPID, + SIG_DESC_SET(SCU500, 3)); +SIG_EXPR_LIST_DECL_SESG(Y4, VBMISO, VB, SIG_DESC_SET(SCU500, 5)); +SIG_EXPR_LIST_DECL_SESG(Y4, SD3DAT7, SD3DAT7, SIG_DESC_SET(SCU404, 3)); +PIN_DECL_3(Y4, GPIO18E3, FWSPIDMISO, VBMISO, SD3DAT7); +FUNC_GROUP_DECL(SD3DAT7, Y4); + +GROUP_DECL(FWSPID, Y1, Y2, Y3, Y4); +GROUP_DECL(FWQSPID, Y1, Y2, Y3, Y4, AE12, AF12); +FUNC_DECL_2(FWSPID, FWSPID, FWQSPID); +FUNC_GROUP_DECL(VB, Y1, Y2, Y3, Y4); + +/* + * FIXME: Confirm bits and priorities are the right way around for the + * following 4 pins + */ +#define AF25 244 +SIG_EXPR_LIST_DECL_SEMG(AF25, I3C3SCL, I3C3, I3C3, SIG_DESC_SET(SCU438, 20), + SIG_DESC_SET(SCU4D8, 20)); +SIG_EXPR_LIST_DECL_SESG(AF25, FSI1CLK, FSI1, SIG_DESC_CLEAR(SCU438, 20), + SIG_DESC_SET(SCU4D8, 20)); +PIN_DECL_(AF25, SIG_EXPR_LIST_PTR(AF25, I3C3SCL), + SIG_EXPR_LIST_PTR(AF25, FSI1CLK)); + +#define AE26 245 +SIG_EXPR_LIST_DECL_SEMG(AE26, I3C3SDA, I3C3, I3C3, SIG_DESC_SET(SCU438, 21), + SIG_DESC_SET(SCU4D8, 21)); +SIG_EXPR_LIST_DECL_SESG(AE26, FSI1DATA, FSI1, SIG_DESC_CLEAR(SCU438, 21), + SIG_DESC_SET(SCU4D8, 21)); +PIN_DECL_(AE26, SIG_EXPR_LIST_PTR(AE26, I3C3SDA), + SIG_EXPR_LIST_PTR(AE26, FSI1DATA)); + +GROUP_DECL(I3C3, AF25, AE26); +FUNC_DECL_2(I3C3, HVI3C3, I3C3); +FUNC_GROUP_DECL(FSI1, AF25, AE26); + +#define AE25 246 +SIG_EXPR_LIST_DECL_SEMG(AE25, I3C4SCL, I3C4, I3C4, SIG_DESC_SET(SCU438, 22), + SIG_DESC_SET(SCU4D8, 22)); +SIG_EXPR_LIST_DECL_SESG(AE25, FSI2CLK, FSI2, SIG_DESC_CLEAR(SCU438, 22), + SIG_DESC_SET(SCU4D8, 22)); +PIN_DECL_(AE25, SIG_EXPR_LIST_PTR(AE25, I3C4SCL), + SIG_EXPR_LIST_PTR(AE25, FSI2CLK)); + +#define AF24 247 +SIG_EXPR_LIST_DECL_SEMG(AF24, I3C4SDA, I3C4, I3C4, SIG_DESC_SET(SCU438, 23), + SIG_DESC_SET(SCU4D8, 23)); +SIG_EXPR_LIST_DECL_SESG(AF24, FSI2DATA, FSI2, SIG_DESC_CLEAR(SCU438, 23), + SIG_DESC_SET(SCU4D8, 23)); +PIN_DECL_(AF24, SIG_EXPR_LIST_PTR(AF24, I3C4SDA), + SIG_EXPR_LIST_PTR(AF24, FSI2DATA)); + +GROUP_DECL(I3C4, AE25, AF24); +FUNC_DECL_2(I3C4, HVI3C4, I3C4); +FUNC_GROUP_DECL(FSI2, AE25, AF24); + +/* Pins, groups and functions are sort(1):ed alphabetically for sanity */ + +static struct pinctrl_pin_desc aspeed_g6_pins[ASPEED_G6_NR_PINS] = { + ASPEED_PINCTRL_PIN(A11), + ASPEED_PINCTRL_PIN(A12), + ASPEED_PINCTRL_PIN(A13), + ASPEED_PINCTRL_PIN(A14), + ASPEED_PINCTRL_PIN(A15), + ASPEED_PINCTRL_PIN(A16), + ASPEED_PINCTRL_PIN(A17), + ASPEED_PINCTRL_PIN(A18), + ASPEED_PINCTRL_PIN(A19), + ASPEED_PINCTRL_PIN(A2), + ASPEED_PINCTRL_PIN(A20), + ASPEED_PINCTRL_PIN(A21), + ASPEED_PINCTRL_PIN(A22), + ASPEED_PINCTRL_PIN(A23), + ASPEED_PINCTRL_PIN(A24), + ASPEED_PINCTRL_PIN(A25), + ASPEED_PINCTRL_PIN(A3), + ASPEED_PINCTRL_PIN(AA11), + ASPEED_PINCTRL_PIN(AA12), + ASPEED_PINCTRL_PIN(AA23), + ASPEED_PINCTRL_PIN(AA24), + ASPEED_PINCTRL_PIN(AA25), + ASPEED_PINCTRL_PIN(AA26), + ASPEED_PINCTRL_PIN(AA4), + ASPEED_PINCTRL_PIN(AA5), + ASPEED_PINCTRL_PIN(AA9), + ASPEED_PINCTRL_PIN(AB10), + ASPEED_PINCTRL_PIN(AB11), + ASPEED_PINCTRL_PIN(AB12), + ASPEED_PINCTRL_PIN(AB15), + ASPEED_PINCTRL_PIN(AB18), + ASPEED_PINCTRL_PIN(AB19), + ASPEED_PINCTRL_PIN(AB22), + ASPEED_PINCTRL_PIN(AB23), + ASPEED_PINCTRL_PIN(AB24), + ASPEED_PINCTRL_PIN(AB25), + ASPEED_PINCTRL_PIN(AB26), + ASPEED_PINCTRL_PIN(AB4), + ASPEED_PINCTRL_PIN(AB5), + ASPEED_PINCTRL_PIN(AB6), + ASPEED_PINCTRL_PIN(AB7), + ASPEED_PINCTRL_PIN(AB8), + ASPEED_PINCTRL_PIN(AB9), + ASPEED_PINCTRL_PIN(AC10), + ASPEED_PINCTRL_PIN(AC11), + ASPEED_PINCTRL_PIN(AC12), + ASPEED_PINCTRL_PIN(AC15), + ASPEED_PINCTRL_PIN(AC17), + ASPEED_PINCTRL_PIN(AC18), + ASPEED_PINCTRL_PIN(AC19), + ASPEED_PINCTRL_PIN(AC22), + ASPEED_PINCTRL_PIN(AC23), + ASPEED_PINCTRL_PIN(AC24), + ASPEED_PINCTRL_PIN(AC26), + ASPEED_PINCTRL_PIN(AC4), + ASPEED_PINCTRL_PIN(AC5), + ASPEED_PINCTRL_PIN(AC7), + ASPEED_PINCTRL_PIN(AC8), + ASPEED_PINCTRL_PIN(AC9), + ASPEED_PINCTRL_PIN(AD10), + ASPEED_PINCTRL_PIN(AD11), + ASPEED_PINCTRL_PIN(AD12), + ASPEED_PINCTRL_PIN(AD14), + ASPEED_PINCTRL_PIN(AD15), + ASPEED_PINCTRL_PIN(AD19), + ASPEED_PINCTRL_PIN(AD20), + ASPEED_PINCTRL_PIN(AD22), + ASPEED_PINCTRL_PIN(AD23), + ASPEED_PINCTRL_PIN(AD24), + ASPEED_PINCTRL_PIN(AD25), + ASPEED_PINCTRL_PIN(AD26), + ASPEED_PINCTRL_PIN(AD7), + ASPEED_PINCTRL_PIN(AD8), + ASPEED_PINCTRL_PIN(AD9), + ASPEED_PINCTRL_PIN(AE10), + ASPEED_PINCTRL_PIN(AE11), + ASPEED_PINCTRL_PIN(AE12), + ASPEED_PINCTRL_PIN(AE14), + ASPEED_PINCTRL_PIN(AE15), + ASPEED_PINCTRL_PIN(AE18), + ASPEED_PINCTRL_PIN(AE19), + ASPEED_PINCTRL_PIN(AE7), + ASPEED_PINCTRL_PIN(AE8), + ASPEED_PINCTRL_PIN(AF10), + ASPEED_PINCTRL_PIN(AF11), + ASPEED_PINCTRL_PIN(AF12), + ASPEED_PINCTRL_PIN(AF14), + ASPEED_PINCTRL_PIN(AF15), + ASPEED_PINCTRL_PIN(AF7), + ASPEED_PINCTRL_PIN(AF8), + ASPEED_PINCTRL_PIN(AF9), + ASPEED_PINCTRL_PIN(B1), + ASPEED_PINCTRL_PIN(B12), + ASPEED_PINCTRL_PIN(B13), + ASPEED_PINCTRL_PIN(B14), + ASPEED_PINCTRL_PIN(B16), + ASPEED_PINCTRL_PIN(B17), + ASPEED_PINCTRL_PIN(B18), + ASPEED_PINCTRL_PIN(B2), + ASPEED_PINCTRL_PIN(B20), + ASPEED_PINCTRL_PIN(B21), + ASPEED_PINCTRL_PIN(B22), + ASPEED_PINCTRL_PIN(B24), + ASPEED_PINCTRL_PIN(B25), + ASPEED_PINCTRL_PIN(B26), + ASPEED_PINCTRL_PIN(B3), + ASPEED_PINCTRL_PIN(C1), + ASPEED_PINCTRL_PIN(C11), + ASPEED_PINCTRL_PIN(C12), + ASPEED_PINCTRL_PIN(C13), + ASPEED_PINCTRL_PIN(C14), + ASPEED_PINCTRL_PIN(C15), + ASPEED_PINCTRL_PIN(C16), + ASPEED_PINCTRL_PIN(C17), + ASPEED_PINCTRL_PIN(C18), + ASPEED_PINCTRL_PIN(C19), + ASPEED_PINCTRL_PIN(C2), + ASPEED_PINCTRL_PIN(C20), + ASPEED_PINCTRL_PIN(C21), + ASPEED_PINCTRL_PIN(C22), + ASPEED_PINCTRL_PIN(C23), + ASPEED_PINCTRL_PIN(C24), + ASPEED_PINCTRL_PIN(C25), + ASPEED_PINCTRL_PIN(C26), + ASPEED_PINCTRL_PIN(C4), + ASPEED_PINCTRL_PIN(C5), + ASPEED_PINCTRL_PIN(C6), + ASPEED_PINCTRL_PIN(D1), + ASPEED_PINCTRL_PIN(D11), + ASPEED_PINCTRL_PIN(D12), + ASPEED_PINCTRL_PIN(D13), + ASPEED_PINCTRL_PIN(D14), + ASPEED_PINCTRL_PIN(D15), + ASPEED_PINCTRL_PIN(D16), + ASPEED_PINCTRL_PIN(D17), + ASPEED_PINCTRL_PIN(D18), + ASPEED_PINCTRL_PIN(D19), + ASPEED_PINCTRL_PIN(D2), + ASPEED_PINCTRL_PIN(D20), + ASPEED_PINCTRL_PIN(D21), + ASPEED_PINCTRL_PIN(D22), + ASPEED_PINCTRL_PIN(D23), + ASPEED_PINCTRL_PIN(D24), + ASPEED_PINCTRL_PIN(D26), + ASPEED_PINCTRL_PIN(D3), + ASPEED_PINCTRL_PIN(D4), + ASPEED_PINCTRL_PIN(D5), + ASPEED_PINCTRL_PIN(D6), + ASPEED_PINCTRL_PIN(E1), + ASPEED_PINCTRL_PIN(E11), + ASPEED_PINCTRL_PIN(E12), + ASPEED_PINCTRL_PIN(E13), + ASPEED_PINCTRL_PIN(E14), + ASPEED_PINCTRL_PIN(E15), + ASPEED_PINCTRL_PIN(E16), + ASPEED_PINCTRL_PIN(E17), + ASPEED_PINCTRL_PIN(E18), + ASPEED_PINCTRL_PIN(E19), + ASPEED_PINCTRL_PIN(E2), + ASPEED_PINCTRL_PIN(E20), + ASPEED_PINCTRL_PIN(E21), + ASPEED_PINCTRL_PIN(E22), + ASPEED_PINCTRL_PIN(E23), + ASPEED_PINCTRL_PIN(E24), + ASPEED_PINCTRL_PIN(E25), + ASPEED_PINCTRL_PIN(E26), + ASPEED_PINCTRL_PIN(E3), + ASPEED_PINCTRL_PIN(E4), + ASPEED_PINCTRL_PIN(E5), + ASPEED_PINCTRL_PIN(E6), + ASPEED_PINCTRL_PIN(F13), + ASPEED_PINCTRL_PIN(F15), + ASPEED_PINCTRL_PIN(F22), + ASPEED_PINCTRL_PIN(F23), + ASPEED_PINCTRL_PIN(F24), + ASPEED_PINCTRL_PIN(F25), + ASPEED_PINCTRL_PIN(F26), + ASPEED_PINCTRL_PIN(F4), + ASPEED_PINCTRL_PIN(F5), + ASPEED_PINCTRL_PIN(G22), + ASPEED_PINCTRL_PIN(G23), + ASPEED_PINCTRL_PIN(G24), + ASPEED_PINCTRL_PIN(G26), + ASPEED_PINCTRL_PIN(H22), + ASPEED_PINCTRL_PIN(H23), + ASPEED_PINCTRL_PIN(H24), + ASPEED_PINCTRL_PIN(H25), + ASPEED_PINCTRL_PIN(H26), + ASPEED_PINCTRL_PIN(J22), + ASPEED_PINCTRL_PIN(J23), + ASPEED_PINCTRL_PIN(J24), + ASPEED_PINCTRL_PIN(J25), + ASPEED_PINCTRL_PIN(J26), + ASPEED_PINCTRL_PIN(K23), + ASPEED_PINCTRL_PIN(K24), + ASPEED_PINCTRL_PIN(K25), + ASPEED_PINCTRL_PIN(K26), + ASPEED_PINCTRL_PIN(L23), + ASPEED_PINCTRL_PIN(L24), + ASPEED_PINCTRL_PIN(L26), + ASPEED_PINCTRL_PIN(M23), + ASPEED_PINCTRL_PIN(M24), + ASPEED_PINCTRL_PIN(M25), + ASPEED_PINCTRL_PIN(M26), + ASPEED_PINCTRL_PIN(N23), + ASPEED_PINCTRL_PIN(N24), + ASPEED_PINCTRL_PIN(N25), + ASPEED_PINCTRL_PIN(N26), + ASPEED_PINCTRL_PIN(P23), + ASPEED_PINCTRL_PIN(P24), + ASPEED_PINCTRL_PIN(P25), + ASPEED_PINCTRL_PIN(P26), + ASPEED_PINCTRL_PIN(R23), + ASPEED_PINCTRL_PIN(R24), + ASPEED_PINCTRL_PIN(R26), + ASPEED_PINCTRL_PIN(T23), + ASPEED_PINCTRL_PIN(T24), + ASPEED_PINCTRL_PIN(T25), + ASPEED_PINCTRL_PIN(T26), + ASPEED_PINCTRL_PIN(U24), + ASPEED_PINCTRL_PIN(U25), + ASPEED_PINCTRL_PIN(U26), + ASPEED_PINCTRL_PIN(V24), + ASPEED_PINCTRL_PIN(V25), + ASPEED_PINCTRL_PIN(V26), + ASPEED_PINCTRL_PIN(W23), + ASPEED_PINCTRL_PIN(W24), + ASPEED_PINCTRL_PIN(W26), + ASPEED_PINCTRL_PIN(Y1), + ASPEED_PINCTRL_PIN(Y2), + ASPEED_PINCTRL_PIN(Y23), + ASPEED_PINCTRL_PIN(Y24), + ASPEED_PINCTRL_PIN(Y25), + ASPEED_PINCTRL_PIN(Y26), + ASPEED_PINCTRL_PIN(Y3), + ASPEED_PINCTRL_PIN(Y4), + ASPEED_PINCTRL_PIN(Y5), + ASPEED_PINCTRL_PIN(AB16), + ASPEED_PINCTRL_PIN(AA17), + ASPEED_PINCTRL_PIN(AB17), + ASPEED_PINCTRL_PIN(AE16), + ASPEED_PINCTRL_PIN(AC16), + ASPEED_PINCTRL_PIN(AA16), + ASPEED_PINCTRL_PIN(AD16), + ASPEED_PINCTRL_PIN(AF25), + ASPEED_PINCTRL_PIN(AE26), + ASPEED_PINCTRL_PIN(AE25), + ASPEED_PINCTRL_PIN(AF24), +}; + +static const struct aspeed_pin_group aspeed_g6_groups[] = { + ASPEED_PINCTRL_GROUP(ADC0), + ASPEED_PINCTRL_GROUP(ADC1), + ASPEED_PINCTRL_GROUP(ADC10), + ASPEED_PINCTRL_GROUP(ADC11), + ASPEED_PINCTRL_GROUP(ADC12), + ASPEED_PINCTRL_GROUP(ADC13), + ASPEED_PINCTRL_GROUP(ADC14), + ASPEED_PINCTRL_GROUP(ADC15), + ASPEED_PINCTRL_GROUP(ADC2), + ASPEED_PINCTRL_GROUP(ADC3), + ASPEED_PINCTRL_GROUP(ADC4), + ASPEED_PINCTRL_GROUP(ADC5), + ASPEED_PINCTRL_GROUP(ADC6), + ASPEED_PINCTRL_GROUP(ADC7), + ASPEED_PINCTRL_GROUP(ADC8), + ASPEED_PINCTRL_GROUP(ADC9), + ASPEED_PINCTRL_GROUP(BMCINT), + ASPEED_PINCTRL_GROUP(ESPI), + ASPEED_PINCTRL_GROUP(ESPIALT), + ASPEED_PINCTRL_GROUP(FSI1), + ASPEED_PINCTRL_GROUP(FSI2), + ASPEED_PINCTRL_GROUP(FWSPIABR), + ASPEED_PINCTRL_GROUP(FWSPID), + ASPEED_PINCTRL_GROUP(FWQSPID), + ASPEED_PINCTRL_GROUP(FWSPIWP), + ASPEED_PINCTRL_GROUP(GPIT0), + ASPEED_PINCTRL_GROUP(GPIT1), + ASPEED_PINCTRL_GROUP(GPIT2), + ASPEED_PINCTRL_GROUP(GPIT3), + ASPEED_PINCTRL_GROUP(GPIT4), + ASPEED_PINCTRL_GROUP(GPIT5), + ASPEED_PINCTRL_GROUP(GPIT6), + ASPEED_PINCTRL_GROUP(GPIT7), + ASPEED_PINCTRL_GROUP(GPIU0), + ASPEED_PINCTRL_GROUP(GPIU1), + ASPEED_PINCTRL_GROUP(GPIU2), + ASPEED_PINCTRL_GROUP(GPIU3), + ASPEED_PINCTRL_GROUP(GPIU4), + ASPEED_PINCTRL_GROUP(GPIU5), + ASPEED_PINCTRL_GROUP(GPIU6), + ASPEED_PINCTRL_GROUP(GPIU7), + ASPEED_PINCTRL_GROUP(HVI3C3), + ASPEED_PINCTRL_GROUP(HVI3C4), + ASPEED_PINCTRL_GROUP(I2C1), + ASPEED_PINCTRL_GROUP(I2C10), + ASPEED_PINCTRL_GROUP(I2C11), + ASPEED_PINCTRL_GROUP(I2C12), + ASPEED_PINCTRL_GROUP(I2C13), + ASPEED_PINCTRL_GROUP(I2C14), + ASPEED_PINCTRL_GROUP(I2C15), + ASPEED_PINCTRL_GROUP(I2C16), + ASPEED_PINCTRL_GROUP(I2C2), + ASPEED_PINCTRL_GROUP(I2C3), + ASPEED_PINCTRL_GROUP(I2C4), + ASPEED_PINCTRL_GROUP(I2C5), + ASPEED_PINCTRL_GROUP(I2C6), + ASPEED_PINCTRL_GROUP(I2C7), + ASPEED_PINCTRL_GROUP(I2C8), + ASPEED_PINCTRL_GROUP(I2C9), + ASPEED_PINCTRL_GROUP(I3C3), + ASPEED_PINCTRL_GROUP(I3C4), + ASPEED_PINCTRL_GROUP(I3C5), + ASPEED_PINCTRL_GROUP(I3C6), + ASPEED_PINCTRL_GROUP(JTAGM), + ASPEED_PINCTRL_GROUP(LHPD), + ASPEED_PINCTRL_GROUP(LHSIRQ), + ASPEED_PINCTRL_GROUP(LPC), + ASPEED_PINCTRL_GROUP(LPCHC), + ASPEED_PINCTRL_GROUP(LPCPD), + ASPEED_PINCTRL_GROUP(LPCPME), + ASPEED_PINCTRL_GROUP(LPCSMI), + ASPEED_PINCTRL_GROUP(LSIRQ), + ASPEED_PINCTRL_GROUP(MACLINK1), + ASPEED_PINCTRL_GROUP(MACLINK2), + ASPEED_PINCTRL_GROUP(MACLINK3), + ASPEED_PINCTRL_GROUP(MACLINK4), + ASPEED_PINCTRL_GROUP(MDIO1), + ASPEED_PINCTRL_GROUP(MDIO2), + ASPEED_PINCTRL_GROUP(MDIO3), + ASPEED_PINCTRL_GROUP(MDIO4), + ASPEED_PINCTRL_GROUP(NCTS1), + ASPEED_PINCTRL_GROUP(NCTS2), + ASPEED_PINCTRL_GROUP(NCTS3), + ASPEED_PINCTRL_GROUP(NCTS4), + ASPEED_PINCTRL_GROUP(NDCD1), + ASPEED_PINCTRL_GROUP(NDCD2), + ASPEED_PINCTRL_GROUP(NDCD3), + ASPEED_PINCTRL_GROUP(NDCD4), + ASPEED_PINCTRL_GROUP(NDSR1), + ASPEED_PINCTRL_GROUP(NDSR2), + ASPEED_PINCTRL_GROUP(NDSR3), + ASPEED_PINCTRL_GROUP(NDSR4), + ASPEED_PINCTRL_GROUP(NDTR1), + ASPEED_PINCTRL_GROUP(NDTR2), + ASPEED_PINCTRL_GROUP(NDTR3), + ASPEED_PINCTRL_GROUP(NDTR4), + ASPEED_PINCTRL_GROUP(NRI1), + ASPEED_PINCTRL_GROUP(NRI2), + ASPEED_PINCTRL_GROUP(NRI3), + ASPEED_PINCTRL_GROUP(NRI4), + ASPEED_PINCTRL_GROUP(NRTS1), + ASPEED_PINCTRL_GROUP(NRTS2), + ASPEED_PINCTRL_GROUP(NRTS3), + ASPEED_PINCTRL_GROUP(NRTS4), + ASPEED_PINCTRL_GROUP(OSCCLK), + ASPEED_PINCTRL_GROUP(PEWAKE), + ASPEED_PINCTRL_GROUP(PWM0), + ASPEED_PINCTRL_GROUP(PWM1), + ASPEED_PINCTRL_GROUP(PWM10G0), + ASPEED_PINCTRL_GROUP(PWM10G1), + ASPEED_PINCTRL_GROUP(PWM11G0), + ASPEED_PINCTRL_GROUP(PWM11G1), + ASPEED_PINCTRL_GROUP(PWM12G0), + ASPEED_PINCTRL_GROUP(PWM12G1), + ASPEED_PINCTRL_GROUP(PWM13G0), + ASPEED_PINCTRL_GROUP(PWM13G1), + ASPEED_PINCTRL_GROUP(PWM14G0), + ASPEED_PINCTRL_GROUP(PWM14G1), + ASPEED_PINCTRL_GROUP(PWM15G0), + ASPEED_PINCTRL_GROUP(PWM15G1), + ASPEED_PINCTRL_GROUP(PWM2), + ASPEED_PINCTRL_GROUP(PWM3), + ASPEED_PINCTRL_GROUP(PWM4), + ASPEED_PINCTRL_GROUP(PWM5), + ASPEED_PINCTRL_GROUP(PWM6), + ASPEED_PINCTRL_GROUP(PWM7), + ASPEED_PINCTRL_GROUP(PWM8G0), + ASPEED_PINCTRL_GROUP(PWM8G1), + ASPEED_PINCTRL_GROUP(PWM9G0), + ASPEED_PINCTRL_GROUP(PWM9G1), + ASPEED_PINCTRL_GROUP(QSPI1), + ASPEED_PINCTRL_GROUP(QSPI2), + ASPEED_PINCTRL_GROUP(RGMII1), + ASPEED_PINCTRL_GROUP(RGMII2), + ASPEED_PINCTRL_GROUP(RGMII3), + ASPEED_PINCTRL_GROUP(RGMII4), + ASPEED_PINCTRL_GROUP(RMII1), + ASPEED_PINCTRL_GROUP(RMII2), + ASPEED_PINCTRL_GROUP(RMII3), + ASPEED_PINCTRL_GROUP(RMII4), + ASPEED_PINCTRL_GROUP(RXD1), + ASPEED_PINCTRL_GROUP(RXD2), + ASPEED_PINCTRL_GROUP(RXD3), + ASPEED_PINCTRL_GROUP(RXD4), + ASPEED_PINCTRL_GROUP(SALT1), + ASPEED_PINCTRL_GROUP(SALT10G0), + ASPEED_PINCTRL_GROUP(SALT10G1), + ASPEED_PINCTRL_GROUP(SALT11G0), + ASPEED_PINCTRL_GROUP(SALT11G1), + ASPEED_PINCTRL_GROUP(SALT12G0), + ASPEED_PINCTRL_GROUP(SALT12G1), + ASPEED_PINCTRL_GROUP(SALT13G0), + ASPEED_PINCTRL_GROUP(SALT13G1), + ASPEED_PINCTRL_GROUP(SALT14G0), + ASPEED_PINCTRL_GROUP(SALT14G1), + ASPEED_PINCTRL_GROUP(SALT15G0), + ASPEED_PINCTRL_GROUP(SALT15G1), + ASPEED_PINCTRL_GROUP(SALT16G0), + ASPEED_PINCTRL_GROUP(SALT16G1), + ASPEED_PINCTRL_GROUP(SALT2), + ASPEED_PINCTRL_GROUP(SALT3), + ASPEED_PINCTRL_GROUP(SALT4), + ASPEED_PINCTRL_GROUP(SALT5), + ASPEED_PINCTRL_GROUP(SALT6), + ASPEED_PINCTRL_GROUP(SALT7), + ASPEED_PINCTRL_GROUP(SALT8), + ASPEED_PINCTRL_GROUP(SALT9G0), + ASPEED_PINCTRL_GROUP(SALT9G1), + ASPEED_PINCTRL_GROUP(SD1), + ASPEED_PINCTRL_GROUP(SD2), + ASPEED_PINCTRL_GROUP(SD3), + ASPEED_PINCTRL_GROUP(SD3DAT4), + ASPEED_PINCTRL_GROUP(SD3DAT5), + ASPEED_PINCTRL_GROUP(SD3DAT6), + ASPEED_PINCTRL_GROUP(SD3DAT7), + ASPEED_PINCTRL_GROUP(SGPM1), + ASPEED_PINCTRL_GROUP(SGPS1), + ASPEED_PINCTRL_GROUP(SIOONCTRL), + ASPEED_PINCTRL_GROUP(SIOPBI), + ASPEED_PINCTRL_GROUP(SIOPBO), + ASPEED_PINCTRL_GROUP(SIOPWREQ), + ASPEED_PINCTRL_GROUP(SIOPWRGD), + ASPEED_PINCTRL_GROUP(SIOS3), + ASPEED_PINCTRL_GROUP(SIOS5), + ASPEED_PINCTRL_GROUP(SIOSCI), + ASPEED_PINCTRL_GROUP(SPI1), + ASPEED_PINCTRL_GROUP(SPI1ABR), + ASPEED_PINCTRL_GROUP(SPI1CS1), + ASPEED_PINCTRL_GROUP(SPI1WP), + ASPEED_PINCTRL_GROUP(SPI2), + ASPEED_PINCTRL_GROUP(SPI2CS1), + ASPEED_PINCTRL_GROUP(SPI2CS2), + ASPEED_PINCTRL_GROUP(TACH0), + ASPEED_PINCTRL_GROUP(TACH1), + ASPEED_PINCTRL_GROUP(TACH10), + ASPEED_PINCTRL_GROUP(TACH11), + ASPEED_PINCTRL_GROUP(TACH12), + ASPEED_PINCTRL_GROUP(TACH13), + ASPEED_PINCTRL_GROUP(TACH14), + ASPEED_PINCTRL_GROUP(TACH15), + ASPEED_PINCTRL_GROUP(TACH2), + ASPEED_PINCTRL_GROUP(TACH3), + ASPEED_PINCTRL_GROUP(TACH4), + ASPEED_PINCTRL_GROUP(TACH5), + ASPEED_PINCTRL_GROUP(TACH6), + ASPEED_PINCTRL_GROUP(TACH7), + ASPEED_PINCTRL_GROUP(TACH8), + ASPEED_PINCTRL_GROUP(TACH9), + ASPEED_PINCTRL_GROUP(THRU0), + ASPEED_PINCTRL_GROUP(THRU1), + ASPEED_PINCTRL_GROUP(THRU2), + ASPEED_PINCTRL_GROUP(THRU3), + ASPEED_PINCTRL_GROUP(TXD1), + ASPEED_PINCTRL_GROUP(TXD2), + ASPEED_PINCTRL_GROUP(TXD3), + ASPEED_PINCTRL_GROUP(TXD4), + ASPEED_PINCTRL_GROUP(UART10), + ASPEED_PINCTRL_GROUP(UART11), + ASPEED_PINCTRL_GROUP(UART12G0), + ASPEED_PINCTRL_GROUP(UART12G1), + ASPEED_PINCTRL_GROUP(UART13G0), + ASPEED_PINCTRL_GROUP(UART13G1), + ASPEED_PINCTRL_GROUP(UART6), + ASPEED_PINCTRL_GROUP(UART7), + ASPEED_PINCTRL_GROUP(UART8), + ASPEED_PINCTRL_GROUP(UART9), + ASPEED_PINCTRL_GROUP(VB), + ASPEED_PINCTRL_GROUP(VGAHS), + ASPEED_PINCTRL_GROUP(VGAVS), + ASPEED_PINCTRL_GROUP(WDTRST1), + ASPEED_PINCTRL_GROUP(WDTRST2), + ASPEED_PINCTRL_GROUP(WDTRST3), + ASPEED_PINCTRL_GROUP(WDTRST4), +}; + +static const struct aspeed_pin_function aspeed_g6_functions[] = { + ASPEED_PINCTRL_FUNC(ADC0), + ASPEED_PINCTRL_FUNC(ADC1), + ASPEED_PINCTRL_FUNC(ADC10), + ASPEED_PINCTRL_FUNC(ADC11), + ASPEED_PINCTRL_FUNC(ADC12), + ASPEED_PINCTRL_FUNC(ADC13), + ASPEED_PINCTRL_FUNC(ADC14), + ASPEED_PINCTRL_FUNC(ADC15), + ASPEED_PINCTRL_FUNC(ADC2), + ASPEED_PINCTRL_FUNC(ADC3), + ASPEED_PINCTRL_FUNC(ADC4), + ASPEED_PINCTRL_FUNC(ADC5), + ASPEED_PINCTRL_FUNC(ADC6), + ASPEED_PINCTRL_FUNC(ADC7), + ASPEED_PINCTRL_FUNC(ADC8), + ASPEED_PINCTRL_FUNC(ADC9), + ASPEED_PINCTRL_FUNC(BMCINT), + ASPEED_PINCTRL_FUNC(ESPI), + ASPEED_PINCTRL_FUNC(ESPIALT), + ASPEED_PINCTRL_FUNC(FSI1), + ASPEED_PINCTRL_FUNC(FSI2), + ASPEED_PINCTRL_FUNC(FWSPIABR), + ASPEED_PINCTRL_FUNC(FWSPID), + ASPEED_PINCTRL_FUNC(FWSPIWP), + ASPEED_PINCTRL_FUNC(GPIT0), + ASPEED_PINCTRL_FUNC(GPIT1), + ASPEED_PINCTRL_FUNC(GPIT2), + ASPEED_PINCTRL_FUNC(GPIT3), + ASPEED_PINCTRL_FUNC(GPIT4), + ASPEED_PINCTRL_FUNC(GPIT5), + ASPEED_PINCTRL_FUNC(GPIT6), + ASPEED_PINCTRL_FUNC(GPIT7), + ASPEED_PINCTRL_FUNC(GPIU0), + ASPEED_PINCTRL_FUNC(GPIU1), + ASPEED_PINCTRL_FUNC(GPIU2), + ASPEED_PINCTRL_FUNC(GPIU3), + ASPEED_PINCTRL_FUNC(GPIU4), + ASPEED_PINCTRL_FUNC(GPIU5), + ASPEED_PINCTRL_FUNC(GPIU6), + ASPEED_PINCTRL_FUNC(GPIU7), + ASPEED_PINCTRL_FUNC(I2C1), + ASPEED_PINCTRL_FUNC(I2C10), + ASPEED_PINCTRL_FUNC(I2C11), + ASPEED_PINCTRL_FUNC(I2C12), + ASPEED_PINCTRL_FUNC(I2C13), + ASPEED_PINCTRL_FUNC(I2C14), + ASPEED_PINCTRL_FUNC(I2C15), + ASPEED_PINCTRL_FUNC(I2C16), + ASPEED_PINCTRL_FUNC(I2C2), + ASPEED_PINCTRL_FUNC(I2C3), + ASPEED_PINCTRL_FUNC(I2C4), + ASPEED_PINCTRL_FUNC(I2C5), + ASPEED_PINCTRL_FUNC(I2C6), + ASPEED_PINCTRL_FUNC(I2C7), + ASPEED_PINCTRL_FUNC(I2C8), + ASPEED_PINCTRL_FUNC(I2C9), + ASPEED_PINCTRL_FUNC(I3C3), + ASPEED_PINCTRL_FUNC(I3C4), + ASPEED_PINCTRL_FUNC(I3C5), + ASPEED_PINCTRL_FUNC(I3C6), + ASPEED_PINCTRL_FUNC(JTAGM), + ASPEED_PINCTRL_FUNC(LHPD), + ASPEED_PINCTRL_FUNC(LHSIRQ), + ASPEED_PINCTRL_FUNC(LPC), + ASPEED_PINCTRL_FUNC(LPCHC), + ASPEED_PINCTRL_FUNC(LPCPD), + ASPEED_PINCTRL_FUNC(LPCPME), + ASPEED_PINCTRL_FUNC(LPCSMI), + ASPEED_PINCTRL_FUNC(LSIRQ), + ASPEED_PINCTRL_FUNC(MACLINK1), + ASPEED_PINCTRL_FUNC(MACLINK2), + ASPEED_PINCTRL_FUNC(MACLINK3), + ASPEED_PINCTRL_FUNC(MACLINK4), + ASPEED_PINCTRL_FUNC(MDIO1), + ASPEED_PINCTRL_FUNC(MDIO2), + ASPEED_PINCTRL_FUNC(MDIO3), + ASPEED_PINCTRL_FUNC(MDIO4), + ASPEED_PINCTRL_FUNC(NCTS1), + ASPEED_PINCTRL_FUNC(NCTS2), + ASPEED_PINCTRL_FUNC(NCTS3), + ASPEED_PINCTRL_FUNC(NCTS4), + ASPEED_PINCTRL_FUNC(NDCD1), + ASPEED_PINCTRL_FUNC(NDCD2), + ASPEED_PINCTRL_FUNC(NDCD3), + ASPEED_PINCTRL_FUNC(NDCD4), + ASPEED_PINCTRL_FUNC(NDSR1), + ASPEED_PINCTRL_FUNC(NDSR2), + ASPEED_PINCTRL_FUNC(NDSR3), + ASPEED_PINCTRL_FUNC(NDSR4), + ASPEED_PINCTRL_FUNC(NDTR1), + ASPEED_PINCTRL_FUNC(NDTR2), + ASPEED_PINCTRL_FUNC(NDTR3), + ASPEED_PINCTRL_FUNC(NDTR4), + ASPEED_PINCTRL_FUNC(NRI1), + ASPEED_PINCTRL_FUNC(NRI2), + ASPEED_PINCTRL_FUNC(NRI3), + ASPEED_PINCTRL_FUNC(NRI4), + ASPEED_PINCTRL_FUNC(NRTS1), + ASPEED_PINCTRL_FUNC(NRTS2), + ASPEED_PINCTRL_FUNC(NRTS3), + ASPEED_PINCTRL_FUNC(NRTS4), + ASPEED_PINCTRL_FUNC(OSCCLK), + ASPEED_PINCTRL_FUNC(PEWAKE), + ASPEED_PINCTRL_FUNC(PWM0), + ASPEED_PINCTRL_FUNC(PWM1), + ASPEED_PINCTRL_FUNC(PWM10), + ASPEED_PINCTRL_FUNC(PWM11), + ASPEED_PINCTRL_FUNC(PWM12), + ASPEED_PINCTRL_FUNC(PWM13), + ASPEED_PINCTRL_FUNC(PWM14), + ASPEED_PINCTRL_FUNC(PWM15), + ASPEED_PINCTRL_FUNC(PWM2), + ASPEED_PINCTRL_FUNC(PWM3), + ASPEED_PINCTRL_FUNC(PWM4), + ASPEED_PINCTRL_FUNC(PWM5), + ASPEED_PINCTRL_FUNC(PWM6), + ASPEED_PINCTRL_FUNC(PWM7), + ASPEED_PINCTRL_FUNC(PWM8), + ASPEED_PINCTRL_FUNC(PWM9), + ASPEED_PINCTRL_FUNC(RGMII1), + ASPEED_PINCTRL_FUNC(RGMII2), + ASPEED_PINCTRL_FUNC(RGMII3), + ASPEED_PINCTRL_FUNC(RGMII4), + ASPEED_PINCTRL_FUNC(RMII1), + ASPEED_PINCTRL_FUNC(RMII2), + ASPEED_PINCTRL_FUNC(RMII3), + ASPEED_PINCTRL_FUNC(RMII4), + ASPEED_PINCTRL_FUNC(RXD1), + ASPEED_PINCTRL_FUNC(RXD2), + ASPEED_PINCTRL_FUNC(RXD3), + ASPEED_PINCTRL_FUNC(RXD4), + ASPEED_PINCTRL_FUNC(SALT1), + ASPEED_PINCTRL_FUNC(SALT10), + ASPEED_PINCTRL_FUNC(SALT11), + ASPEED_PINCTRL_FUNC(SALT12), + ASPEED_PINCTRL_FUNC(SALT13), + ASPEED_PINCTRL_FUNC(SALT14), + ASPEED_PINCTRL_FUNC(SALT15), + ASPEED_PINCTRL_FUNC(SALT16), + ASPEED_PINCTRL_FUNC(SALT2), + ASPEED_PINCTRL_FUNC(SALT3), + ASPEED_PINCTRL_FUNC(SALT4), + ASPEED_PINCTRL_FUNC(SALT5), + ASPEED_PINCTRL_FUNC(SALT6), + ASPEED_PINCTRL_FUNC(SALT7), + ASPEED_PINCTRL_FUNC(SALT8), + ASPEED_PINCTRL_FUNC(SALT9), + ASPEED_PINCTRL_FUNC(SD1), + ASPEED_PINCTRL_FUNC(SD2), + ASPEED_PINCTRL_FUNC(SD3), + ASPEED_PINCTRL_FUNC(SD3DAT4), + ASPEED_PINCTRL_FUNC(SD3DAT5), + ASPEED_PINCTRL_FUNC(SD3DAT6), + ASPEED_PINCTRL_FUNC(SD3DAT7), + ASPEED_PINCTRL_FUNC(SGPM1), + ASPEED_PINCTRL_FUNC(SGPS1), + ASPEED_PINCTRL_FUNC(SIOONCTRL), + ASPEED_PINCTRL_FUNC(SIOPBI), + ASPEED_PINCTRL_FUNC(SIOPBO), + ASPEED_PINCTRL_FUNC(SIOPWREQ), + ASPEED_PINCTRL_FUNC(SIOPWRGD), + ASPEED_PINCTRL_FUNC(SIOS3), + ASPEED_PINCTRL_FUNC(SIOS5), + ASPEED_PINCTRL_FUNC(SIOSCI), + ASPEED_PINCTRL_FUNC(SPI1), + ASPEED_PINCTRL_FUNC(SPI1ABR), + ASPEED_PINCTRL_FUNC(SPI1CS1), + ASPEED_PINCTRL_FUNC(SPI1WP), + ASPEED_PINCTRL_FUNC(SPI2), + ASPEED_PINCTRL_FUNC(SPI2CS1), + ASPEED_PINCTRL_FUNC(SPI2CS2), + ASPEED_PINCTRL_FUNC(TACH0), + ASPEED_PINCTRL_FUNC(TACH1), + ASPEED_PINCTRL_FUNC(TACH10), + ASPEED_PINCTRL_FUNC(TACH11), + ASPEED_PINCTRL_FUNC(TACH12), + ASPEED_PINCTRL_FUNC(TACH13), + ASPEED_PINCTRL_FUNC(TACH14), + ASPEED_PINCTRL_FUNC(TACH15), + ASPEED_PINCTRL_FUNC(TACH2), + ASPEED_PINCTRL_FUNC(TACH3), + ASPEED_PINCTRL_FUNC(TACH4), + ASPEED_PINCTRL_FUNC(TACH5), + ASPEED_PINCTRL_FUNC(TACH6), + ASPEED_PINCTRL_FUNC(TACH7), + ASPEED_PINCTRL_FUNC(TACH8), + ASPEED_PINCTRL_FUNC(TACH9), + ASPEED_PINCTRL_FUNC(THRU0), + ASPEED_PINCTRL_FUNC(THRU1), + ASPEED_PINCTRL_FUNC(THRU2), + ASPEED_PINCTRL_FUNC(THRU3), + ASPEED_PINCTRL_FUNC(TXD1), + ASPEED_PINCTRL_FUNC(TXD2), + ASPEED_PINCTRL_FUNC(TXD3), + ASPEED_PINCTRL_FUNC(TXD4), + ASPEED_PINCTRL_FUNC(UART10), + ASPEED_PINCTRL_FUNC(UART11), + ASPEED_PINCTRL_FUNC(UART12), + ASPEED_PINCTRL_FUNC(UART13), + ASPEED_PINCTRL_FUNC(UART6), + ASPEED_PINCTRL_FUNC(UART7), + ASPEED_PINCTRL_FUNC(UART8), + ASPEED_PINCTRL_FUNC(UART9), + ASPEED_PINCTRL_FUNC(VB), + ASPEED_PINCTRL_FUNC(VGAHS), + ASPEED_PINCTRL_FUNC(VGAVS), + ASPEED_PINCTRL_FUNC(WDTRST1), + ASPEED_PINCTRL_FUNC(WDTRST2), + ASPEED_PINCTRL_FUNC(WDTRST3), + ASPEED_PINCTRL_FUNC(WDTRST4), +}; + +/** + * Configure a pin's signal by applying an expression's descriptor state for + * all descriptors in the expression. + * + * @ctx: The pinmux context + * @expr: The expression associated with the function whose signal is to be + * configured + * @enable: true to enable an function's signal through a pin's signal + * expression, false to disable the function's signal + * + * Return: 0 if the expression is configured as requested and a negative error + * code otherwise + */ +static int aspeed_g6_sig_expr_set(struct aspeed_pinmux_data *ctx, + const struct aspeed_sig_expr *expr, + bool enable) +{ + int ret; + int i; + + for (i = 0; i < expr->ndescs; i++) { + const struct aspeed_sig_desc *desc = &expr->descs[i]; + u32 pattern = enable ? desc->enable : desc->disable; + u32 val = (pattern << __ffs(desc->mask)); + bool is_strap; + + if (!ctx->maps[desc->ip]) + return -ENODEV; + + WARN_ON(desc->ip != ASPEED_IP_SCU); + is_strap = desc->reg == SCU500 || desc->reg == SCU510; + + if (is_strap) { + /* + * The AST2600 has write protection mask registers for + * the hardware strapping in SCU508 and SCU518. Assume + * that if the platform doesn't want the strapping + * values changed that it has set the write mask. + * + * The strapping registers implement write-1-clear + * behaviour. SCU500 is paired with clear writes on + * SCU504, likewise SCU510 is paired with SCU514. + */ + u32 clear = ~val & desc->mask; + u32 w1c = desc->reg + 4; + + if (clear) + ret = regmap_update_bits(ctx->maps[desc->ip], + w1c, desc->mask, + clear); + } + + ret = regmap_update_bits(ctx->maps[desc->ip], desc->reg, + desc->mask, val); + if (ret) + return ret; + } + + ret = aspeed_sig_expr_eval(ctx, expr, enable); + if (ret < 0) + return ret; + + if (!ret) + return -EPERM; + return 0; +} + +static const struct aspeed_pinmux_ops aspeed_g5_ops = { + .set = aspeed_g6_sig_expr_set, +}; + +static struct aspeed_pinctrl_data aspeed_g6_pinctrl_data = { + .pins = aspeed_g6_pins, + .npins = ARRAY_SIZE(aspeed_g6_pins), + .pinmux = { + .ops = &aspeed_g5_ops, + .groups = aspeed_g6_groups, + .ngroups = ARRAY_SIZE(aspeed_g6_groups), + .functions = aspeed_g6_functions, + .nfunctions = ARRAY_SIZE(aspeed_g6_functions), + }, +}; + +static const struct pinmux_ops aspeed_g6_pinmux_ops = { + .get_functions_count = aspeed_pinmux_get_fn_count, + .get_function_name = aspeed_pinmux_get_fn_name, + .get_function_groups = aspeed_pinmux_get_fn_groups, + .set_mux = aspeed_pinmux_set_mux, + .gpio_request_enable = aspeed_gpio_request_enable, + .strict = true, +}; + +static const struct pinctrl_ops aspeed_g6_pinctrl_ops = { + .get_groups_count = aspeed_pinctrl_get_groups_count, + .get_group_name = aspeed_pinctrl_get_group_name, + .get_group_pins = aspeed_pinctrl_get_group_pins, + .pin_dbg_show = aspeed_pinctrl_pin_dbg_show, + .dt_node_to_map = pinconf_generic_dt_node_to_map_all, + .dt_free_map = pinctrl_utils_free_map, +}; + +static struct pinctrl_desc aspeed_g6_pinctrl_desc = { + .name = "aspeed-g6-pinctrl", + .pins = aspeed_g6_pins, + .npins = ARRAY_SIZE(aspeed_g6_pins), + .pctlops = &aspeed_g6_pinctrl_ops, + .pmxops = &aspeed_g6_pinmux_ops, +}; + +static int aspeed_g6_pinctrl_probe(struct platform_device *pdev) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(aspeed_g6_pins); i++) + aspeed_g6_pins[i].number = i; + + return aspeed_pinctrl_probe(pdev, &aspeed_g6_pinctrl_desc, + &aspeed_g6_pinctrl_data); +} + +static const struct of_device_id aspeed_g6_pinctrl_of_match[] = { + { .compatible = "aspeed,ast2600-pinctrl", }, + { }, +}; + +static struct platform_driver aspeed_g6_pinctrl_driver = { + .probe = aspeed_g6_pinctrl_probe, + .driver = { + .name = "aspeed-g6-pinctrl", + .of_match_table = aspeed_g6_pinctrl_of_match, + }, +}; + +static int aspeed_g6_pinctrl_init(void) +{ + return platform_driver_register(&aspeed_g6_pinctrl_driver); +} + +arch_initcall(aspeed_g6_pinctrl_init); diff --git a/drivers/pinctrl/aspeed/pinmux-aspeed.h b/drivers/pinctrl/aspeed/pinmux-aspeed.h index db3457c86f48..a2c0d52e4f7b 100644 --- a/drivers/pinctrl/aspeed/pinmux-aspeed.h +++ b/drivers/pinctrl/aspeed/pinmux-aspeed.h @@ -162,10 +162,11 @@ * * Enabling lower priority signals requires higher priority signals be * disabled * - * * A function represents a set of signals; functions are distinct if their - * sets of signals are not equal + * * A function represents a set of signals; functions are distinct if they + * do not share a subset of signals (and may be distinct if they are a + * strict subset). * - * * Signals participate in one or more functions + * * Signals participate in one or more functions or groups * * * A function is described by an expression of one or more signal * descriptors, which compare bit values in a register @@ -507,20 +508,21 @@ struct aspeed_pin_desc { * @idx: The bit index in the register */ #define SIG_DESC_SET(reg, idx) SIG_DESC_IP_BIT(ASPEED_IP_SCU, reg, idx, 1) +#define SIG_DESC_CLEAR(reg, idx) SIG_DESC_IP_BIT(ASPEED_IP_SCU, reg, idx, 0) -#define SIG_DESC_LIST_SYM(sig, func) sig_descs_ ## sig ## _ ## func -#define SIG_DESC_LIST_DECL(sig, func, ...) \ - static const struct aspeed_sig_desc SIG_DESC_LIST_SYM(sig, func)[] = \ +#define SIG_DESC_LIST_SYM(sig, group) sig_descs_ ## sig ## _ ## group +#define SIG_DESC_LIST_DECL(sig, group, ...) \ + static const struct aspeed_sig_desc SIG_DESC_LIST_SYM(sig, group)[] = \ { __VA_ARGS__ } -#define SIG_EXPR_SYM(sig, func) sig_expr_ ## sig ## _ ## func -#define SIG_EXPR_DECL_(sig, func) \ - static const struct aspeed_sig_expr SIG_EXPR_SYM(sig, func) = \ +#define SIG_EXPR_SYM(sig, group) sig_expr_ ## sig ## _ ## group +#define SIG_EXPR_DECL_(sig, group, func) \ + static const struct aspeed_sig_expr SIG_EXPR_SYM(sig, group) = \ { \ .signal = #sig, \ .function = #func, \ - .ndescs = ARRAY_SIZE(SIG_DESC_LIST_SYM(sig, func)), \ - .descs = &(SIG_DESC_LIST_SYM(sig, func))[0], \ + .ndescs = ARRAY_SIZE(SIG_DESC_LIST_SYM(sig, group)), \ + .descs = &(SIG_DESC_LIST_SYM(sig, group))[0], \ } /** @@ -533,16 +535,16 @@ struct aspeed_pin_desc { * * For example, the following declares the ROMD8 signal for the ROM16 function: * - * SIG_EXPR_DECL(ROMD8, ROM16, SIG_DESC_SET(SCU90, 6)); + * SIG_EXPR_DECL(ROMD8, ROM16, ROM16, SIG_DESC_SET(SCU90, 6)); * * And with multiple signal descriptors: * - * SIG_EXPR_DECL(ROMD8, ROM16S, SIG_DESC_SET(HW_STRAP1, 4), + * SIG_EXPR_DECL(ROMD8, ROM16S, ROM16S, SIG_DESC_SET(HW_STRAP1, 4), * { HW_STRAP1, GENMASK(1, 0), 0, 0 }); */ -#define SIG_EXPR_DECL(sig, func, ...) \ - SIG_DESC_LIST_DECL(sig, func, __VA_ARGS__); \ - SIG_EXPR_DECL_(sig, func) +#define SIG_EXPR_DECL(sig, group, func, ...) \ + SIG_DESC_LIST_DECL(sig, group, __VA_ARGS__); \ + SIG_EXPR_DECL_(sig, group, func) /** * Declare a pointer to a signal expression @@ -550,9 +552,9 @@ struct aspeed_pin_desc { * @sig: The macro symbol name for the signal (subjected to token pasting) * @func: The macro symbol name for the function (subjected to token pasting) */ -#define SIG_EXPR_PTR(sig, func) (&SIG_EXPR_SYM(sig, func)) +#define SIG_EXPR_PTR(sig, group) (&SIG_EXPR_SYM(sig, group)) -#define SIG_EXPR_LIST_SYM(sig) sig_exprs_ ## sig +#define SIG_EXPR_LIST_SYM(sig, group) sig_exprs_ ## sig ## _ ## group /** * Declare a signal expression list for reference in a struct aspeed_pin_prio. @@ -563,80 +565,101 @@ struct aspeed_pin_desc { * For example, the 16-bit ROM bus can be enabled by one of two possible signal * expressions: * - * SIG_EXPR_DECL(ROMD8, ROM16, SIG_DESC_SET(SCU90, 6)); - * SIG_EXPR_DECL(ROMD8, ROM16S, SIG_DESC_SET(HW_STRAP1, 4), + * SIG_EXPR_DECL(ROMD8, ROM16, ROM16, SIG_DESC_SET(SCU90, 6)); + * SIG_EXPR_DECL(ROMD8, ROM16S, ROM16S, SIG_DESC_SET(HW_STRAP1, 4), * { HW_STRAP1, GENMASK(1, 0), 0, 0 }); * SIG_EXPR_LIST_DECL(ROMD8, SIG_EXPR_PTR(ROMD8, ROM16), * SIG_EXPR_PTR(ROMD8, ROM16S)); */ -#define SIG_EXPR_LIST_DECL(sig, ...) \ - static const struct aspeed_sig_expr *SIG_EXPR_LIST_SYM(sig)[] = \ +#define SIG_EXPR_LIST_DECL(sig, group, ...) \ + static const struct aspeed_sig_expr *SIG_EXPR_LIST_SYM(sig, group)[] =\ { __VA_ARGS__, NULL } +#define stringify(x) #x +#define istringify(x) stringify(x) + +/** + * Create an expression symbol alias from (signal, group) to (pin, signal). + * + * @pin: The pin number + * @sig: The signal name + * @group: The name of the group of which the pin is a member that is + * associated with the function's signal + * + * Using an alias in this way enables detection of copy/paste errors (defining + * the signal for a group multiple times) whilst enabling multiple pin groups + * to exist for a signal without intrusive side-effects on defining the list of + * signals available on a pin. + */ +#define SIG_EXPR_LIST_ALIAS(pin, sig, group) \ + static const struct aspeed_sig_expr *\ + SIG_EXPR_LIST_SYM(pin, sig)[ARRAY_SIZE(SIG_EXPR_LIST_SYM(sig, group))] \ + __attribute__((alias(istringify(SIG_EXPR_LIST_SYM(sig, group))))) + /** * A short-hand macro for declaring a function expression and an expression - * list with a single function. + * list with a single expression (SE) and a single group (SG) of pins. * - * @func: A macro symbol name for the function (is subjected to token pasting) + * @pin: The pin the signal will be routed to + * @sig: The signal that will be routed to the pin for the function + * @func: A macro symbol name for the function * @...: Function descriptors that define the function expression * * For example, signal NCTS6 participates in its own function with one group: * - * SIG_EXPR_LIST_DECL_SINGLE(NCTS6, NCTS6, SIG_DESC_SET(SCU90, 7)); + * SIG_EXPR_LIST_DECL_SINGLE(A18, NCTS6, NCTS6, SIG_DESC_SET(SCU90, 7)); */ -#define SIG_EXPR_LIST_DECL_SINGLE(sig, func, ...) \ +#define SIG_EXPR_LIST_DECL_SESG(pin, sig, func, ...) \ SIG_DESC_LIST_DECL(sig, func, __VA_ARGS__); \ - SIG_EXPR_DECL_(sig, func); \ - SIG_EXPR_LIST_DECL(sig, SIG_EXPR_PTR(sig, func)) + SIG_EXPR_DECL_(sig, func, func); \ + SIG_EXPR_LIST_DECL(sig, func, SIG_EXPR_PTR(sig, func)); \ + SIG_EXPR_LIST_ALIAS(pin, sig, func) + +/** + * Similar to the above, but for pins with a single expression (SE) and + * multiple groups (MG) of pins. + * + * @pin: The pin the signal will be routed to + * @sig: The signal that will be routed to the pin for the function + * @group: The name of the function's pin group in which the pin participates + * @func: A macro symbol name for the function + * @...: Function descriptors that define the function expression + */ +#define SIG_EXPR_LIST_DECL_SEMG(pin, sig, group, func, ...) \ + SIG_DESC_LIST_DECL(sig, group, __VA_ARGS__); \ + SIG_EXPR_DECL_(sig, group, func); \ + SIG_EXPR_LIST_DECL(sig, group, SIG_EXPR_PTR(sig, group)); \ + SIG_EXPR_LIST_ALIAS(pin, sig, group) -#define SIG_EXPR_LIST_DECL_DUAL(sig, f0, f1) \ - SIG_EXPR_LIST_DECL(sig, SIG_EXPR_PTR(sig, f0), SIG_EXPR_PTR(sig, f1)) +/** + * Similar to the above, but for pins with a dual expressions (DE) and + * and a single group (SG) of pins. + * + * @pin: The pin the signal will be routed to + * @sig: The signal that will be routed to the pin for the function + * @group: The name of the function's pin group in which the pin participates + * @func: A macro symbol name for the function + * @...: Function descriptors that define the function expression + */ +#define SIG_EXPR_LIST_DECL_DESG(pin, sig, f0, f1) \ + SIG_EXPR_LIST_DECL(sig, f0, \ + SIG_EXPR_PTR(sig, f0), \ + SIG_EXPR_PTR(sig, f1)); \ + SIG_EXPR_LIST_ALIAS(pin, sig, f0) -#define SIG_EXPR_LIST_PTR(sig) (&SIG_EXPR_LIST_SYM(sig)[0]) +#define SIG_EXPR_LIST_PTR(sig, group) SIG_EXPR_LIST_SYM(sig, group) #define PIN_EXPRS_SYM(pin) pin_exprs_ ## pin #define PIN_EXPRS_PTR(pin) (&PIN_EXPRS_SYM(pin)[0]) #define PIN_SYM(pin) pin_ ## pin -#define MS_PIN_DECL_(pin, ...) \ +#define PIN_DECL_(pin, ...) \ static const struct aspeed_sig_expr **PIN_EXPRS_SYM(pin)[] = \ { __VA_ARGS__, NULL }; \ static const struct aspeed_pin_desc PIN_SYM(pin) = \ { #pin, PIN_EXPRS_PTR(pin) } /** - * Declare a multi-signal pin - * - * @pin: The pin number - * @other: Macro name for "other" functionality (subjected to stringification) - * @high: Macro name for the highest priority signal functions - * @low: Macro name for the low signal functions - * - * For example: - * - * #define A8 56 - * SIG_EXPR_DECL(ROMD8, ROM16, SIG_DESC_SET(SCU90, 6)); - * SIG_EXPR_DECL(ROMD8, ROM16S, SIG_DESC_SET(HW_STRAP1, 4), - * { HW_STRAP1, GENMASK(1, 0), 0, 0 }); - * SIG_EXPR_LIST_DECL(ROMD8, SIG_EXPR_PTR(ROMD8, ROM16), - * SIG_EXPR_PTR(ROMD8, ROM16S)); - * SIG_EXPR_LIST_DECL_SINGLE(NCTS6, NCTS6, SIG_DESC_SET(SCU90, 7)); - * MS_PIN_DECL(A8, GPIOH0, ROMD8, NCTS6); - */ -#define MS_PIN_DECL(pin, other, high, low) \ - SIG_EXPR_LIST_DECL_SINGLE(other, other); \ - MS_PIN_DECL_(pin, \ - SIG_EXPR_LIST_PTR(high), \ - SIG_EXPR_LIST_PTR(low), \ - SIG_EXPR_LIST_PTR(other)) - -#define PIN_GROUP_SYM(func) pins_ ## func -#define FUNC_GROUP_SYM(func) groups_ ## func -#define FUNC_GROUP_DECL(func, ...) \ - static const int PIN_GROUP_SYM(func)[] = { __VA_ARGS__ }; \ - static const char *FUNC_GROUP_SYM(func)[] = { #func } - -/** * Declare a single signal pin * * @pin: The pin number @@ -647,11 +670,12 @@ struct aspeed_pin_desc { * * #define E3 80 * SIG_EXPR_LIST_DECL_SINGLE(SCL5, I2C5, I2C5_DESC); - * SS_PIN_DECL(E3, GPIOK0, SCL5); + * PIN_DECL_1(E3, GPIOK0, SCL5); */ -#define SS_PIN_DECL(pin, other, sig) \ - SIG_EXPR_LIST_DECL_SINGLE(other, other); \ - MS_PIN_DECL_(pin, SIG_EXPR_LIST_PTR(sig), SIG_EXPR_LIST_PTR(other)) +#define PIN_DECL_1(pin, other, sig) \ + SIG_EXPR_LIST_DECL_SESG(pin, other, other); \ + PIN_DECL_(pin, SIG_EXPR_LIST_PTR(pin, sig), \ + SIG_EXPR_LIST_PTR(pin, other)) /** * Single signal, single function pin declaration @@ -666,14 +690,63 @@ struct aspeed_pin_desc { * SSSF_PIN_DECL(A4, GPIOA2, TIMER3, SIG_DESC_SET(SCU80, 2)); */ #define SSSF_PIN_DECL(pin, other, sig, ...) \ - SIG_EXPR_LIST_DECL_SINGLE(sig, sig, __VA_ARGS__); \ - SIG_EXPR_LIST_DECL_SINGLE(other, other); \ - MS_PIN_DECL_(pin, SIG_EXPR_LIST_PTR(sig), SIG_EXPR_LIST_PTR(other)); \ + SIG_EXPR_LIST_DECL_SESG(pin, sig, sig, __VA_ARGS__); \ + SIG_EXPR_LIST_DECL_SESG(pin, other, other); \ + PIN_DECL_(pin, SIG_EXPR_LIST_PTR(pin, sig), \ + SIG_EXPR_LIST_PTR(pin, other)); \ FUNC_GROUP_DECL(sig, pin) +/** + * Declare a two-signal pin + * + * @pin: The pin number + * @other: Macro name for "other" functionality (subjected to stringification) + * @high: Macro name for the highest priority signal functions + * @low: Macro name for the low signal functions + * + * For example: + * + * #define A8 56 + * SIG_EXPR_DECL(ROMD8, ROM16, SIG_DESC_SET(SCU90, 6)); + * SIG_EXPR_DECL(ROMD8, ROM16S, SIG_DESC_SET(HW_STRAP1, 4), + * { HW_STRAP1, GENMASK(1, 0), 0, 0 }); + * SIG_EXPR_LIST_DECL(ROMD8, SIG_EXPR_PTR(ROMD8, ROM16), + * SIG_EXPR_PTR(ROMD8, ROM16S)); + * SIG_EXPR_LIST_DECL_SINGLE(NCTS6, NCTS6, SIG_DESC_SET(SCU90, 7)); + * PIN_DECL_2(A8, GPIOH0, ROMD8, NCTS6); + */ +#define PIN_DECL_2(pin, other, high, low) \ + SIG_EXPR_LIST_DECL_SESG(pin, other, other); \ + PIN_DECL_(pin, \ + SIG_EXPR_LIST_PTR(pin, high), \ + SIG_EXPR_LIST_PTR(pin, low), \ + SIG_EXPR_LIST_PTR(pin, other)) + +#define PIN_DECL_3(pin, other, high, medium, low) \ + SIG_EXPR_LIST_DECL_SESG(pin, other, other); \ + PIN_DECL_(pin, \ + SIG_EXPR_LIST_PTR(pin, high), \ + SIG_EXPR_LIST_PTR(pin, medium), \ + SIG_EXPR_LIST_PTR(pin, low), \ + SIG_EXPR_LIST_PTR(pin, other)) + +#define GROUP_SYM(group) group_pins_ ## group +#define GROUP_DECL(group, ...) \ + static const int GROUP_SYM(group)[] = { __VA_ARGS__ } + +#define FUNC_SYM(func) func_groups_ ## func +#define FUNC_DECL_(func, ...) \ + static const char *FUNC_SYM(func)[] = { __VA_ARGS__ } + +#define FUNC_DECL_2(func, one, two) FUNC_DECL_(func, #one, #two) + +#define FUNC_GROUP_DECL(func, ...) \ + GROUP_DECL(func, __VA_ARGS__); \ + FUNC_DECL_(func, #func) + #define GPIO_PIN_DECL(pin, gpio) \ - SIG_EXPR_LIST_DECL_SINGLE(gpio, gpio); \ - MS_PIN_DECL_(pin, SIG_EXPR_LIST_PTR(gpio)) + SIG_EXPR_LIST_DECL_SESG(pin, gpio, gpio); \ + PIN_DECL_(pin, SIG_EXPR_LIST_PTR(pin, gpio)) struct aspeed_pin_group { const char *name; @@ -683,8 +756,8 @@ struct aspeed_pin_group { #define ASPEED_PINCTRL_GROUP(name_) { \ .name = #name_, \ - .pins = &(PIN_GROUP_SYM(name_))[0], \ - .npins = ARRAY_SIZE(PIN_GROUP_SYM(name_)), \ + .pins = &(GROUP_SYM(name_))[0], \ + .npins = ARRAY_SIZE(GROUP_SYM(name_)), \ } struct aspeed_pin_function { @@ -695,8 +768,8 @@ struct aspeed_pin_function { #define ASPEED_PINCTRL_FUNC(name_, ...) { \ .name = #name_, \ - .groups = &FUNC_GROUP_SYM(name_)[0], \ - .ngroups = ARRAY_SIZE(FUNC_GROUP_SYM(name_)), \ + .groups = &FUNC_SYM(name_)[0], \ + .ngroups = ARRAY_SIZE(FUNC_SYM(name_)), \ } struct aspeed_pinmux_data; diff --git a/drivers/pinctrl/bcm/pinctrl-bcm2835.c b/drivers/pinctrl/bcm/pinctrl-bcm2835.c index 183d1ffe6a75..0de1a3a96984 100644 --- a/drivers/pinctrl/bcm/pinctrl-bcm2835.c +++ b/drivers/pinctrl/bcm/pinctrl-bcm2835.c @@ -57,19 +57,27 @@ #define GPAFEN0 0x88 /* Pin Async Falling Edge Detect */ #define GPPUD 0x94 /* Pin Pull-up/down Enable */ #define GPPUDCLK0 0x98 /* Pin Pull-up/down Enable Clock */ +#define GP_GPIO_PUP_PDN_CNTRL_REG0 0xe4 /* 2711 Pin Pull-up/down select */ #define FSEL_REG(p) (GPFSEL0 + (((p) / 10) * 4)) #define FSEL_SHIFT(p) (((p) % 10) * 3) #define GPIO_REG_OFFSET(p) ((p) / 32) #define GPIO_REG_SHIFT(p) ((p) % 32) +#define PUD_2711_MASK 0x3 +#define PUD_2711_REG_OFFSET(p) ((p) / 16) +#define PUD_2711_REG_SHIFT(p) (((p) % 16) * 2) + /* argument: bcm2835_pinconf_pull */ #define BCM2835_PINCONF_PARAM_PULL (PIN_CONFIG_END + 1) +#define BCM2711_PULL_NONE 0x0 +#define BCM2711_PULL_UP 0x1 +#define BCM2711_PULL_DOWN 0x2 + struct bcm2835_pinctrl { struct device *dev; void __iomem *base; - int irq[BCM2835_NUM_IRQS]; /* note: locking assumes each bank will have its own unsigned long */ unsigned long enabled_irq_map[BCM2835_NUM_BANKS]; @@ -373,14 +381,14 @@ static void bcm2835_gpio_irq_handler(struct irq_desc *desc) int group; int i; - for (i = 0; i < ARRAY_SIZE(pc->irq); i++) { - if (pc->irq[i] == irq) { + for (i = 0; i < BCM2835_NUM_IRQS; i++) { + if (chip->irq.parents[i] == irq) { group = i; break; } } /* This should not happen, every IRQ has a bank */ - if (i == ARRAY_SIZE(pc->irq)) + if (i == BCM2835_NUM_IRQS) BUG(); chained_irq_enter(host_chip, desc); @@ -975,6 +983,77 @@ static const struct pinconf_ops bcm2835_pinconf_ops = { .pin_config_set = bcm2835_pinconf_set, }; +static void bcm2711_pull_config_set(struct bcm2835_pinctrl *pc, + unsigned int pin, unsigned int arg) +{ + u32 shifter; + u32 value; + u32 off; + + off = PUD_2711_REG_OFFSET(pin); + shifter = PUD_2711_REG_SHIFT(pin); + + value = bcm2835_gpio_rd(pc, GP_GPIO_PUP_PDN_CNTRL_REG0 + (off * 4)); + value &= ~(PUD_2711_MASK << shifter); + value |= (arg << shifter); + bcm2835_gpio_wr(pc, GP_GPIO_PUP_PDN_CNTRL_REG0 + (off * 4), value); +} + +static int bcm2711_pinconf_set(struct pinctrl_dev *pctldev, + unsigned int pin, unsigned long *configs, + unsigned int num_configs) +{ + struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev); + u32 param, arg; + int i; + + for (i = 0; i < num_configs; i++) { + param = pinconf_to_config_param(configs[i]); + arg = pinconf_to_config_argument(configs[i]); + + switch (param) { + /* convert legacy brcm,pull */ + case BCM2835_PINCONF_PARAM_PULL: + if (arg == BCM2835_PUD_UP) + arg = BCM2711_PULL_UP; + else if (arg == BCM2835_PUD_DOWN) + arg = BCM2711_PULL_DOWN; + else + arg = BCM2711_PULL_NONE; + + bcm2711_pull_config_set(pc, pin, arg); + break; + + /* Set pull generic bindings */ + case PIN_CONFIG_BIAS_DISABLE: + bcm2711_pull_config_set(pc, pin, BCM2711_PULL_NONE); + break; + case PIN_CONFIG_BIAS_PULL_DOWN: + bcm2711_pull_config_set(pc, pin, BCM2711_PULL_DOWN); + break; + case PIN_CONFIG_BIAS_PULL_UP: + bcm2711_pull_config_set(pc, pin, BCM2711_PULL_UP); + break; + + /* Set output-high or output-low */ + case PIN_CONFIG_OUTPUT: + bcm2835_gpio_set_bit(pc, arg ? GPSET0 : GPCLR0, pin); + break; + + default: + return -ENOTSUPP; + } + } /* for each config */ + + return 0; +} + +static const struct pinconf_ops bcm2711_pinconf_ops = { + .is_generic = true, + .pin_config_get = bcm2835_pinconf_get, + .pin_config_set = bcm2711_pinconf_set, +}; + static struct pinctrl_desc bcm2835_pinctrl_desc = { .name = MODULE_NAME, .pins = bcm2835_gpio_pins, @@ -990,13 +1069,28 @@ static struct pinctrl_gpio_range bcm2835_pinctrl_gpio_range = { .npins = BCM2835_NUM_GPIOS, }; +static const struct of_device_id bcm2835_pinctrl_match[] = { + { + .compatible = "brcm,bcm2835-gpio", + .data = &bcm2835_pinconf_ops, + }, + { + .compatible = "brcm,bcm2711-gpio", + .data = &bcm2711_pinconf_ops, + }, + {} +}; + static int bcm2835_pinctrl_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; struct device_node *np = dev->of_node; struct bcm2835_pinctrl *pc; + struct gpio_irq_chip *girq; struct resource iomem; int err, i; + const struct of_device_id *match; + BUILD_BUG_ON(ARRAY_SIZE(bcm2835_gpio_pins) != BCM2835_NUM_GPIOS); BUILD_BUG_ON(ARRAY_SIZE(bcm2835_gpio_groups) != BCM2835_NUM_GPIOS); @@ -1041,36 +1135,37 @@ static int bcm2835_pinctrl_probe(struct platform_device *pdev) raw_spin_lock_init(&pc->irq_lock[i]); } + girq = &pc->gpio_chip.irq; + girq->chip = &bcm2835_gpio_irq_chip; + girq->parent_handler = bcm2835_gpio_irq_handler; + girq->num_parents = BCM2835_NUM_IRQS; + girq->parents = devm_kcalloc(dev, BCM2835_NUM_IRQS, + sizeof(*girq->parents), + GFP_KERNEL); + if (!girq->parents) + return -ENOMEM; + /* + * Use the same handler for all groups: this is necessary + * since we use one gpiochip to cover all lines - the + * irq handler then needs to figure out which group and + * bank that was firing the IRQ and look up the per-group + * and bank data. + */ + for (i = 0; i < BCM2835_NUM_IRQS; i++) + girq->parents[i] = irq_of_parse_and_map(np, i); + girq->default_type = IRQ_TYPE_NONE; + girq->handler = handle_level_irq; + err = gpiochip_add_data(&pc->gpio_chip, pc); if (err) { dev_err(dev, "could not add GPIO chip\n"); return err; } - err = gpiochip_irqchip_add(&pc->gpio_chip, &bcm2835_gpio_irq_chip, - 0, handle_level_irq, IRQ_TYPE_NONE); - if (err) { - dev_info(dev, "could not add irqchip\n"); - return err; - } - - for (i = 0; i < BCM2835_NUM_IRQS; i++) { - pc->irq[i] = irq_of_parse_and_map(np, i); - - if (pc->irq[i] == 0) - continue; - - /* - * Use the same handler for all groups: this is necessary - * since we use one gpiochip to cover all lines - the - * irq handler then needs to figure out which group and - * bank that was firing the IRQ and look up the per-group - * and bank data. - */ - gpiochip_set_chained_irqchip(&pc->gpio_chip, - &bcm2835_gpio_irq_chip, - pc->irq[i], - bcm2835_gpio_irq_handler); + match = of_match_node(bcm2835_pinctrl_match, pdev->dev.of_node); + if (match) { + bcm2835_pinctrl_desc.confops = + (const struct pinconf_ops *)match->data; } pc->pctl_dev = devm_pinctrl_register(dev, &bcm2835_pinctrl_desc, pc); @@ -1087,11 +1182,6 @@ static int bcm2835_pinctrl_probe(struct platform_device *pdev) return 0; } -static const struct of_device_id bcm2835_pinctrl_match[] = { - { .compatible = "brcm,bcm2835-gpio" }, - {} -}; - static struct platform_driver bcm2835_pinctrl_driver = { .probe = bcm2835_pinctrl_probe, .driver = { diff --git a/drivers/pinctrl/bcm/pinctrl-cygnus-mux.c b/drivers/pinctrl/bcm/pinctrl-cygnus-mux.c index 44df35942a43..dcab2204c60c 100644 --- a/drivers/pinctrl/bcm/pinctrl-cygnus-mux.c +++ b/drivers/pinctrl/bcm/pinctrl-cygnus-mux.c @@ -923,7 +923,6 @@ static int cygnus_mux_log_init(struct cygnus_pinctrl *pinctrl) if (!pinctrl->mux_log) return -ENOMEM; - log = pinctrl->mux_log; for (i = 0; i < CYGNUS_NUM_IOMUX_REGS; i++) { for (j = 0; j < CYGNUS_NUM_MUX_PER_REG; j++) { log = &pinctrl->mux_log[i * CYGNUS_NUM_MUX_PER_REG diff --git a/drivers/pinctrl/bcm/pinctrl-iproc-gpio.c b/drivers/pinctrl/bcm/pinctrl-iproc-gpio.c index b70058caee50..6f7d3a2f2e97 100644 --- a/drivers/pinctrl/bcm/pinctrl-iproc-gpio.c +++ b/drivers/pinctrl/bcm/pinctrl-iproc-gpio.c @@ -54,8 +54,12 @@ /* drive strength control for ASIU GPIO */ #define IPROC_GPIO_ASIU_DRV0_CTRL_OFFSET 0x58 -/* drive strength control for CCM/CRMU (AON) GPIO */ -#define IPROC_GPIO_DRV0_CTRL_OFFSET 0x00 +/* pinconf for CCM GPIO */ +#define IPROC_GPIO_PULL_DN_OFFSET 0x10 +#define IPROC_GPIO_PULL_UP_OFFSET 0x14 + +/* pinconf for CRMU(aon) GPIO and CCM GPIO*/ +#define IPROC_GPIO_DRV_CTRL_OFFSET 0x00 #define GPIO_BANK_SIZE 0x200 #define NGPIOS_PER_BANK 32 @@ -76,6 +80,12 @@ enum iproc_pinconf_param { IPROC_PINCON_MAX, }; +enum iproc_pinconf_ctrl_type { + IOCTRL_TYPE_AON = 1, + IOCTRL_TYPE_CDRU, + IOCTRL_TYPE_INVALID, +}; + /* * Iproc GPIO core * @@ -100,9 +110,11 @@ struct iproc_gpio { void __iomem *base; void __iomem *io_ctrl; + enum iproc_pinconf_ctrl_type io_ctrl_type; raw_spinlock_t lock; + struct irq_chip irqchip; struct gpio_chip gc; unsigned num_banks; @@ -291,14 +303,6 @@ static int iproc_gpio_irq_set_type(struct irq_data *d, unsigned int type) return 0; } -static struct irq_chip iproc_gpio_irq_chip = { - .name = "bcm-iproc-gpio", - .irq_ack = iproc_gpio_irq_ack, - .irq_mask = iproc_gpio_irq_mask, - .irq_unmask = iproc_gpio_irq_unmask, - .irq_set_type = iproc_gpio_irq_set_type, -}; - /* * Request the Iproc IOMUX pinmux controller to mux individual pins to GPIO */ @@ -355,6 +359,15 @@ static int iproc_gpio_direction_output(struct gpio_chip *gc, unsigned gpio, return 0; } +static int iproc_gpio_get_direction(struct gpio_chip *gc, unsigned int gpio) +{ + struct iproc_gpio *chip = gpiochip_get_data(gc); + unsigned int offset = IPROC_GPIO_REG(gpio, IPROC_GPIO_OUT_EN_OFFSET); + unsigned int shift = IPROC_GPIO_SHIFT(gpio); + + return !(readl(chip->base + offset) & BIT(shift)); +} + static void iproc_gpio_set(struct gpio_chip *gc, unsigned gpio, int val) { struct iproc_gpio *chip = gpiochip_get_data(gc); @@ -461,20 +474,44 @@ static const struct pinctrl_ops iproc_pctrl_ops = { static int iproc_gpio_set_pull(struct iproc_gpio *chip, unsigned gpio, bool disable, bool pull_up) { + void __iomem *base; unsigned long flags; + unsigned int shift; + u32 val_1, val_2; raw_spin_lock_irqsave(&chip->lock, flags); - - if (disable) { - iproc_set_bit(chip, IPROC_GPIO_RES_EN_OFFSET, gpio, false); + if (chip->io_ctrl_type == IOCTRL_TYPE_CDRU) { + base = chip->io_ctrl; + shift = IPROC_GPIO_SHIFT(gpio); + + val_1 = readl(base + IPROC_GPIO_PULL_UP_OFFSET); + val_2 = readl(base + IPROC_GPIO_PULL_DN_OFFSET); + if (disable) { + /* no pull-up or pull-down */ + val_1 &= ~BIT(shift); + val_2 &= ~BIT(shift); + } else if (pull_up) { + val_1 |= BIT(shift); + val_2 &= ~BIT(shift); + } else { + val_1 &= ~BIT(shift); + val_2 |= BIT(shift); + } + writel(val_1, base + IPROC_GPIO_PULL_UP_OFFSET); + writel(val_2, base + IPROC_GPIO_PULL_DN_OFFSET); } else { - iproc_set_bit(chip, IPROC_GPIO_PAD_RES_OFFSET, gpio, - pull_up); - iproc_set_bit(chip, IPROC_GPIO_RES_EN_OFFSET, gpio, true); + if (disable) { + iproc_set_bit(chip, IPROC_GPIO_RES_EN_OFFSET, gpio, + false); + } else { + iproc_set_bit(chip, IPROC_GPIO_PAD_RES_OFFSET, gpio, + pull_up); + iproc_set_bit(chip, IPROC_GPIO_RES_EN_OFFSET, gpio, + true); + } } raw_spin_unlock_irqrestore(&chip->lock, flags); - dev_dbg(chip->dev, "gpio:%u set pullup:%d\n", gpio, pull_up); return 0; @@ -483,14 +520,35 @@ static int iproc_gpio_set_pull(struct iproc_gpio *chip, unsigned gpio, static void iproc_gpio_get_pull(struct iproc_gpio *chip, unsigned gpio, bool *disable, bool *pull_up) { + void __iomem *base; unsigned long flags; + unsigned int shift; + u32 val_1, val_2; raw_spin_lock_irqsave(&chip->lock, flags); - *disable = !iproc_get_bit(chip, IPROC_GPIO_RES_EN_OFFSET, gpio); - *pull_up = iproc_get_bit(chip, IPROC_GPIO_PAD_RES_OFFSET, gpio); + if (chip->io_ctrl_type == IOCTRL_TYPE_CDRU) { + base = chip->io_ctrl; + shift = IPROC_GPIO_SHIFT(gpio); + + val_1 = readl(base + IPROC_GPIO_PULL_UP_OFFSET) & BIT(shift); + val_2 = readl(base + IPROC_GPIO_PULL_DN_OFFSET) & BIT(shift); + + *pull_up = val_1 ? true : false; + *disable = (val_1 | val_2) ? false : true; + + } else { + *disable = !iproc_get_bit(chip, IPROC_GPIO_RES_EN_OFFSET, gpio); + *pull_up = iproc_get_bit(chip, IPROC_GPIO_PAD_RES_OFFSET, gpio); + } raw_spin_unlock_irqrestore(&chip->lock, flags); } +#define DRV_STRENGTH_OFFSET(gpio, bit, type) ((type) == IOCTRL_TYPE_AON ? \ + ((2 - (bit)) * 4 + IPROC_GPIO_DRV_CTRL_OFFSET) : \ + ((type) == IOCTRL_TYPE_CDRU) ? \ + ((bit) * 4 + IPROC_GPIO_DRV_CTRL_OFFSET) : \ + ((bit) * 4 + IPROC_GPIO_REG(gpio, IPROC_GPIO_ASIU_DRV0_CTRL_OFFSET))) + static int iproc_gpio_set_strength(struct iproc_gpio *chip, unsigned gpio, unsigned strength) { @@ -505,11 +563,8 @@ static int iproc_gpio_set_strength(struct iproc_gpio *chip, unsigned gpio, if (chip->io_ctrl) { base = chip->io_ctrl; - offset = IPROC_GPIO_DRV0_CTRL_OFFSET; } else { base = chip->base; - offset = IPROC_GPIO_REG(gpio, - IPROC_GPIO_ASIU_DRV0_CTRL_OFFSET); } shift = IPROC_GPIO_SHIFT(gpio); @@ -520,11 +575,11 @@ static int iproc_gpio_set_strength(struct iproc_gpio *chip, unsigned gpio, raw_spin_lock_irqsave(&chip->lock, flags); strength = (strength / 2) - 1; for (i = 0; i < GPIO_DRV_STRENGTH_BITS; i++) { + offset = DRV_STRENGTH_OFFSET(gpio, i, chip->io_ctrl_type); val = readl(base + offset); val &= ~BIT(shift); val |= ((strength >> i) & 0x1) << shift; writel(val, base + offset); - offset += 4; } raw_spin_unlock_irqrestore(&chip->lock, flags); @@ -541,11 +596,8 @@ static int iproc_gpio_get_strength(struct iproc_gpio *chip, unsigned gpio, if (chip->io_ctrl) { base = chip->io_ctrl; - offset = IPROC_GPIO_DRV0_CTRL_OFFSET; } else { base = chip->base; - offset = IPROC_GPIO_REG(gpio, - IPROC_GPIO_ASIU_DRV0_CTRL_OFFSET); } shift = IPROC_GPIO_SHIFT(gpio); @@ -553,10 +605,10 @@ static int iproc_gpio_get_strength(struct iproc_gpio *chip, unsigned gpio, raw_spin_lock_irqsave(&chip->lock, flags); *strength = 0; for (i = 0; i < GPIO_DRV_STRENGTH_BITS; i++) { + offset = DRV_STRENGTH_OFFSET(gpio, i, chip->io_ctrl_type); val = readl(base + offset) & BIT(shift); val >>= shift; *strength += (val << i); - offset += 4; } /* convert to mA */ @@ -734,6 +786,7 @@ static int iproc_gpio_probe(struct platform_device *pdev) u32 ngpios, pinconf_disable_mask = 0; int irq, ret; bool no_pinconf = false; + enum iproc_pinconf_ctrl_type io_ctrl_type = IOCTRL_TYPE_INVALID; /* NSP does not support drive strength config */ if (of_device_is_compatible(dev->of_node, "brcm,iproc-nsp-gpio")) @@ -764,8 +817,15 @@ static int iproc_gpio_probe(struct platform_device *pdev) dev_err(dev, "unable to map I/O memory\n"); return PTR_ERR(chip->io_ctrl); } + if (of_device_is_compatible(dev->of_node, + "brcm,cygnus-ccm-gpio")) + io_ctrl_type = IOCTRL_TYPE_CDRU; + else + io_ctrl_type = IOCTRL_TYPE_AON; } + chip->io_ctrl_type = io_ctrl_type; + if (of_property_read_u32(dev->of_node, "ngpios", &ngpios)) { dev_err(&pdev->dev, "missing ngpios DT property\n"); return -ENODEV; @@ -784,12 +844,42 @@ static int iproc_gpio_probe(struct platform_device *pdev) gc->free = iproc_gpio_free; gc->direction_input = iproc_gpio_direction_input; gc->direction_output = iproc_gpio_direction_output; + gc->get_direction = iproc_gpio_get_direction; gc->set = iproc_gpio_set; gc->get = iproc_gpio_get; chip->pinmux_is_supported = of_property_read_bool(dev->of_node, "gpio-ranges"); + /* optional GPIO interrupt support */ + irq = platform_get_irq(pdev, 0); + if (irq) { + struct irq_chip *irqc; + struct gpio_irq_chip *girq; + + irqc = &chip->irqchip; + irqc->name = "bcm-iproc-gpio"; + irqc->irq_ack = iproc_gpio_irq_ack; + irqc->irq_mask = iproc_gpio_irq_mask; + irqc->irq_unmask = iproc_gpio_irq_unmask; + irqc->irq_set_type = iproc_gpio_irq_set_type; + irqc->irq_enable = iproc_gpio_irq_unmask; + irqc->irq_disable = iproc_gpio_irq_mask; + + girq = &gc->irq; + girq->chip = irqc; + girq->parent_handler = iproc_gpio_irq_handler; + girq->num_parents = 1; + girq->parents = devm_kcalloc(dev, 1, + sizeof(*girq->parents), + GFP_KERNEL); + if (!girq->parents) + return -ENOMEM; + girq->parents[0] = irq; + girq->default_type = IRQ_TYPE_NONE; + girq->handler = handle_simple_irq; + } + ret = gpiochip_add_data(gc, chip); if (ret < 0) { dev_err(dev, "unable to add GPIO chip\n"); @@ -814,20 +904,6 @@ static int iproc_gpio_probe(struct platform_device *pdev) } } - /* optional GPIO interrupt support */ - irq = platform_get_irq(pdev, 0); - if (irq) { - ret = gpiochip_irqchip_add(gc, &iproc_gpio_irq_chip, 0, - handle_simple_irq, IRQ_TYPE_NONE); - if (ret) { - dev_err(dev, "no GPIO irqchip\n"); - goto err_rm_gpiochip; - } - - gpiochip_set_chained_irqchip(gc, &iproc_gpio_irq_chip, irq, - iproc_gpio_irq_handler); - } - return 0; err_rm_gpiochip: diff --git a/drivers/pinctrl/cirrus/Kconfig b/drivers/pinctrl/cirrus/Kconfig index e546a6b75b4d..f1806fd781a0 100644 --- a/drivers/pinctrl/cirrus/Kconfig +++ b/drivers/pinctrl/cirrus/Kconfig @@ -15,6 +15,9 @@ config PINCTRL_MADERA select PINMUX select GENERIC_PINCONF +config PINCTRL_CS47L15 + bool + config PINCTRL_CS47L35 bool @@ -23,3 +26,6 @@ config PINCTRL_CS47L85 config PINCTRL_CS47L90 bool + +config PINCTRL_CS47L92 + bool diff --git a/drivers/pinctrl/cirrus/Makefile b/drivers/pinctrl/cirrus/Makefile index 0c5deb62153e..a484518c840e 100644 --- a/drivers/pinctrl/cirrus/Makefile +++ b/drivers/pinctrl/cirrus/Makefile @@ -3,6 +3,9 @@ obj-$(CONFIG_PINCTRL_LOCHNAGAR) += pinctrl-lochnagar.o pinctrl-madera-objs := pinctrl-madera-core.o +ifeq ($(CONFIG_PINCTRL_CS47L15),y) +pinctrl-madera-objs += pinctrl-cs47l15.o +endif ifeq ($(CONFIG_PINCTRL_CS47L35),y) pinctrl-madera-objs += pinctrl-cs47l35.o endif @@ -12,5 +15,8 @@ endif ifeq ($(CONFIG_PINCTRL_CS47L90),y) pinctrl-madera-objs += pinctrl-cs47l90.o endif +ifeq ($(CONFIG_PINCTRL_CS47L92),y) +pinctrl-madera-objs += pinctrl-cs47l92.o +endif obj-$(CONFIG_PINCTRL_MADERA) += pinctrl-madera.o diff --git a/drivers/pinctrl/cirrus/pinctrl-cs47l15.c b/drivers/pinctrl/cirrus/pinctrl-cs47l15.c new file mode 100644 index 000000000000..a4bfec5281d0 --- /dev/null +++ b/drivers/pinctrl/cirrus/pinctrl-cs47l15.c @@ -0,0 +1,40 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Pinctrl for Cirrus Logic CS47L15 + * + * Copyright (C) 2018-2019 Cirrus Logic, Inc. and + * Cirrus Logic International Semiconductor Ltd. + */ + +#include <linux/err.h> +#include <linux/mfd/madera/core.h> + +#include "pinctrl-madera.h" + +/* + * The alt func groups are the most commonly used functions we place these at + * the lower function indexes for convenience, and the less commonly used gpio + * functions at higher indexes. + * + * To stay consistent with the datasheet the function names are the same as + * the group names for that function's pins + * + * Note - all 1 less than in datasheet because these are zero-indexed + */ +static const unsigned int cs47l15_aif1_pins[] = { 0, 1, 2, 3 }; +static const unsigned int cs47l15_aif2_pins[] = { 4, 5, 6, 7 }; +static const unsigned int cs47l15_aif3_pins[] = { 8, 9, 10, 11 }; +static const unsigned int cs47l15_spk1_pins[] = { 12, 13, 14 }; + +static const struct madera_pin_groups cs47l15_pin_groups[] = { + { "aif1", cs47l15_aif1_pins, ARRAY_SIZE(cs47l15_aif1_pins) }, + { "aif2", cs47l15_aif2_pins, ARRAY_SIZE(cs47l15_aif2_pins) }, + { "aif3", cs47l15_aif3_pins, ARRAY_SIZE(cs47l15_aif3_pins) }, + { "pdmspk1", cs47l15_spk1_pins, ARRAY_SIZE(cs47l15_spk1_pins) }, +}; + +const struct madera_pin_chip cs47l15_pin_chip = { + .n_pins = CS47L15_NUM_GPIOS, + .pin_groups = cs47l15_pin_groups, + .n_pin_groups = ARRAY_SIZE(cs47l15_pin_groups), +}; diff --git a/drivers/pinctrl/cirrus/pinctrl-cs47l92.c b/drivers/pinctrl/cirrus/pinctrl-cs47l92.c new file mode 100644 index 000000000000..4e409734334e --- /dev/null +++ b/drivers/pinctrl/cirrus/pinctrl-cs47l92.c @@ -0,0 +1,40 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Pinctrl for Cirrus Logic CS47L92 + * + * Copyright (C) 2018-2019 Cirrus Logic, Inc. and + * Cirrus Logic International Semiconductor Ltd. + */ + +#include <linux/err.h> +#include <linux/mfd/madera/core.h> + +#include "pinctrl-madera.h" + +/* + * The alt func groups are the most commonly used functions we place these at + * the lower function indexes for convenience, and the less commonly used gpio + * functions at higher indexes. + * + * To stay consistent with the datasheet the function names are the same as + * the group names for that function's pins + * + * Note - all 1 less than in datasheet because these are zero-indexed + */ +static const unsigned int cs47l92_spk1_pins[] = { 2, 3 }; +static const unsigned int cs47l92_aif1_pins[] = { 4, 5, 6, 7 }; +static const unsigned int cs47l92_aif2_pins[] = { 8, 9, 10, 11 }; +static const unsigned int cs47l92_aif3_pins[] = { 12, 13, 14, 15 }; + +static const struct madera_pin_groups cs47l92_pin_groups[] = { + { "aif1", cs47l92_aif1_pins, ARRAY_SIZE(cs47l92_aif1_pins) }, + { "aif2", cs47l92_aif2_pins, ARRAY_SIZE(cs47l92_aif2_pins) }, + { "aif3", cs47l92_aif3_pins, ARRAY_SIZE(cs47l92_aif3_pins) }, + { "pdmspk1", cs47l92_spk1_pins, ARRAY_SIZE(cs47l92_spk1_pins) }, +}; + +const struct madera_pin_chip cs47l92_pin_chip = { + .n_pins = CS47L92_NUM_GPIOS, + .pin_groups = cs47l92_pin_groups, + .n_pin_groups = ARRAY_SIZE(cs47l92_pin_groups), +}; diff --git a/drivers/pinctrl/cirrus/pinctrl-madera-core.c b/drivers/pinctrl/cirrus/pinctrl-madera-core.c index c6b9f65f2362..e2f72dcce4c9 100644 --- a/drivers/pinctrl/cirrus/pinctrl-madera-core.c +++ b/drivers/pinctrl/cirrus/pinctrl-madera-core.c @@ -396,6 +396,16 @@ static const struct { .group_names = madera_pin_single_group_names, .func = 0x157 }, + { + .name = "aux-pdm-clk", + .group_names = madera_pin_single_group_names, + .func = 0x280 + }, + { + .name = "aux-pdm-dat", + .group_names = madera_pin_single_group_names, + .func = 0x281 + }, }; static u16 madera_pin_make_drv_str(struct madera_pin_private *priv, @@ -986,7 +996,7 @@ static struct pinctrl_desc madera_pin_desc = { static int madera_pin_probe(struct platform_device *pdev) { struct madera *madera = dev_get_drvdata(pdev->dev.parent); - const struct madera_pdata *pdata = dev_get_platdata(madera->dev); + const struct madera_pdata *pdata = &madera->pdata; struct madera_pin_private *priv; int ret; @@ -1004,6 +1014,10 @@ static int madera_pin_probe(struct platform_device *pdev) pdev->dev.of_node = madera->dev->of_node; switch (madera->type) { + case CS47L15: + if (IS_ENABLED(CONFIG_PINCTRL_CS47L15)) + priv->chip = &cs47l15_pin_chip; + break; case CS47L35: if (IS_ENABLED(CONFIG_PINCTRL_CS47L35)) priv->chip = &cs47l35_pin_chip; @@ -1018,6 +1032,12 @@ static int madera_pin_probe(struct platform_device *pdev) if (IS_ENABLED(CONFIG_PINCTRL_CS47L90)) priv->chip = &cs47l90_pin_chip; break; + case CS42L92: + case CS47L92: + case CS47L93: + if (IS_ENABLED(CONFIG_PINCTRL_CS47L92)) + priv->chip = &cs47l92_pin_chip; + break; default: break; } @@ -1037,7 +1057,7 @@ static int madera_pin_probe(struct platform_device *pdev) } /* if the configuration is provided through pdata, apply it */ - if (pdata && pdata->gpio_configs) { + if (pdata->gpio_configs) { ret = pinctrl_register_mappings(pdata->gpio_configs, pdata->n_gpio_configs); if (ret) { diff --git a/drivers/pinctrl/cirrus/pinctrl-madera.h b/drivers/pinctrl/cirrus/pinctrl-madera.h index 4ae13918316f..c16a4dc19a2a 100644 --- a/drivers/pinctrl/cirrus/pinctrl-madera.h +++ b/drivers/pinctrl/cirrus/pinctrl-madera.h @@ -30,8 +30,10 @@ struct madera_pin_private { struct pinctrl_dev *pctl; }; +extern const struct madera_pin_chip cs47l15_pin_chip; extern const struct madera_pin_chip cs47l35_pin_chip; extern const struct madera_pin_chip cs47l85_pin_chip; extern const struct madera_pin_chip cs47l90_pin_chip; +extern const struct madera_pin_chip cs47l92_pin_chip; #endif diff --git a/drivers/pinctrl/core.c b/drivers/pinctrl/core.c index b70df27874d1..2bbd8ee93507 100644 --- a/drivers/pinctrl/core.c +++ b/drivers/pinctrl/core.c @@ -736,6 +736,34 @@ int pinctrl_get_group_selector(struct pinctrl_dev *pctldev, return -EINVAL; } +bool pinctrl_gpio_can_use_line(unsigned gpio) +{ + struct pinctrl_dev *pctldev; + struct pinctrl_gpio_range *range; + bool result; + int pin; + + /* + * Try to obtain GPIO range, if it fails + * we're probably dealing with GPIO driver + * without a backing pin controller - bail out. + */ + if (pinctrl_get_device_gpio_range(gpio, &pctldev, &range)) + return true; + + mutex_lock(&pctldev->mutex); + + /* Convert to the pin controllers number space */ + pin = gpio_to_pin(range, gpio); + + result = pinmux_can_be_used_for_gpio(pctldev, pin); + + mutex_unlock(&pctldev->mutex); + + return result; +} +EXPORT_SYMBOL_GPL(pinctrl_gpio_can_use_line); + /** * pinctrl_gpio_request() - request a single pin to be used as GPIO * @gpio: the GPIO pin number from the GPIO subsystem number space diff --git a/drivers/pinctrl/devicetree.c b/drivers/pinctrl/devicetree.c index 88ddbb2e30de..5d6d8b1e9062 100644 --- a/drivers/pinctrl/devicetree.c +++ b/drivers/pinctrl/devicetree.c @@ -228,10 +228,8 @@ int pinctrl_dt_to_map(struct pinctrl *p, struct pinctrl_dev *pctldev) * than dynamically allocate it and have to free it later, * just point part way into the property name for the string. */ - if (ret < 0) { - /* strlen("pinctrl-") == 8 */ - statename = prop->name + 8; - } + if (ret < 0) + statename = prop->name + strlen("pinctrl-"); /* For every referenced pin configuration node in it */ for (config = 0; config < size; config++) { diff --git a/drivers/pinctrl/freescale/pinctrl-imx.c b/drivers/pinctrl/freescale/pinctrl-imx.c index 83ff9532bae6..9f42036c5fbb 100644 --- a/drivers/pinctrl/freescale/pinctrl-imx.c +++ b/drivers/pinctrl/freescale/pinctrl-imx.c @@ -672,8 +672,10 @@ static int imx_pinctrl_parse_functions(struct device_node *np, grp = devm_kzalloc(ipctl->dev, sizeof(struct group_desc), GFP_KERNEL); - if (!grp) + if (!grp) { + of_node_put(child); return -ENOMEM; + } mutex_lock(&ipctl->mutex); radix_tree_insert(&pctl->pin_group_tree, @@ -697,12 +699,17 @@ static bool imx_pinctrl_dt_is_flat_functions(struct device_node *np) struct device_node *pinctrl_np; for_each_child_of_node(np, function_np) { - if (of_property_read_bool(function_np, "fsl,pins")) + if (of_property_read_bool(function_np, "fsl,pins")) { + of_node_put(function_np); return true; + } for_each_child_of_node(function_np, pinctrl_np) { - if (of_property_read_bool(pinctrl_np, "fsl,pins")) + if (of_property_read_bool(pinctrl_np, "fsl,pins")) { + of_node_put(pinctrl_np); + of_node_put(function_np); return false; + } } } diff --git a/drivers/pinctrl/freescale/pinctrl-mxs.c b/drivers/pinctrl/freescale/pinctrl-mxs.c index 641b3088876f..735cedd0958a 100644 --- a/drivers/pinctrl/freescale/pinctrl-mxs.c +++ b/drivers/pinctrl/freescale/pinctrl-mxs.c @@ -488,8 +488,10 @@ static int mxs_pinctrl_probe_dt(struct platform_device *pdev, if (of_property_read_u32(child, "reg", &val)) { ret = mxs_pinctrl_parse_group(pdev, child, idxg++, NULL); - if (ret) + if (ret) { + of_node_put(child); return ret; + } continue; } @@ -499,15 +501,19 @@ static int mxs_pinctrl_probe_dt(struct platform_device *pdev, f->ngroups, sizeof(*f->groups), GFP_KERNEL); - if (!f->groups) + if (!f->groups) { + of_node_put(child); return -ENOMEM; + } fn = child->name; i = 0; } ret = mxs_pinctrl_parse_group(pdev, child, idxg++, &f->groups[i++]); - if (ret) + if (ret) { + of_node_put(child); return ret; + } } return 0; diff --git a/drivers/pinctrl/intel/pinctrl-baytrail.c b/drivers/pinctrl/intel/pinctrl-baytrail.c index 297b7b5fcb28..9ffb22211d2b 100644 --- a/drivers/pinctrl/intel/pinctrl-baytrail.c +++ b/drivers/pinctrl/intel/pinctrl-baytrail.c @@ -98,13 +98,6 @@ struct byt_gpio_pin_context { u32 val; }; -struct byt_community { - unsigned int pin_base; - size_t npins; - const unsigned int *pad_map; - void __iomem *reg_base; -}; - #define COMMUNITY(p, n, map) \ { \ .pin_base = (p), \ @@ -112,26 +105,14 @@ struct byt_community { .pad_map = (map),\ } -struct byt_pinctrl_soc_data { - const char *uid; - const struct pinctrl_pin_desc *pins; - size_t npins; - const struct intel_pingroup *groups; - size_t ngroups; - const struct intel_function *functions; - size_t nfunctions; - const struct byt_community *communities; - size_t ncommunities; -}; - struct byt_gpio { struct gpio_chip chip; struct platform_device *pdev; struct pinctrl_dev *pctl_dev; struct pinctrl_desc pctl_desc; raw_spinlock_t lock; - const struct byt_pinctrl_soc_data *soc_data; - struct byt_community *communities_copy; + const struct intel_pinctrl_soc_data *soc_data; + struct intel_community *communities_copy; struct byt_gpio_pin_context *saved_context; }; @@ -383,11 +364,11 @@ static const struct intel_function byt_score_functions[] = { FUNCTION("gpio", byt_score_gpio_groups), }; -static const struct byt_community byt_score_communities[] = { +static const struct intel_community byt_score_communities[] = { COMMUNITY(0, BYT_NGPIO_SCORE, byt_score_pins_map), }; -static const struct byt_pinctrl_soc_data byt_score_soc_data = { +static const struct intel_pinctrl_soc_data byt_score_soc_data = { .uid = BYT_SCORE_ACPI_UID, .pins = byt_score_pins, .npins = ARRAY_SIZE(byt_score_pins), @@ -496,11 +477,11 @@ static const struct intel_function byt_sus_functions[] = { FUNCTION("gpio", byt_sus_gpio_groups), }; -static const struct byt_community byt_sus_communities[] = { +static const struct intel_community byt_sus_communities[] = { COMMUNITY(0, BYT_NGPIO_SUS, byt_sus_pins_map), }; -static const struct byt_pinctrl_soc_data byt_sus_soc_data = { +static const struct intel_pinctrl_soc_data byt_sus_soc_data = { .uid = BYT_SUS_ACPI_UID, .pins = byt_sus_pins, .npins = ARRAY_SIZE(byt_sus_pins), @@ -549,11 +530,11 @@ static const unsigned int byt_ncore_pins_map[BYT_NGPIO_NCORE] = { 3, 6, 10, 13, 2, 5, 9, 7, }; -static const struct byt_community byt_ncore_communities[] = { +static const struct intel_community byt_ncore_communities[] = { COMMUNITY(0, BYT_NGPIO_NCORE, byt_ncore_pins_map), }; -static const struct byt_pinctrl_soc_data byt_ncore_soc_data = { +static const struct intel_pinctrl_soc_data byt_ncore_soc_data = { .uid = BYT_NCORE_ACPI_UID, .pins = byt_ncore_pins, .npins = ARRAY_SIZE(byt_ncore_pins), @@ -561,17 +542,17 @@ static const struct byt_pinctrl_soc_data byt_ncore_soc_data = { .ncommunities = ARRAY_SIZE(byt_ncore_communities), }; -static const struct byt_pinctrl_soc_data *byt_soc_data[] = { +static const struct intel_pinctrl_soc_data *byt_soc_data[] = { &byt_score_soc_data, &byt_sus_soc_data, &byt_ncore_soc_data, NULL }; -static struct byt_community *byt_get_community(struct byt_gpio *vg, - unsigned int pin) +static struct intel_community *byt_get_community(struct byt_gpio *vg, + unsigned int pin) { - struct byt_community *comm; + struct intel_community *comm; int i; for (i = 0; i < vg->soc_data->ncommunities; i++) { @@ -586,7 +567,7 @@ static struct byt_community *byt_get_community(struct byt_gpio *vg, static void __iomem *byt_gpio_reg(struct byt_gpio *vg, unsigned int offset, int reg) { - struct byt_community *comm = byt_get_community(vg, offset); + struct intel_community *comm = byt_get_community(vg, offset); u32 reg_offset; if (!comm) @@ -605,7 +586,7 @@ static void __iomem *byt_gpio_reg(struct byt_gpio *vg, unsigned int offset, break; } - return comm->reg_base + reg_offset + reg; + return comm->pad_regs + reg_offset + reg; } static int byt_get_groups_count(struct pinctrl_dev *pctldev) @@ -1211,7 +1192,7 @@ static void byt_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip) u32 conf0, val; for (i = 0; i < vg->soc_data->npins; i++) { - const struct byt_community *comm; + const struct intel_community *comm; const char *pull_str = NULL; const char *pull = NULL; void __iomem *reg; @@ -1580,7 +1561,7 @@ static int byt_gpio_probe(struct byt_gpio *vg) } static int byt_set_soc_data(struct byt_gpio *vg, - const struct byt_pinctrl_soc_data *soc_data) + const struct intel_pinctrl_soc_data *soc_data) { int i; @@ -1593,15 +1574,13 @@ static int byt_set_soc_data(struct byt_gpio *vg, return -ENOMEM; for (i = 0; i < soc_data->ncommunities; i++) { - struct byt_community *comm = vg->communities_copy + i; - struct resource *mem_rc; + struct intel_community *comm = vg->communities_copy + i; *comm = vg->soc_data->communities[i]; - mem_rc = platform_get_resource(vg->pdev, IORESOURCE_MEM, 0); - comm->reg_base = devm_ioremap_resource(&vg->pdev->dev, mem_rc); - if (IS_ERR(comm->reg_base)) - return PTR_ERR(comm->reg_base); + comm->pad_regs = devm_platform_ioremap_resource(vg->pdev, 0); + if (IS_ERR(comm->pad_regs)) + return PTR_ERR(comm->pad_regs); } return 0; @@ -1615,8 +1594,8 @@ static const struct acpi_device_id byt_gpio_acpi_match[] = { static int byt_pinctrl_probe(struct platform_device *pdev) { - const struct byt_pinctrl_soc_data *soc_data = NULL; - const struct byt_pinctrl_soc_data **soc_table; + const struct intel_pinctrl_soc_data *soc_data = NULL; + const struct intel_pinctrl_soc_data **soc_table; struct acpi_device *acpi_dev; struct byt_gpio *vg; int i, ret; @@ -1625,7 +1604,7 @@ static int byt_pinctrl_probe(struct platform_device *pdev) if (!acpi_dev) return -ENODEV; - soc_table = (const struct byt_pinctrl_soc_data **)device_get_match_data(&pdev->dev); + soc_table = (const struct intel_pinctrl_soc_data **)device_get_match_data(&pdev->dev); for (i = 0; soc_table[i]; i++) { if (!strcmp(acpi_dev->pnp.unique_id, soc_table[i]->uid)) { diff --git a/drivers/pinctrl/intel/pinctrl-broxton.c b/drivers/pinctrl/intel/pinctrl-broxton.c index e2d4505d6747..2be7e414f803 100644 --- a/drivers/pinctrl/intel/pinctrl-broxton.c +++ b/drivers/pinctrl/intel/pinctrl-broxton.c @@ -15,8 +15,9 @@ #include "pinctrl-intel.h" #define BXT_PAD_OWN 0x020 -#define BXT_HOSTSW_OWN 0x080 #define BXT_PADCFGLOCK 0x060 +#define BXT_HOSTSW_OWN 0x080 +#define BXT_GPI_IS 0x100 #define BXT_GPI_IE 0x110 #define BXT_COMMUNITY(s, e) \ @@ -24,6 +25,7 @@ .padown_offset = BXT_PAD_OWN, \ .padcfglock_offset = BXT_PADCFGLOCK, \ .hostown_offset = BXT_HOSTSW_OWN, \ + .is_offset = BXT_GPI_IS, \ .ie_offset = BXT_GPI_IE, \ .gpp_size = 32, \ .pin_base = (s), \ diff --git a/drivers/pinctrl/intel/pinctrl-cannonlake.c b/drivers/pinctrl/intel/pinctrl-cannonlake.c index 08024b065033..f51b27bbf9f1 100644 --- a/drivers/pinctrl/intel/pinctrl-cannonlake.c +++ b/drivers/pinctrl/intel/pinctrl-cannonlake.c @@ -19,6 +19,7 @@ #define CNL_PADCFGLOCK 0x080 #define CNL_LP_HOSTSW_OWN 0x0b0 #define CNL_H_HOSTSW_OWN 0x0c0 +#define CNL_GPI_IS 0x100 #define CNL_GPI_IE 0x120 #define CNL_GPP(r, s, e, g) \ @@ -37,6 +38,7 @@ .padown_offset = CNL_PAD_OWN, \ .padcfglock_offset = CNL_PADCFGLOCK, \ .hostown_offset = (o), \ + .is_offset = CNL_GPI_IS, \ .ie_offset = CNL_GPI_IE, \ .pin_base = (s), \ .npins = ((e) - (s) + 1), \ diff --git a/drivers/pinctrl/intel/pinctrl-cherryview.c b/drivers/pinctrl/intel/pinctrl-cherryview.c index ab681d1a3a74..aae51c507f59 100644 --- a/drivers/pinctrl/intel/pinctrl-cherryview.c +++ b/drivers/pinctrl/intel/pinctrl-cherryview.c @@ -1677,7 +1677,6 @@ static int chv_pinctrl_probe(struct platform_device *pdev) { struct chv_pinctrl *pctrl; struct acpi_device *adev; - struct resource *res; acpi_status status; int ret, irq, i; @@ -1707,16 +1706,13 @@ static int chv_pinctrl_probe(struct platform_device *pdev) return -ENOMEM; #endif - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - pctrl->regs = devm_ioremap_resource(&pdev->dev, res); + pctrl->regs = devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(pctrl->regs)) return PTR_ERR(pctrl->regs); irq = platform_get_irq(pdev, 0); - if (irq < 0) { - dev_err(&pdev->dev, "failed to get interrupt number\n"); + if (irq < 0) return irq; - } pctrl->pctldesc = chv_pinctrl_desc; pctrl->pctldesc.name = dev_name(&pdev->dev); diff --git a/drivers/pinctrl/intel/pinctrl-denverton.c b/drivers/pinctrl/intel/pinctrl-denverton.c index 3a4932b557b4..f26d030b9b41 100644 --- a/drivers/pinctrl/intel/pinctrl-denverton.c +++ b/drivers/pinctrl/intel/pinctrl-denverton.c @@ -15,8 +15,9 @@ #include "pinctrl-intel.h" #define DNV_PAD_OWN 0x020 -#define DNV_HOSTSW_OWN 0x0C0 #define DNV_PADCFGLOCK 0x090 +#define DNV_HOSTSW_OWN 0x0C0 +#define DNV_GPI_IS 0x100 #define DNV_GPI_IE 0x120 #define DNV_GPP(n, s, e) \ @@ -32,6 +33,7 @@ .padown_offset = DNV_PAD_OWN, \ .padcfglock_offset = DNV_PADCFGLOCK, \ .hostown_offset = DNV_HOSTSW_OWN, \ + .is_offset = DNV_GPI_IS, \ .ie_offset = DNV_GPI_IE, \ .pin_base = (s), \ .npins = ((e) - (s) + 1), \ @@ -39,6 +41,7 @@ .ngpps = ARRAY_SIZE(g), \ } +/* Denverton */ static const struct pinctrl_pin_desc dnv_pins[] = { /* North ALL */ PINCTRL_PIN(0, "GBE0_SDP0"), @@ -59,7 +62,7 @@ static const struct pinctrl_pin_desc dnv_pins[] = { PINCTRL_PIN(15, "NCSI_CLK_IN"), PINCTRL_PIN(16, "NCSI_RXD1"), PINCTRL_PIN(17, "NCSI_CRS_DV"), - PINCTRL_PIN(18, "NCSI_ARB_IN"), + PINCTRL_PIN(18, "IDSLDO_VID_TICKLE"), PINCTRL_PIN(19, "NCSI_TX_EN"), PINCTRL_PIN(20, "NCSI_TXD0"), PINCTRL_PIN(21, "NCSI_TXD1"), @@ -68,14 +71,14 @@ static const struct pinctrl_pin_desc dnv_pins[] = { PINCTRL_PIN(24, "GBE0_LED1"), PINCTRL_PIN(25, "GBE1_LED0"), PINCTRL_PIN(26, "GBE1_LED1"), - PINCTRL_PIN(27, "GPIO_0"), + PINCTRL_PIN(27, "SPARE_0"), PINCTRL_PIN(28, "PCIE_CLKREQ0_N"), PINCTRL_PIN(29, "PCIE_CLKREQ1_N"), PINCTRL_PIN(30, "PCIE_CLKREQ2_N"), PINCTRL_PIN(31, "PCIE_CLKREQ3_N"), PINCTRL_PIN(32, "PCIE_CLKREQ4_N"), - PINCTRL_PIN(33, "GPIO_1"), - PINCTRL_PIN(34, "GPIO_2"), + PINCTRL_PIN(33, "GBE_MDC"), + PINCTRL_PIN(34, "GBE_MDIO"), PINCTRL_PIN(35, "SVID_ALERT_N"), PINCTRL_PIN(36, "SVID_DATA"), PINCTRL_PIN(37, "SVID_CLK"), @@ -102,15 +105,15 @@ static const struct pinctrl_pin_desc dnv_pins[] = { PINCTRL_PIN(57, "DFX_PORT14"), PINCTRL_PIN(58, "DFX_PORT15"), /* South GPP0 */ - PINCTRL_PIN(59, "GPIO_12"), - PINCTRL_PIN(60, "SMB5_GBE_ALRT_N"), + PINCTRL_PIN(59, "SPI_TPM_CS_N"), + PINCTRL_PIN(60, "UART2_CTS"), PINCTRL_PIN(61, "PCIE_CLKREQ5_N"), PINCTRL_PIN(62, "PCIE_CLKREQ6_N"), PINCTRL_PIN(63, "PCIE_CLKREQ7_N"), PINCTRL_PIN(64, "UART0_RXD"), PINCTRL_PIN(65, "UART0_TXD"), - PINCTRL_PIN(66, "SMB5_GBE_CLK"), - PINCTRL_PIN(67, "SMB5_GBE_DATA"), + PINCTRL_PIN(66, "CPU_RESET_N"), + PINCTRL_PIN(67, "NMI"), PINCTRL_PIN(68, "ERROR2_N"), PINCTRL_PIN(69, "ERROR1_N"), PINCTRL_PIN(70, "ERROR0_N"), @@ -129,20 +132,20 @@ static const struct pinctrl_pin_desc dnv_pins[] = { PINCTRL_PIN(83, "USB_OC0_N"), PINCTRL_PIN(84, "FLEX_CLK_SE0"), PINCTRL_PIN(85, "FLEX_CLK_SE1"), - PINCTRL_PIN(86, "GPIO_4"), - PINCTRL_PIN(87, "GPIO_5"), - PINCTRL_PIN(88, "GPIO_6"), - PINCTRL_PIN(89, "GPIO_7"), + PINCTRL_PIN(86, "SPARE_4"), + PINCTRL_PIN(87, "SMB3_IE0_CLK"), + PINCTRL_PIN(88, "SMB3_IE0_DATA"), + PINCTRL_PIN(89, "SMB3_IE0_ALRT_N"), PINCTRL_PIN(90, "SATA0_LED_N"), PINCTRL_PIN(91, "SATA1_LED_N"), PINCTRL_PIN(92, "SATA_PDETECT0"), PINCTRL_PIN(93, "SATA_PDETECT1"), - PINCTRL_PIN(94, "SATA0_SDOUT"), - PINCTRL_PIN(95, "SATA1_SDOUT"), + PINCTRL_PIN(94, "UART1_RTS"), + PINCTRL_PIN(95, "UART1_CTS"), PINCTRL_PIN(96, "UART1_RXD"), PINCTRL_PIN(97, "UART1_TXD"), - PINCTRL_PIN(98, "GPIO_8"), - PINCTRL_PIN(99, "GPIO_9"), + PINCTRL_PIN(98, "SPARE_8"), + PINCTRL_PIN(99, "SPARE_9"), PINCTRL_PIN(100, "TCK"), PINCTRL_PIN(101, "TRST_N"), PINCTRL_PIN(102, "TMS"), @@ -150,11 +153,11 @@ static const struct pinctrl_pin_desc dnv_pins[] = { PINCTRL_PIN(104, "TDO"), PINCTRL_PIN(105, "CX_PRDY_N"), PINCTRL_PIN(106, "CX_PREQ_N"), - PINCTRL_PIN(107, "CTBTRIGINOUT"), - PINCTRL_PIN(108, "CTBTRIGOUT"), - PINCTRL_PIN(109, "DFX_SPARE2"), - PINCTRL_PIN(110, "DFX_SPARE3"), - PINCTRL_PIN(111, "DFX_SPARE4"), + PINCTRL_PIN(107, "TAP1_TCK"), + PINCTRL_PIN(108, "TAP1_TRST_N"), + PINCTRL_PIN(109, "TAP1_TMS"), + PINCTRL_PIN(110, "TAP1_TDI"), + PINCTRL_PIN(111, "TAP1_TDO"), /* South GPP1 */ PINCTRL_PIN(112, "SUSPWRDNACK"), PINCTRL_PIN(113, "PMU_SUSCLK"), @@ -183,8 +186,8 @@ static const struct pinctrl_pin_desc dnv_pins[] = { PINCTRL_PIN(136, "ESPI_CLK"), PINCTRL_PIN(137, "ESPI_RST_N"), PINCTRL_PIN(138, "ESPI_ALRT0_N"), - PINCTRL_PIN(139, "GPIO_10"), - PINCTRL_PIN(140, "GPIO_11"), + PINCTRL_PIN(139, "ESPI_CS1_N"), + PINCTRL_PIN(140, "ESPI_ALRT1_N"), PINCTRL_PIN(141, "ESPI_CLK_LOOPBK"), PINCTRL_PIN(142, "EMMC_CMD"), PINCTRL_PIN(143, "EMMC_STROBE"), @@ -197,7 +200,7 @@ static const struct pinctrl_pin_desc dnv_pins[] = { PINCTRL_PIN(150, "EMMC_D5"), PINCTRL_PIN(151, "EMMC_D6"), PINCTRL_PIN(152, "EMMC_D7"), - PINCTRL_PIN(153, "GPIO_3"), + PINCTRL_PIN(153, "SPARE_3"), }; static const unsigned int dnv_uart0_pins[] = { 60, 61, 64, 65 }; diff --git a/drivers/pinctrl/intel/pinctrl-geminilake.c b/drivers/pinctrl/intel/pinctrl-geminilake.c index 331b8fd54d88..df02028b40f3 100644 --- a/drivers/pinctrl/intel/pinctrl-geminilake.c +++ b/drivers/pinctrl/intel/pinctrl-geminilake.c @@ -17,6 +17,7 @@ #define GLK_PAD_OWN 0x020 #define GLK_PADCFGLOCK 0x080 #define GLK_HOSTSW_OWN 0x0b0 +#define GLK_GPI_IS 0x100 #define GLK_GPI_IE 0x110 #define GLK_COMMUNITY(s, e) \ @@ -24,6 +25,7 @@ .padown_offset = GLK_PAD_OWN, \ .padcfglock_offset = GLK_PADCFGLOCK, \ .hostown_offset = GLK_HOSTSW_OWN, \ + .is_offset = GLK_GPI_IS, \ .ie_offset = GLK_GPI_IE, \ .gpp_size = 32, \ .pin_base = (s), \ diff --git a/drivers/pinctrl/intel/pinctrl-icelake.c b/drivers/pinctrl/intel/pinctrl-icelake.c index 5f2f5c61ad41..6489e9bbb61f 100644 --- a/drivers/pinctrl/intel/pinctrl-icelake.c +++ b/drivers/pinctrl/intel/pinctrl-icelake.c @@ -18,6 +18,7 @@ #define ICL_PAD_OWN 0x020 #define ICL_PADCFGLOCK 0x080 #define ICL_HOSTSW_OWN 0x0b0 +#define ICL_GPI_IS 0x100 #define ICL_GPI_IE 0x110 #define ICL_GPP(r, s, e, g) \ @@ -36,6 +37,7 @@ .padown_offset = ICL_PAD_OWN, \ .padcfglock_offset = ICL_PADCFGLOCK, \ .hostown_offset = ICL_HOSTSW_OWN, \ + .is_offset = ICL_GPI_IS, \ .ie_offset = ICL_GPI_IE, \ .pin_base = (s), \ .npins = ((e) - (s) + 1), \ diff --git a/drivers/pinctrl/intel/pinctrl-intel.c b/drivers/pinctrl/intel/pinctrl-intel.c index a18d6eefe672..1f13bcd0e4e1 100644 --- a/drivers/pinctrl/intel/pinctrl-intel.c +++ b/drivers/pinctrl/intel/pinctrl-intel.c @@ -8,12 +8,13 @@ */ #include <linux/acpi.h> -#include <linux/module.h> #include <linux/interrupt.h> #include <linux/gpio/driver.h> #include <linux/log2.h> +#include <linux/module.h> #include <linux/platform_device.h> #include <linux/property.h> +#include <linux/time.h> #include <linux/pinctrl/pinctrl.h> #include <linux/pinctrl/pinmux.h> @@ -29,7 +30,6 @@ #define REVID_MASK GENMASK(31, 16) #define PADBAR 0x00c -#define GPI_IS 0x100 #define PADOWN_BITS 4 #define PADOWN_SHIFT(p) ((p) % 8 * PADOWN_BITS) @@ -71,7 +71,7 @@ #define PADCFG2_DEBOUNCE_SHIFT 1 #define PADCFG2_DEBOUNCE_MASK GENMASK(4, 1) -#define DEBOUNCE_PERIOD 31250 /* ns */ +#define DEBOUNCE_PERIOD_NSEC 31250 struct intel_pad_context { u32 padcfg0; @@ -165,7 +165,7 @@ static void __iomem *intel_get_padcfg(struct intel_pinctrl *pctrl, padno = pin_to_padno(community, pin); nregs = (community->features & PINCTRL_FEATURE_DEBOUNCE) ? 4 : 2; - if (reg == PADCFG2 && !(community->features & PINCTRL_FEATURE_DEBOUNCE)) + if (reg >= nregs * 4) return NULL; return community->pad_regs + reg + padno * nregs * 4; @@ -220,47 +220,71 @@ static bool intel_pad_acpi_mode(struct intel_pinctrl *pctrl, unsigned int pin) return !(readl(hostown) & BIT(gpp_offset)); } -static bool intel_pad_locked(struct intel_pinctrl *pctrl, unsigned int pin) +/** + * enum - Locking variants of the pad configuration + * + * @PAD_UNLOCKED: pad is fully controlled by the configuration registers + * @PAD_LOCKED: pad configuration registers, except TX state, are locked + * @PAD_LOCKED_TX: pad configuration TX state is locked + * @PAD_LOCKED_FULL: pad configuration registers are locked completely + * + * Locking is considered as read-only mode for corresponding registers and + * their respective fields. That said, TX state bit is locked separately from + * the main locking scheme. + */ +enum { + PAD_UNLOCKED = 0, + PAD_LOCKED = 1, + PAD_LOCKED_TX = 2, + PAD_LOCKED_FULL = PAD_LOCKED | PAD_LOCKED_TX, +}; + +static int intel_pad_locked(struct intel_pinctrl *pctrl, unsigned int pin) { struct intel_community *community; const struct intel_padgroup *padgrp; unsigned int offset, gpp_offset; u32 value; + int ret = PAD_UNLOCKED; community = intel_get_community(pctrl, pin); if (!community) - return true; + return PAD_LOCKED_FULL; if (!community->padcfglock_offset) - return false; + return PAD_UNLOCKED; padgrp = intel_community_get_padgroup(community, pin); if (!padgrp) - return true; + return PAD_LOCKED_FULL; gpp_offset = padgroup_offset(padgrp, pin); /* * If PADCFGLOCK and PADCFGLOCKTX bits are both clear for this pad, * the pad is considered unlocked. Any other case means that it is - * either fully or partially locked and we don't touch it. + * either fully or partially locked. */ - offset = community->padcfglock_offset + padgrp->reg_num * 8; + offset = community->padcfglock_offset + 0 + padgrp->reg_num * 8; value = readl(community->regs + offset); if (value & BIT(gpp_offset)) - return true; + ret |= PAD_LOCKED; offset = community->padcfglock_offset + 4 + padgrp->reg_num * 8; value = readl(community->regs + offset); if (value & BIT(gpp_offset)) - return true; + ret |= PAD_LOCKED_TX; - return false; + return ret; +} + +static bool intel_pad_is_unlocked(struct intel_pinctrl *pctrl, unsigned int pin) +{ + return (intel_pad_locked(pctrl, pin) & PAD_LOCKED) == PAD_UNLOCKED; } static bool intel_pad_usable(struct intel_pinctrl *pctrl, unsigned int pin) { - return intel_pad_owned_by_host(pctrl, pin) && - !intel_pad_locked(pctrl, pin); + return intel_pad_owned_by_host(pctrl, pin) && intel_pad_is_unlocked(pctrl, pin); } static int intel_get_groups_count(struct pinctrl_dev *pctldev) @@ -294,7 +318,8 @@ static void intel_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s, struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); void __iomem *padcfg; u32 cfg0, cfg1, mode; - bool locked, acpi; + int locked; + bool acpi; if (!intel_pad_owned_by_host(pctrl, pin)) { seq_puts(s, "not available"); @@ -322,11 +347,16 @@ static void intel_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s, if (locked || acpi) { seq_puts(s, " ["); - if (locked) { + if (locked) seq_puts(s, "LOCKED"); - if (acpi) - seq_puts(s, ", "); - } + if ((locked & PAD_LOCKED_FULL) == PAD_LOCKED_TX) + seq_puts(s, " tx"); + else if ((locked & PAD_LOCKED_FULL) == PAD_LOCKED_FULL) + seq_puts(s, " full"); + + if (locked && acpi) + seq_puts(s, ", "); + if (acpi) seq_puts(s, "ACPI"); seq_puts(s, "]"); @@ -448,11 +478,16 @@ static int intel_gpio_request_enable(struct pinctrl_dev *pctldev, raw_spin_lock_irqsave(&pctrl->lock, flags); - if (!intel_pad_usable(pctrl, pin)) { + if (!intel_pad_owned_by_host(pctrl, pin)) { raw_spin_unlock_irqrestore(&pctrl->lock, flags); return -EBUSY; } + if (!intel_pad_is_unlocked(pctrl, pin)) { + raw_spin_unlock_irqrestore(&pctrl->lock, flags); + return 0; + } + padcfg0 = intel_get_padcfg(pctrl, pin, PADCFG0); intel_gpio_set_gpio_mode(padcfg0); /* Disable TX buffer and enable RX (this will be input) */ @@ -566,7 +601,7 @@ static int intel_config_get(struct pinctrl_dev *pctldev, unsigned int pin, return -EINVAL; v = (v & PADCFG2_DEBOUNCE_MASK) >> PADCFG2_DEBOUNCE_SHIFT; - arg = BIT(v) * DEBOUNCE_PERIOD / 1000; + arg = BIT(v) * DEBOUNCE_PERIOD_NSEC / NSEC_PER_USEC; break; } @@ -683,7 +718,7 @@ static int intel_config_set_debounce(struct intel_pinctrl *pctrl, if (debounce) { unsigned long v; - v = order_base_2(debounce * 1000 / DEBOUNCE_PERIOD); + v = order_base_2(debounce * NSEC_PER_USEC / DEBOUNCE_PERIOD_NSEC); if (v < 3 || v > 15) { ret = -EINVAL; goto exit_unlock; @@ -796,6 +831,29 @@ static int intel_gpio_to_pin(struct intel_pinctrl *pctrl, unsigned int offset, return -EINVAL; } +/** + * intel_pin_to_gpio() - Translate from pin number to GPIO offset + * @pctrl: Pinctrl structure + * @pin: pin number + * + * Translate the pin number of pinctrl to GPIO offset + */ +static __maybe_unused int intel_pin_to_gpio(struct intel_pinctrl *pctrl, int pin) +{ + const struct intel_community *community; + const struct intel_padgroup *padgrp; + + community = intel_get_community(pctrl, pin); + if (!community) + return -EINVAL; + + padgrp = intel_community_get_padgroup(community, pin); + if (!padgrp) + return -EINVAL; + + return pin - padgrp->base + padgrp->gpio_base; +} + static int intel_gpio_get(struct gpio_chip *chip, unsigned int offset) { struct intel_pinctrl *pctrl = gpiochip_get_data(chip); @@ -1313,15 +1371,12 @@ static int intel_pinctrl_probe(struct platform_device *pdev, for (i = 0; i < pctrl->ncommunities; i++) { struct intel_community *community = &pctrl->communities[i]; - struct resource *res; void __iomem *regs; u32 padbar; *community = pctrl->soc->communities[i]; - res = platform_get_resource(pdev, IORESOURCE_MEM, - community->barno); - regs = devm_ioremap_resource(&pdev->dev, res); + regs = devm_platform_ioremap_resource(pdev, community->barno); if (IS_ERR(regs)) return PTR_ERR(regs); @@ -1345,19 +1400,14 @@ static int intel_pinctrl_probe(struct platform_device *pdev, community->regs = regs; community->pad_regs = regs + padbar; - if (!community->is_offset) - community->is_offset = GPI_IS; - ret = intel_pinctrl_add_padgroups(pctrl, community); if (ret) return ret; } irq = platform_get_irq(pdev, 0); - if (irq < 0) { - dev_err(&pdev->dev, "failed to get interrupt number\n"); + if (irq < 0) return irq; - } ret = intel_pinctrl_pm_init(pctrl); if (ret) @@ -1421,8 +1471,6 @@ int intel_pinctrl_probe_by_uid(struct platform_device *pdev) table = (const struct intel_pinctrl_soc_data **)id->driver_data; data = table[pdev->id]; } - if (!data) - return -ENODEV; return intel_pinctrl_probe(pdev, data); } @@ -1443,7 +1491,7 @@ static bool intel_pinctrl_should_save(struct intel_pinctrl *pctrl, unsigned int * them alone. */ if (pd->mux_owner || pd->gpio_owner || - gpiochip_line_is_irq(&pctrl->chip, pin)) + gpiochip_line_is_irq(&pctrl->chip, intel_pin_to_gpio(pctrl, pin))) return true; return false; diff --git a/drivers/pinctrl/intel/pinctrl-intel.h b/drivers/pinctrl/intel/pinctrl-intel.h index a8e958f1dcf5..34b38a321760 100644 --- a/drivers/pinctrl/intel/pinctrl-intel.h +++ b/drivers/pinctrl/intel/pinctrl-intel.h @@ -75,9 +75,9 @@ struct intel_padgroup { * @hostown_offset: Register offset of HOSTSW_OWN from @regs. If %0 then it * is assumed that the host owns the pin (rather than * ACPI). - * @is_offset: Register offset of GPI_IS from @regs. If %0 then uses the - * default (%0x100). + * @is_offset: Register offset of GPI_IS from @regs. * @ie_offset: Register offset of GPI_IE from @regs. + * @features: Additional features supported by the hardware * @pin_base: Starting pin of pins in this community * @gpp_size: Maximum number of pads in each group, such as PADCFGLOCK, * HOSTSW_OWN, GPI_IS, GPI_IE, etc. Used when @gpps is %NULL. @@ -85,9 +85,9 @@ struct intel_padgroup { * minimum. Use %0 if the number of registers can be * determined by the size of the group. * @npins: Number of pins in this community - * @features: Additional features supported by the hardware * @gpps: Pad groups if the controller has variable size pad groups * @ngpps: Number of pad groups in this community + * @pad_map: Optional non-linear mapping of the pads * @regs: Community specific common registers (reserved for core driver) * @pad_regs: Community specific pad registers (reserved for core driver) * @@ -104,13 +104,14 @@ struct intel_community { unsigned int hostown_offset; unsigned int is_offset; unsigned int ie_offset; + unsigned int features; unsigned int pin_base; unsigned int gpp_size; unsigned int gpp_num_padown_regs; size_t npins; - unsigned int features; const struct intel_padgroup *gpps; size_t ngpps; + const unsigned int *pad_map; /* Reserved for the core driver */ void __iomem *regs; void __iomem *pad_regs; diff --git a/drivers/pinctrl/intel/pinctrl-lewisburg.c b/drivers/pinctrl/intel/pinctrl-lewisburg.c index 03b04c7ae9e8..2e06fb1464ab 100644 --- a/drivers/pinctrl/intel/pinctrl-lewisburg.c +++ b/drivers/pinctrl/intel/pinctrl-lewisburg.c @@ -17,6 +17,7 @@ #define LBG_PAD_OWN 0x020 #define LBG_PADCFGLOCK 0x060 #define LBG_HOSTSW_OWN 0x080 +#define LBG_GPI_IS 0x100 #define LBG_GPI_IE 0x110 #define LBG_COMMUNITY(b, s, e) \ @@ -25,6 +26,7 @@ .padown_offset = LBG_PAD_OWN, \ .padcfglock_offset = LBG_PADCFGLOCK, \ .hostown_offset = LBG_HOSTSW_OWN, \ + .is_offset = LBG_GPI_IS, \ .ie_offset = LBG_GPI_IE, \ .gpp_size = 24, \ .pin_base = (s), \ diff --git a/drivers/pinctrl/intel/pinctrl-merrifield.c b/drivers/pinctrl/intel/pinctrl-merrifield.c index 4b65e1296b8a..04ca8ae95df8 100644 --- a/drivers/pinctrl/intel/pinctrl-merrifield.c +++ b/drivers/pinctrl/intel/pinctrl-merrifield.c @@ -885,7 +885,6 @@ static int mrfld_pinctrl_probe(struct platform_device *pdev) { struct mrfld_family *families; struct mrfld_pinctrl *mp; - struct resource *mem; void __iomem *regs; size_t nfamilies; unsigned int i; @@ -897,8 +896,7 @@ static int mrfld_pinctrl_probe(struct platform_device *pdev) mp->dev = &pdev->dev; raw_spin_lock_init(&mp->lock); - mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); - regs = devm_ioremap_resource(&pdev->dev, mem); + regs = devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(regs)) return PTR_ERR(regs); diff --git a/drivers/pinctrl/intel/pinctrl-sunrisepoint.c b/drivers/pinctrl/intel/pinctrl-sunrisepoint.c index ccafeea4939c..44d7f50bbc82 100644 --- a/drivers/pinctrl/intel/pinctrl-sunrisepoint.c +++ b/drivers/pinctrl/intel/pinctrl-sunrisepoint.c @@ -18,6 +18,7 @@ #define SPT_PAD_OWN 0x020 #define SPT_PADCFGLOCK 0x0a0 #define SPT_HOSTSW_OWN 0x0d0 +#define SPT_GPI_IS 0x100 #define SPT_GPI_IE 0x120 #define SPT_COMMUNITY(b, s, e) \ @@ -26,6 +27,7 @@ .padown_offset = SPT_PAD_OWN, \ .padcfglock_offset = SPT_PADCFGLOCK, \ .hostown_offset = SPT_HOSTSW_OWN, \ + .is_offset = SPT_GPI_IS, \ .ie_offset = SPT_GPI_IE, \ .gpp_size = 24, \ .gpp_num_padown_regs = 4, \ diff --git a/drivers/pinctrl/meson/pinctrl-meson-g12a.c b/drivers/pinctrl/meson/pinctrl-meson-g12a.c index 3475cd7bd2af..582665fd362a 100644 --- a/drivers/pinctrl/meson/pinctrl-meson-g12a.c +++ b/drivers/pinctrl/meson/pinctrl-meson-g12a.c @@ -801,6 +801,9 @@ static const unsigned int remote_ao_input_pins[] = { GPIOAO_5 }; /* ir_out */ static const unsigned int remote_ao_out_pins[] = { GPIOAO_4 }; +/* pwm_a_e */ +static const unsigned int pwm_a_e_pins[] = { GPIOE_2 }; + /* pwm_ao_a */ static const unsigned int pwm_ao_a_pins[] = { GPIOAO_11 }; static const unsigned int pwm_ao_a_hiz_pins[] = { GPIOAO_11 }; @@ -888,6 +891,7 @@ static struct meson_pmx_group meson_g12a_aobus_groups[] = { GROUP(i2c_ao_slave_sda, 3), GROUP(remote_ao_input, 1), GROUP(remote_ao_out, 1), + GROUP(pwm_a_e, 3), GROUP(pwm_ao_a, 3), GROUP(pwm_ao_a_hiz, 2), GROUP(pwm_ao_b, 3), @@ -1192,6 +1196,10 @@ static const char * const remote_ao_out_groups[] = { "remote_ao_out", }; +static const char * const pwm_a_e_groups[] = { + "pwm_a_e", +}; + static const char * const pwm_ao_a_groups[] = { "pwm_ao_a", "pwm_ao_a_hiz", }; @@ -1290,6 +1298,7 @@ static struct meson_pmx_func meson_g12a_aobus_functions[] = { FUNCTION(i2c_ao_slave), FUNCTION(remote_ao_input), FUNCTION(remote_ao_out), + FUNCTION(pwm_a_e), FUNCTION(pwm_ao_a), FUNCTION(pwm_ao_b), FUNCTION(pwm_ao_c), diff --git a/drivers/pinctrl/meson/pinctrl-meson-gxbb.c b/drivers/pinctrl/meson/pinctrl-meson-gxbb.c index 6c640837073e..5bfa56f3847e 100644 --- a/drivers/pinctrl/meson/pinctrl-meson-gxbb.c +++ b/drivers/pinctrl/meson/pinctrl-meson-gxbb.c @@ -192,8 +192,8 @@ static const unsigned int uart_rts_b_pins[] = { GPIODV_27 }; static const unsigned int uart_tx_c_pins[] = { GPIOY_13 }; static const unsigned int uart_rx_c_pins[] = { GPIOY_14 }; -static const unsigned int uart_cts_c_pins[] = { GPIOX_11 }; -static const unsigned int uart_rts_c_pins[] = { GPIOX_12 }; +static const unsigned int uart_cts_c_pins[] = { GPIOY_11 }; +static const unsigned int uart_rts_c_pins[] = { GPIOY_12 }; static const unsigned int i2c_sck_a_pins[] = { GPIODV_25 }; static const unsigned int i2c_sda_a_pins[] = { GPIODV_24 }; @@ -439,10 +439,10 @@ static struct meson_pmx_group meson_gxbb_periphs_groups[] = { GROUP(pwm_f_x, 3, 18), /* Bank Y */ - GROUP(uart_cts_c, 1, 19), - GROUP(uart_rts_c, 1, 18), - GROUP(uart_tx_c, 1, 17), - GROUP(uart_rx_c, 1, 16), + GROUP(uart_cts_c, 1, 17), + GROUP(uart_rts_c, 1, 16), + GROUP(uart_tx_c, 1, 19), + GROUP(uart_rx_c, 1, 18), GROUP(pwm_a_y, 1, 21), GROUP(pwm_f_y, 1, 20), GROUP(i2s_out_ch23_y, 1, 5), diff --git a/drivers/pinctrl/meson/pinctrl-meson.c b/drivers/pinctrl/meson/pinctrl-meson.c index 596786926209..8bba9d053d9f 100644 --- a/drivers/pinctrl/meson/pinctrl-meson.c +++ b/drivers/pinctrl/meson/pinctrl-meson.c @@ -651,6 +651,7 @@ static int meson_pinctrl_parse_dt(struct meson_pinctrl *pc, continue; if (gpio_np) { dev_err(pc->dev, "multiple gpio nodes\n"); + of_node_put(np); return -EINVAL; } gpio_np = np; diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-cp110.c b/drivers/pinctrl/mvebu/pinctrl-armada-cp110.c index 584952b2ba47..17491b27e487 100644 --- a/drivers/pinctrl/mvebu/pinctrl-armada-cp110.c +++ b/drivers/pinctrl/mvebu/pinctrl-armada-cp110.c @@ -32,6 +32,7 @@ enum { V_ARMADA_7K = BIT(0), V_ARMADA_8K_CPM = BIT(1), V_ARMADA_8K_CPS = BIT(2), + V_CP115_STANDALONE = BIT(3), V_ARMADA_7K_8K_CPM = (V_ARMADA_7K | V_ARMADA_8K_CPM), V_ARMADA_7K_8K_CPS = (V_ARMADA_7K | V_ARMADA_8K_CPS), }; @@ -597,7 +598,8 @@ static struct mvebu_mpp_mode armada_cp110_mpp_modes[] = { MPP_FUNCTION(7, "uart0", "rxd"), MPP_FUNCTION(8, "uart2", "rxd"), MPP_FUNCTION(9, "sata0", "present_act"), - MPP_FUNCTION(10, "ge", "mdc")), + MPP_FUNCTION(10, "ge", "mdc"), + MPP_FUNCTION(14, "sdio", "ds")), }; static const struct of_device_id armada_cp110_pinctrl_of_match[] = { @@ -613,6 +615,10 @@ static const struct of_device_id armada_cp110_pinctrl_of_match[] = { .compatible = "marvell,armada-8k-cps-pinctrl", .data = (void *) V_ARMADA_8K_CPS, }, + { + .compatible = "marvell,cp115-standalone-pinctrl", + .data = (void *) V_CP115_STANDALONE, + }, { }, }; @@ -654,16 +660,20 @@ static int armada_cp110_pinctrl_probe(struct platform_device *pdev) switch (i) { case 0 ... 31: - mvebu_pinctrl_assign_variant(m, V_ARMADA_7K_8K_CPS); + mvebu_pinctrl_assign_variant(m, (V_ARMADA_7K_8K_CPS | + V_CP115_STANDALONE)); break; case 32 ... 38: - mvebu_pinctrl_assign_variant(m, V_ARMADA_7K_8K_CPM); + mvebu_pinctrl_assign_variant(m, (V_ARMADA_7K_8K_CPM | + V_CP115_STANDALONE)); break; case 39 ... 43: - mvebu_pinctrl_assign_variant(m, V_ARMADA_8K_CPM); + mvebu_pinctrl_assign_variant(m, (V_ARMADA_8K_CPM | + V_CP115_STANDALONE)); break; case 44 ... 62: - mvebu_pinctrl_assign_variant(m, V_ARMADA_7K_8K_CPM); + mvebu_pinctrl_assign_variant(m, (V_ARMADA_7K_8K_CPM | + V_CP115_STANDALONE)); break; } } diff --git a/drivers/pinctrl/nomadik/pinctrl-abx500.c b/drivers/pinctrl/nomadik/pinctrl-abx500.c index c3595200e1e6..7aa534576a45 100644 --- a/drivers/pinctrl/nomadik/pinctrl-abx500.c +++ b/drivers/pinctrl/nomadik/pinctrl-abx500.c @@ -815,6 +815,7 @@ static int abx500_dt_node_to_map(struct pinctrl_dev *pctldev, &reserved_maps, num_maps); if (ret < 0) { pinctrl_utils_free_map(pctldev, *map, *num_maps); + of_node_put(np); return ret; } } diff --git a/drivers/pinctrl/nomadik/pinctrl-nomadik.c b/drivers/pinctrl/nomadik/pinctrl-nomadik.c index ddd1f466d302..2a8190b11d10 100644 --- a/drivers/pinctrl/nomadik/pinctrl-nomadik.c +++ b/drivers/pinctrl/nomadik/pinctrl-nomadik.c @@ -1508,6 +1508,7 @@ static int nmk_pinctrl_dt_node_to_map(struct pinctrl_dev *pctldev, &reserved_maps, num_maps); if (ret < 0) { pinctrl_utils_free_map(pctldev, *map, *num_maps); + of_node_put(np); return ret; } } diff --git a/drivers/pinctrl/pinctrl-amd.c b/drivers/pinctrl/pinctrl-amd.c index 9b9c61e3f065..2c61141519f8 100644 --- a/drivers/pinctrl/pinctrl-amd.c +++ b/drivers/pinctrl/pinctrl-amd.c @@ -565,15 +565,25 @@ static irqreturn_t amd_gpio_irq_handler(int irq, void *dev_id) !(regval & BIT(INTERRUPT_MASK_OFF))) continue; irq = irq_find_mapping(gc->irq.domain, irqnr + i); - generic_handle_irq(irq); + if (irq != 0) + generic_handle_irq(irq); /* Clear interrupt. * We must read the pin register again, in case the * value was changed while executing * generic_handle_irq() above. + * If we didn't find a mapping for the interrupt, + * disable it in order to avoid a system hang caused + * by an interrupt storm. */ raw_spin_lock_irqsave(&gpio_dev->lock, flags); regval = readl(regs + i); + if (irq == 0) { + regval &= ~BIT(INTERRUPT_ENABLE_OFF); + dev_dbg(&gpio_dev->pdev->dev, + "Disabling spurious GPIO IRQ %d\n", + irqnr + i); + } writel(regval, regs + i); raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); ret = IRQ_HANDLED; @@ -861,10 +871,8 @@ static int amd_gpio_probe(struct platform_device *pdev) return -ENOMEM; irq_base = platform_get_irq(pdev, 0); - if (irq_base < 0) { - dev_err(&pdev->dev, "Failed to get gpio IRQ: %d\n", irq_base); + if (irq_base < 0) return irq_base; - } #ifdef CONFIG_PM_SLEEP gpio_dev->saved_regs = devm_kcalloc(&pdev->dev, amd_pinctrl_desc.npins, diff --git a/drivers/pinctrl/pinctrl-falcon.c b/drivers/pinctrl/pinctrl-falcon.c index ef133a82e612..a454f57c264e 100644 --- a/drivers/pinctrl/pinctrl-falcon.c +++ b/drivers/pinctrl/pinctrl-falcon.c @@ -96,12 +96,8 @@ static void lantiq_load_pin_desc(struct pinctrl_pin_desc *d, int bank, int len) int i; for (i = 0; i < len; i++) { - /* strlen("ioXYZ") + 1 = 6 */ - char *name = kzalloc(6, GFP_KERNEL); - - snprintf(name, 6, "io%d", base + i); d[i].number = base + i; - d[i].name = name; + d[i].name = kasprintf(GFP_KERNEL, "io%d", base + i); } pad_count[bank] = len; } @@ -455,12 +451,15 @@ static int pinctrl_falcon_probe(struct platform_device *pdev) falcon_info.clk[*bank] = clk_get(&ppdev->dev, NULL); if (IS_ERR(falcon_info.clk[*bank])) { dev_err(&ppdev->dev, "failed to get clock\n"); + of_node_put(np) return PTR_ERR(falcon_info.clk[*bank]); } falcon_info.membase[*bank] = devm_ioremap_resource(&pdev->dev, &res); - if (IS_ERR(falcon_info.membase[*bank])) + if (IS_ERR(falcon_info.membase[*bank])) { + of_node_put(np); return PTR_ERR(falcon_info.membase[*bank]); + } avail = pad_r32(falcon_info.membase[*bank], LTQ_PADC_AVAIL); diff --git a/drivers/pinctrl/pinctrl-ingenic.c b/drivers/pinctrl/pinctrl-ingenic.c index c8ef3b91a730..6e2683016c1f 100644 --- a/drivers/pinctrl/pinctrl-ingenic.c +++ b/drivers/pinctrl/pinctrl-ingenic.c @@ -3,6 +3,7 @@ * Ingenic SoCs pinctrl driver * * Copyright (c) 2017 Paul Cercueil <paul@crapouillou.net> + * Copyright (c) 2019 Zhou Yanjie <zhouyanjie@zoho.com> */ #include <linux/compiler.h> @@ -35,11 +36,14 @@ #define JZ4740_GPIO_TRIG 0x70 #define JZ4740_GPIO_FLAG 0x80 -#define JZ4770_GPIO_INT 0x10 -#define JZ4770_GPIO_PAT1 0x30 -#define JZ4770_GPIO_PAT0 0x40 -#define JZ4770_GPIO_FLAG 0x50 -#define JZ4770_GPIO_PEN 0x70 +#define JZ4760_GPIO_INT 0x10 +#define JZ4760_GPIO_PAT1 0x30 +#define JZ4760_GPIO_PAT0 0x40 +#define JZ4760_GPIO_FLAG 0x50 +#define JZ4760_GPIO_PEN 0x70 + +#define X1000_GPIO_PZ_BASE 0x700 +#define X1000_GPIO_PZ_GID2LD 0x7f0 #define REG_SET(x) ((x) + 0x4) #define REG_CLEAR(x) ((x) + 0x8) @@ -49,8 +53,13 @@ enum jz_version { ID_JZ4740, ID_JZ4725B, + ID_JZ4760, + ID_JZ4760B, ID_JZ4770, ID_JZ4780, + ID_X1000, + ID_X1000E, + ID_X1500, }; struct ingenic_chip_info { @@ -338,6 +347,269 @@ static const struct ingenic_chip_info jz4725b_chip_info = { .pull_downs = jz4740_pull_downs, }; +static const u32 jz4760_pull_ups[6] = { + 0xffffffff, 0xfffcf3ff, 0xffffffff, 0xffffcfff, 0xfffffb7c, 0xfffff00f, +}; + +static const u32 jz4760_pull_downs[6] = { + 0x00000000, 0x00030c00, 0x00000000, 0x00003000, 0x00000483, 0x00000ff0, +}; + +static int jz4760_uart0_data_pins[] = { 0xa0, 0xa3, }; +static int jz4760_uart0_hwflow_pins[] = { 0xa1, 0xa2, }; +static int jz4760_uart1_data_pins[] = { 0x7a, 0x7c, }; +static int jz4760_uart1_hwflow_pins[] = { 0x7b, 0x7d, }; +static int jz4760_uart2_data_pins[] = { 0x5c, 0x5e, }; +static int jz4760_uart2_hwflow_pins[] = { 0x5d, 0x5f, }; +static int jz4760_uart3_data_pins[] = { 0x6c, 0x85, }; +static int jz4760_uart3_hwflow_pins[] = { 0x88, 0x89, }; +static int jz4760_mmc0_1bit_a_pins[] = { 0x12, 0x13, 0x14, }; +static int jz4760_mmc0_4bit_a_pins[] = { 0x15, 0x16, 0x17, }; +static int jz4760_mmc0_1bit_e_pins[] = { 0x9c, 0x9d, 0x94, }; +static int jz4760_mmc0_4bit_e_pins[] = { 0x95, 0x96, 0x97, }; +static int jz4760_mmc0_8bit_e_pins[] = { 0x98, 0x99, 0x9a, 0x9b, }; +static int jz4760_mmc1_1bit_d_pins[] = { 0x78, 0x79, 0x74, }; +static int jz4760_mmc1_4bit_d_pins[] = { 0x75, 0x76, 0x77, }; +static int jz4760_mmc1_1bit_e_pins[] = { 0x9c, 0x9d, 0x94, }; +static int jz4760_mmc1_4bit_e_pins[] = { 0x95, 0x96, 0x97, }; +static int jz4760_mmc1_8bit_e_pins[] = { 0x98, 0x99, 0x9a, 0x9b, }; +static int jz4760_mmc2_1bit_b_pins[] = { 0x3c, 0x3d, 0x34, }; +static int jz4760_mmc2_4bit_b_pins[] = { 0x35, 0x3e, 0x3f, }; +static int jz4760_mmc2_1bit_e_pins[] = { 0x9c, 0x9d, 0x94, }; +static int jz4760_mmc2_4bit_e_pins[] = { 0x95, 0x96, 0x97, }; +static int jz4760_mmc2_8bit_e_pins[] = { 0x98, 0x99, 0x9a, 0x9b, }; +static int jz4760_nemc_8bit_data_pins[] = { + 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, +}; +static int jz4760_nemc_16bit_data_pins[] = { + 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, +}; +static int jz4760_nemc_cle_ale_pins[] = { 0x20, 0x21, }; +static int jz4760_nemc_addr_pins[] = { 0x22, 0x23, 0x24, 0x25, }; +static int jz4760_nemc_rd_we_pins[] = { 0x10, 0x11, }; +static int jz4760_nemc_frd_fwe_pins[] = { 0x12, 0x13, }; +static int jz4760_nemc_wait_pins[] = { 0x1b, }; +static int jz4760_nemc_cs1_pins[] = { 0x15, }; +static int jz4760_nemc_cs2_pins[] = { 0x16, }; +static int jz4760_nemc_cs3_pins[] = { 0x17, }; +static int jz4760_nemc_cs4_pins[] = { 0x18, }; +static int jz4760_nemc_cs5_pins[] = { 0x19, }; +static int jz4760_nemc_cs6_pins[] = { 0x1a, }; +static int jz4760_i2c0_pins[] = { 0x7e, 0x7f, }; +static int jz4760_i2c1_pins[] = { 0x9e, 0x9f, }; +static int jz4760_cim_pins[] = { + 0x26, 0x27, 0x28, 0x29, + 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f, 0x30, 0x31, +}; +static int jz4760_lcd_24bit_pins[] = { + 0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47, + 0x48, 0x49, 0x4a, 0x4b, 0x4c, 0x4d, 0x4e, 0x4f, + 0x50, 0x51, 0x52, 0x53, 0x54, 0x55, 0x56, 0x57, + 0x58, 0x59, 0x5a, 0x5b, +}; +static int jz4760_pwm_pwm0_pins[] = { 0x80, }; +static int jz4760_pwm_pwm1_pins[] = { 0x81, }; +static int jz4760_pwm_pwm2_pins[] = { 0x82, }; +static int jz4760_pwm_pwm3_pins[] = { 0x83, }; +static int jz4760_pwm_pwm4_pins[] = { 0x84, }; +static int jz4760_pwm_pwm5_pins[] = { 0x85, }; +static int jz4760_pwm_pwm6_pins[] = { 0x6a, }; +static int jz4760_pwm_pwm7_pins[] = { 0x6b, }; + +static int jz4760_uart0_data_funcs[] = { 0, 0, }; +static int jz4760_uart0_hwflow_funcs[] = { 0, 0, }; +static int jz4760_uart1_data_funcs[] = { 0, 0, }; +static int jz4760_uart1_hwflow_funcs[] = { 0, 0, }; +static int jz4760_uart2_data_funcs[] = { 0, 0, }; +static int jz4760_uart2_hwflow_funcs[] = { 0, 0, }; +static int jz4760_uart3_data_funcs[] = { 0, 1, }; +static int jz4760_uart3_hwflow_funcs[] = { 0, 0, }; +static int jz4760_mmc0_1bit_a_funcs[] = { 1, 1, 0, }; +static int jz4760_mmc0_4bit_a_funcs[] = { 1, 1, 1, }; +static int jz4760_mmc0_1bit_e_funcs[] = { 0, 0, 0, }; +static int jz4760_mmc0_4bit_e_funcs[] = { 0, 0, 0, }; +static int jz4760_mmc0_8bit_e_funcs[] = { 0, 0, 0, 0, }; +static int jz4760_mmc1_1bit_d_funcs[] = { 0, 0, 0, }; +static int jz4760_mmc1_4bit_d_funcs[] = { 0, 0, 0, }; +static int jz4760_mmc1_1bit_e_funcs[] = { 1, 1, 1, }; +static int jz4760_mmc1_4bit_e_funcs[] = { 1, 1, 1, }; +static int jz4760_mmc1_8bit_e_funcs[] = { 1, 1, 1, 1, }; +static int jz4760_mmc2_1bit_b_funcs[] = { 0, 0, 0, }; +static int jz4760_mmc2_4bit_b_funcs[] = { 0, 0, 0, }; +static int jz4760_mmc2_1bit_e_funcs[] = { 2, 2, 2, }; +static int jz4760_mmc2_4bit_e_funcs[] = { 2, 2, 2, }; +static int jz4760_mmc2_8bit_e_funcs[] = { 2, 2, 2, 2, }; +static int jz4760_nemc_8bit_data_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, }; +static int jz4760_nemc_16bit_data_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, }; +static int jz4760_nemc_cle_ale_funcs[] = { 0, 0, }; +static int jz4760_nemc_addr_funcs[] = { 0, 0, 0, 0, }; +static int jz4760_nemc_rd_we_funcs[] = { 0, 0, }; +static int jz4760_nemc_frd_fwe_funcs[] = { 0, 0, }; +static int jz4760_nemc_wait_funcs[] = { 0, }; +static int jz4760_nemc_cs1_funcs[] = { 0, }; +static int jz4760_nemc_cs2_funcs[] = { 0, }; +static int jz4760_nemc_cs3_funcs[] = { 0, }; +static int jz4760_nemc_cs4_funcs[] = { 0, }; +static int jz4760_nemc_cs5_funcs[] = { 0, }; +static int jz4760_nemc_cs6_funcs[] = { 0, }; +static int jz4760_i2c0_funcs[] = { 0, 0, }; +static int jz4760_i2c1_funcs[] = { 0, 0, }; +static int jz4760_cim_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, }; +static int jz4760_lcd_24bit_funcs[] = { + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, +}; +static int jz4760_pwm_pwm0_funcs[] = { 0, }; +static int jz4760_pwm_pwm1_funcs[] = { 0, }; +static int jz4760_pwm_pwm2_funcs[] = { 0, }; +static int jz4760_pwm_pwm3_funcs[] = { 0, }; +static int jz4760_pwm_pwm4_funcs[] = { 0, }; +static int jz4760_pwm_pwm5_funcs[] = { 0, }; +static int jz4760_pwm_pwm6_funcs[] = { 0, }; +static int jz4760_pwm_pwm7_funcs[] = { 0, }; + +static const struct group_desc jz4760_groups[] = { + INGENIC_PIN_GROUP("uart0-data", jz4760_uart0_data), + INGENIC_PIN_GROUP("uart0-hwflow", jz4760_uart0_hwflow), + INGENIC_PIN_GROUP("uart1-data", jz4760_uart1_data), + INGENIC_PIN_GROUP("uart1-hwflow", jz4760_uart1_hwflow), + INGENIC_PIN_GROUP("uart2-data", jz4760_uart2_data), + INGENIC_PIN_GROUP("uart2-hwflow", jz4760_uart2_hwflow), + INGENIC_PIN_GROUP("uart3-data", jz4760_uart3_data), + INGENIC_PIN_GROUP("uart3-hwflow", jz4760_uart3_hwflow), + INGENIC_PIN_GROUP("mmc0-1bit-a", jz4760_mmc0_1bit_a), + INGENIC_PIN_GROUP("mmc0-4bit-a", jz4760_mmc0_4bit_a), + INGENIC_PIN_GROUP("mmc0-1bit-e", jz4760_mmc0_1bit_e), + INGENIC_PIN_GROUP("mmc0-4bit-e", jz4760_mmc0_4bit_e), + INGENIC_PIN_GROUP("mmc0-8bit-e", jz4760_mmc0_8bit_e), + INGENIC_PIN_GROUP("mmc1-1bit-d", jz4760_mmc1_1bit_d), + INGENIC_PIN_GROUP("mmc1-4bit-d", jz4760_mmc1_4bit_d), + INGENIC_PIN_GROUP("mmc1-1bit-e", jz4760_mmc1_1bit_e), + INGENIC_PIN_GROUP("mmc1-4bit-e", jz4760_mmc1_4bit_e), + INGENIC_PIN_GROUP("mmc1-8bit-e", jz4760_mmc1_8bit_e), + INGENIC_PIN_GROUP("mmc2-1bit-b", jz4760_mmc2_1bit_b), + INGENIC_PIN_GROUP("mmc2-4bit-b", jz4760_mmc2_4bit_b), + INGENIC_PIN_GROUP("mmc2-1bit-e", jz4760_mmc2_1bit_e), + INGENIC_PIN_GROUP("mmc2-4bit-e", jz4760_mmc2_4bit_e), + INGENIC_PIN_GROUP("mmc2-8bit-e", jz4760_mmc2_8bit_e), + INGENIC_PIN_GROUP("nemc-8bit-data", jz4760_nemc_8bit_data), + INGENIC_PIN_GROUP("nemc-16bit-data", jz4760_nemc_16bit_data), + INGENIC_PIN_GROUP("nemc-cle-ale", jz4760_nemc_cle_ale), + INGENIC_PIN_GROUP("nemc-addr", jz4760_nemc_addr), + INGENIC_PIN_GROUP("nemc-rd-we", jz4760_nemc_rd_we), + INGENIC_PIN_GROUP("nemc-frd-fwe", jz4760_nemc_frd_fwe), + INGENIC_PIN_GROUP("nemc-wait", jz4760_nemc_wait), + INGENIC_PIN_GROUP("nemc-cs1", jz4760_nemc_cs1), + INGENIC_PIN_GROUP("nemc-cs2", jz4760_nemc_cs2), + INGENIC_PIN_GROUP("nemc-cs3", jz4760_nemc_cs3), + INGENIC_PIN_GROUP("nemc-cs4", jz4760_nemc_cs4), + INGENIC_PIN_GROUP("nemc-cs5", jz4760_nemc_cs5), + INGENIC_PIN_GROUP("nemc-cs6", jz4760_nemc_cs6), + INGENIC_PIN_GROUP("i2c0-data", jz4760_i2c0), + INGENIC_PIN_GROUP("i2c1-data", jz4760_i2c1), + INGENIC_PIN_GROUP("cim-data", jz4760_cim), + INGENIC_PIN_GROUP("lcd-24bit", jz4760_lcd_24bit), + { "lcd-no-pins", }, + INGENIC_PIN_GROUP("pwm0", jz4760_pwm_pwm0), + INGENIC_PIN_GROUP("pwm1", jz4760_pwm_pwm1), + INGENIC_PIN_GROUP("pwm2", jz4760_pwm_pwm2), + INGENIC_PIN_GROUP("pwm3", jz4760_pwm_pwm3), + INGENIC_PIN_GROUP("pwm4", jz4760_pwm_pwm4), + INGENIC_PIN_GROUP("pwm5", jz4760_pwm_pwm5), + INGENIC_PIN_GROUP("pwm6", jz4760_pwm_pwm6), + INGENIC_PIN_GROUP("pwm7", jz4760_pwm_pwm7), +}; + +static const char *jz4760_uart0_groups[] = { "uart0-data", "uart0-hwflow", }; +static const char *jz4760_uart1_groups[] = { "uart1-data", "uart1-hwflow", }; +static const char *jz4760_uart2_groups[] = { "uart2-data", "uart2-hwflow", }; +static const char *jz4760_uart3_groups[] = { "uart3-data", "uart3-hwflow", }; +static const char *jz4760_mmc0_groups[] = { + "mmc0-1bit-a", "mmc0-4bit-a", + "mmc0-1bit-e", "mmc0-4bit-e", "mmc0-8bit-e", +}; +static const char *jz4760_mmc1_groups[] = { + "mmc1-1bit-d", "mmc1-4bit-d", + "mmc1-1bit-e", "mmc1-4bit-e", "mmc1-8bit-e", +}; +static const char *jz4760_mmc2_groups[] = { + "mmc2-1bit-b", "mmc2-4bit-b", + "mmc2-1bit-e", "mmc2-4bit-e", "mmc2-8bit-e", +}; +static const char *jz4760_nemc_groups[] = { + "nemc-8bit-data", "nemc-16bit-data", "nemc-cle-ale", + "nemc-addr", "nemc-rd-we", "nemc-frd-fwe", "nemc-wait", +}; +static const char *jz4760_cs1_groups[] = { "nemc-cs1", }; +static const char *jz4760_cs2_groups[] = { "nemc-cs2", }; +static const char *jz4760_cs3_groups[] = { "nemc-cs3", }; +static const char *jz4760_cs4_groups[] = { "nemc-cs4", }; +static const char *jz4760_cs5_groups[] = { "nemc-cs5", }; +static const char *jz4760_cs6_groups[] = { "nemc-cs6", }; +static const char *jz4760_i2c0_groups[] = { "i2c0-data", }; +static const char *jz4760_i2c1_groups[] = { "i2c1-data", }; +static const char *jz4760_cim_groups[] = { "cim-data", }; +static const char *jz4760_lcd_groups[] = { "lcd-24bit", "lcd-no-pins", }; +static const char *jz4760_pwm0_groups[] = { "pwm0", }; +static const char *jz4760_pwm1_groups[] = { "pwm1", }; +static const char *jz4760_pwm2_groups[] = { "pwm2", }; +static const char *jz4760_pwm3_groups[] = { "pwm3", }; +static const char *jz4760_pwm4_groups[] = { "pwm4", }; +static const char *jz4760_pwm5_groups[] = { "pwm5", }; +static const char *jz4760_pwm6_groups[] = { "pwm6", }; +static const char *jz4760_pwm7_groups[] = { "pwm7", }; + +static const struct function_desc jz4760_functions[] = { + { "uart0", jz4760_uart0_groups, ARRAY_SIZE(jz4760_uart0_groups), }, + { "uart1", jz4760_uart1_groups, ARRAY_SIZE(jz4760_uart1_groups), }, + { "uart2", jz4760_uart2_groups, ARRAY_SIZE(jz4760_uart2_groups), }, + { "uart3", jz4760_uart3_groups, ARRAY_SIZE(jz4760_uart3_groups), }, + { "mmc0", jz4760_mmc0_groups, ARRAY_SIZE(jz4760_mmc0_groups), }, + { "mmc1", jz4760_mmc1_groups, ARRAY_SIZE(jz4760_mmc1_groups), }, + { "mmc2", jz4760_mmc2_groups, ARRAY_SIZE(jz4760_mmc2_groups), }, + { "nemc", jz4760_nemc_groups, ARRAY_SIZE(jz4760_nemc_groups), }, + { "nemc-cs1", jz4760_cs1_groups, ARRAY_SIZE(jz4760_cs1_groups), }, + { "nemc-cs2", jz4760_cs2_groups, ARRAY_SIZE(jz4760_cs2_groups), }, + { "nemc-cs3", jz4760_cs3_groups, ARRAY_SIZE(jz4760_cs3_groups), }, + { "nemc-cs4", jz4760_cs4_groups, ARRAY_SIZE(jz4760_cs4_groups), }, + { "nemc-cs5", jz4760_cs5_groups, ARRAY_SIZE(jz4760_cs5_groups), }, + { "nemc-cs6", jz4760_cs6_groups, ARRAY_SIZE(jz4760_cs6_groups), }, + { "i2c0", jz4760_i2c0_groups, ARRAY_SIZE(jz4760_i2c0_groups), }, + { "i2c1", jz4760_i2c1_groups, ARRAY_SIZE(jz4760_i2c1_groups), }, + { "cim", jz4760_cim_groups, ARRAY_SIZE(jz4760_cim_groups), }, + { "lcd", jz4760_lcd_groups, ARRAY_SIZE(jz4760_lcd_groups), }, + { "pwm0", jz4760_pwm0_groups, ARRAY_SIZE(jz4760_pwm0_groups), }, + { "pwm1", jz4760_pwm1_groups, ARRAY_SIZE(jz4760_pwm1_groups), }, + { "pwm2", jz4760_pwm2_groups, ARRAY_SIZE(jz4760_pwm2_groups), }, + { "pwm3", jz4760_pwm3_groups, ARRAY_SIZE(jz4760_pwm3_groups), }, + { "pwm4", jz4760_pwm4_groups, ARRAY_SIZE(jz4760_pwm4_groups), }, + { "pwm5", jz4760_pwm5_groups, ARRAY_SIZE(jz4760_pwm5_groups), }, + { "pwm6", jz4760_pwm6_groups, ARRAY_SIZE(jz4760_pwm6_groups), }, + { "pwm7", jz4760_pwm7_groups, ARRAY_SIZE(jz4760_pwm7_groups), }, +}; + +static const struct ingenic_chip_info jz4760_chip_info = { + .num_chips = 6, + .groups = jz4760_groups, + .num_groups = ARRAY_SIZE(jz4760_groups), + .functions = jz4760_functions, + .num_functions = ARRAY_SIZE(jz4760_functions), + .pull_ups = jz4760_pull_ups, + .pull_downs = jz4760_pull_downs, +}; + +static const struct ingenic_chip_info jz4760b_chip_info = { + .num_chips = 6, + .groups = jz4760_groups, + .num_groups = ARRAY_SIZE(jz4760_groups), + .functions = jz4760_functions, + .num_functions = ARRAY_SIZE(jz4760_functions), + .pull_ups = jz4760_pull_ups, + .pull_downs = jz4760_pull_downs, +}; + static const u32 jz4770_pull_ups[6] = { 0x3fffffff, 0xfff0030c, 0xffffffff, 0xffff4fff, 0xfffffb7c, 0xffa7f00f, }; @@ -744,6 +1016,320 @@ static const struct ingenic_chip_info jz4780_chip_info = { .pull_downs = jz4770_pull_downs, }; +static const u32 x1000_pull_ups[4] = { + 0xffffffff, 0x8dffffff, 0x7d3fffff, 0xffffffff, +}; + +static const u32 x1000_pull_downs[4] = { + 0x00000000, 0x02000000, 0x02000000, 0x00000000, +}; + +static int x1000_uart0_data_pins[] = { 0x4a, 0x4b, }; +static int x1000_uart0_hwflow_pins[] = { 0x4c, 0x4d, }; +static int x1000_uart1_data_a_pins[] = { 0x04, 0x05, }; +static int x1000_uart1_data_d_pins[] = { 0x62, 0x63, }; +static int x1000_uart1_hwflow_d_pins[] = { 0x64, 0x65, }; +static int x1000_uart2_data_a_pins[] = { 0x02, 0x03, }; +static int x1000_uart2_data_d_pins[] = { 0x65, 0x64, }; +static int x1000_mmc0_1bit_pins[] = { 0x18, 0x19, 0x17, }; +static int x1000_mmc0_4bit_pins[] = { 0x16, 0x15, 0x14, }; +static int x1000_mmc0_8bit_pins[] = { 0x13, 0x12, 0x11, 0x10, }; +static int x1000_mmc1_1bit_pins[] = { 0x40, 0x41, 0x42, }; +static int x1000_mmc1_4bit_pins[] = { 0x43, 0x44, 0x45, }; +static int x1000_nemc_8bit_data_pins[] = { + 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, +}; +static int x1000_nemc_16bit_data_pins[] = { + 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, +}; +static int x1000_nemc_addr_pins[] = { + 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27, + 0x28, 0x29, 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f, +}; +static int x1000_nemc_rd_we_pins[] = { 0x30, 0x31, }; +static int x1000_nemc_wait_pins[] = { 0x34, }; +static int x1000_nemc_cs1_pins[] = { 0x32, }; +static int x1000_nemc_cs2_pins[] = { 0x33, }; +static int x1000_i2c0_pins[] = { 0x38, 0x37, }; +static int x1000_i2c1_a_pins[] = { 0x01, 0x00, }; +static int x1000_i2c1_c_pins[] = { 0x5b, 0x5a, }; +static int x1000_i2c2_pins[] = { 0x61, 0x60, }; +static int x1000_cim_pins[] = { + 0x08, 0x09, 0x0a, 0x0b, + 0x13, 0x12, 0x11, 0x10, 0x0f, 0x0e, 0x0d, 0x0c, +}; +static int x1000_lcd_8bit_pins[] = { + 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, + 0x30, 0x31, 0x32, 0x33, 0x34, +}; +static int x1000_lcd_16bit_pins[] = { + 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, +}; +static int x1000_pwm_pwm0_pins[] = { 0x59, }; +static int x1000_pwm_pwm1_pins[] = { 0x5a, }; +static int x1000_pwm_pwm2_pins[] = { 0x5b, }; +static int x1000_pwm_pwm3_pins[] = { 0x26, }; +static int x1000_pwm_pwm4_pins[] = { 0x58, }; +static int x1000_mac_pins[] = { + 0x27, 0x28, 0x29, 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f, 0x26, +}; + +static int x1000_uart0_data_funcs[] = { 0, 0, }; +static int x1000_uart0_hwflow_funcs[] = { 0, 0, }; +static int x1000_uart1_data_a_funcs[] = { 2, 2, }; +static int x1000_uart1_data_d_funcs[] = { 1, 1, }; +static int x1000_uart1_hwflow_d_funcs[] = { 1, 1, }; +static int x1000_uart2_data_a_funcs[] = { 2, 2, }; +static int x1000_uart2_data_d_funcs[] = { 0, 0, }; +static int x1000_mmc0_1bit_funcs[] = { 1, 1, 1, }; +static int x1000_mmc0_4bit_funcs[] = { 1, 1, 1, }; +static int x1000_mmc0_8bit_funcs[] = { 1, 1, 1, 1, 1, }; +static int x1000_mmc1_1bit_funcs[] = { 0, 0, 0, }; +static int x1000_mmc1_4bit_funcs[] = { 0, 0, 0, }; +static int x1000_nemc_8bit_data_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, }; +static int x1000_nemc_16bit_data_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, }; +static int x1000_nemc_addr_funcs[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, +}; +static int x1000_nemc_rd_we_funcs[] = { 0, 0, }; +static int x1000_nemc_wait_funcs[] = { 0, }; +static int x1000_nemc_cs1_funcs[] = { 0, }; +static int x1000_nemc_cs2_funcs[] = { 0, }; +static int x1000_i2c0_funcs[] = { 0, 0, }; +static int x1000_i2c1_a_funcs[] = { 2, 2, }; +static int x1000_i2c1_c_funcs[] = { 0, 0, }; +static int x1000_i2c2_funcs[] = { 1, 1, }; +static int x1000_cim_funcs[] = { 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, }; +static int x1000_lcd_8bit_funcs[] = { + 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, +}; +static int x1000_lcd_16bit_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, }; +static int x1000_pwm_pwm0_funcs[] = { 0, }; +static int x1000_pwm_pwm1_funcs[] = { 1, }; +static int x1000_pwm_pwm2_funcs[] = { 1, }; +static int x1000_pwm_pwm3_funcs[] = { 2, }; +static int x1000_pwm_pwm4_funcs[] = { 0, }; +static int x1000_mac_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, }; + +static const struct group_desc x1000_groups[] = { + INGENIC_PIN_GROUP("uart0-data", x1000_uart0_data), + INGENIC_PIN_GROUP("uart0-hwflow", x1000_uart0_hwflow), + INGENIC_PIN_GROUP("uart1-data-a", x1000_uart1_data_a), + INGENIC_PIN_GROUP("uart1-data-d", x1000_uart1_data_d), + INGENIC_PIN_GROUP("uart1-hwflow-d", x1000_uart1_hwflow_d), + INGENIC_PIN_GROUP("uart2-data-a", x1000_uart2_data_a), + INGENIC_PIN_GROUP("uart2-data-d", x1000_uart2_data_d), + INGENIC_PIN_GROUP("mmc0-1bit", x1000_mmc0_1bit), + INGENIC_PIN_GROUP("mmc0-4bit", x1000_mmc0_4bit), + INGENIC_PIN_GROUP("mmc0-8bit", x1000_mmc0_8bit), + INGENIC_PIN_GROUP("mmc1-1bit", x1000_mmc1_1bit), + INGENIC_PIN_GROUP("mmc1-4bit", x1000_mmc1_4bit), + INGENIC_PIN_GROUP("nemc-8bit-data", x1000_nemc_8bit_data), + INGENIC_PIN_GROUP("nemc-16bit-data", x1000_nemc_16bit_data), + INGENIC_PIN_GROUP("nemc-addr", x1000_nemc_addr), + INGENIC_PIN_GROUP("nemc-rd-we", x1000_nemc_rd_we), + INGENIC_PIN_GROUP("nemc-wait", x1000_nemc_wait), + INGENIC_PIN_GROUP("nemc-cs1", x1000_nemc_cs1), + INGENIC_PIN_GROUP("nemc-cs2", x1000_nemc_cs2), + INGENIC_PIN_GROUP("i2c0-data", x1000_i2c0), + INGENIC_PIN_GROUP("i2c1-data-a", x1000_i2c1_a), + INGENIC_PIN_GROUP("i2c1-data-c", x1000_i2c1_c), + INGENIC_PIN_GROUP("i2c2-data", x1000_i2c2), + INGENIC_PIN_GROUP("cim-data", x1000_cim), + INGENIC_PIN_GROUP("lcd-8bit", x1000_lcd_8bit), + INGENIC_PIN_GROUP("lcd-16bit", x1000_lcd_16bit), + { "lcd-no-pins", }, + INGENIC_PIN_GROUP("pwm0", x1000_pwm_pwm0), + INGENIC_PIN_GROUP("pwm1", x1000_pwm_pwm1), + INGENIC_PIN_GROUP("pwm2", x1000_pwm_pwm2), + INGENIC_PIN_GROUP("pwm3", x1000_pwm_pwm3), + INGENIC_PIN_GROUP("pwm4", x1000_pwm_pwm4), + INGENIC_PIN_GROUP("mac", x1000_mac), +}; + +static const char *x1000_uart0_groups[] = { "uart0-data", "uart0-hwflow", }; +static const char *x1000_uart1_groups[] = { + "uart1-data-a", "uart1-data-d", "uart1-hwflow-d", +}; +static const char *x1000_uart2_groups[] = { "uart2-data-a", "uart2-data-d", }; +static const char *x1000_mmc0_groups[] = { + "mmc0-1bit", "mmc0-4bit", "mmc0-8bit", +}; +static const char *x1000_mmc1_groups[] = { + "mmc1-1bit-e", "mmc1-4bit-e", +}; +static const char *x1000_nemc_groups[] = { + "nemc-8bit-data", "nemc-16bit-data", + "nemc-addr", "nemc-rd-we", "nemc-wait", +}; +static const char *x1000_cs1_groups[] = { "nemc-cs1", }; +static const char *x1000_cs2_groups[] = { "nemc-cs2", }; +static const char *x1000_i2c0_groups[] = { "i2c0-data", }; +static const char *x1000_i2c1_groups[] = { "i2c1-data-a", "i2c1-data-c", }; +static const char *x1000_i2c2_groups[] = { "i2c2-data", }; +static const char *x1000_cim_groups[] = { "cim-data", }; +static const char *x1000_lcd_groups[] = { + "lcd-8bit", "lcd-16bit", "lcd-no-pins", +}; +static const char *x1000_pwm0_groups[] = { "pwm0", }; +static const char *x1000_pwm1_groups[] = { "pwm1", }; +static const char *x1000_pwm2_groups[] = { "pwm2", }; +static const char *x1000_pwm3_groups[] = { "pwm3", }; +static const char *x1000_pwm4_groups[] = { "pwm4", }; +static const char *x1000_mac_groups[] = { "mac", }; + +static const struct function_desc x1000_functions[] = { + { "uart0", x1000_uart0_groups, ARRAY_SIZE(x1000_uart0_groups), }, + { "uart1", x1000_uart1_groups, ARRAY_SIZE(x1000_uart1_groups), }, + { "uart2", x1000_uart2_groups, ARRAY_SIZE(x1000_uart2_groups), }, + { "mmc0", x1000_mmc0_groups, ARRAY_SIZE(x1000_mmc0_groups), }, + { "mmc1", x1000_mmc1_groups, ARRAY_SIZE(x1000_mmc1_groups), }, + { "nemc", x1000_nemc_groups, ARRAY_SIZE(x1000_nemc_groups), }, + { "nemc-cs1", x1000_cs1_groups, ARRAY_SIZE(x1000_cs1_groups), }, + { "nemc-cs2", x1000_cs2_groups, ARRAY_SIZE(x1000_cs2_groups), }, + { "i2c0", x1000_i2c0_groups, ARRAY_SIZE(x1000_i2c0_groups), }, + { "i2c1", x1000_i2c1_groups, ARRAY_SIZE(x1000_i2c1_groups), }, + { "i2c2", x1000_i2c2_groups, ARRAY_SIZE(x1000_i2c2_groups), }, + { "cim", x1000_cim_groups, ARRAY_SIZE(x1000_cim_groups), }, + { "lcd", x1000_lcd_groups, ARRAY_SIZE(x1000_lcd_groups), }, + { "pwm0", x1000_pwm0_groups, ARRAY_SIZE(x1000_pwm0_groups), }, + { "pwm1", x1000_pwm1_groups, ARRAY_SIZE(x1000_pwm1_groups), }, + { "pwm2", x1000_pwm2_groups, ARRAY_SIZE(x1000_pwm2_groups), }, + { "pwm3", x1000_pwm3_groups, ARRAY_SIZE(x1000_pwm3_groups), }, + { "pwm4", x1000_pwm4_groups, ARRAY_SIZE(x1000_pwm4_groups), }, + { "mac", x1000_mac_groups, ARRAY_SIZE(x1000_mac_groups), }, +}; + +static const struct ingenic_chip_info x1000_chip_info = { + .num_chips = 4, + .groups = x1000_groups, + .num_groups = ARRAY_SIZE(x1000_groups), + .functions = x1000_functions, + .num_functions = ARRAY_SIZE(x1000_functions), + .pull_ups = x1000_pull_ups, + .pull_downs = x1000_pull_downs, +}; + +static const struct ingenic_chip_info x1000e_chip_info = { + .num_chips = 4, + .groups = x1000_groups, + .num_groups = ARRAY_SIZE(x1000_groups), + .functions = x1000_functions, + .num_functions = ARRAY_SIZE(x1000_functions), + .pull_ups = x1000_pull_ups, + .pull_downs = x1000_pull_downs, +}; + +static int x1500_uart0_data_pins[] = { 0x4a, 0x4b, }; +static int x1500_uart0_hwflow_pins[] = { 0x4c, 0x4d, }; +static int x1500_uart1_data_a_pins[] = { 0x04, 0x05, }; +static int x1500_uart1_data_d_pins[] = { 0x62, 0x63, }; +static int x1500_uart1_hwflow_d_pins[] = { 0x64, 0x65, }; +static int x1500_uart2_data_a_pins[] = { 0x02, 0x03, }; +static int x1500_uart2_data_d_pins[] = { 0x65, 0x64, }; +static int x1500_mmc0_1bit_pins[] = { 0x18, 0x19, 0x17, }; +static int x1500_mmc0_4bit_pins[] = { 0x16, 0x15, 0x14, }; +static int x1500_i2c0_pins[] = { 0x38, 0x37, }; +static int x1500_i2c1_a_pins[] = { 0x01, 0x00, }; +static int x1500_i2c1_c_pins[] = { 0x5b, 0x5a, }; +static int x1500_i2c2_pins[] = { 0x61, 0x60, }; +static int x1500_cim_pins[] = { + 0x08, 0x09, 0x0a, 0x0b, + 0x13, 0x12, 0x11, 0x10, 0x0f, 0x0e, 0x0d, 0x0c, +}; +static int x1500_pwm_pwm0_pins[] = { 0x59, }; +static int x1500_pwm_pwm1_pins[] = { 0x5a, }; +static int x1500_pwm_pwm2_pins[] = { 0x5b, }; +static int x1500_pwm_pwm3_pins[] = { 0x26, }; +static int x1500_pwm_pwm4_pins[] = { 0x58, }; + +static int x1500_uart0_data_funcs[] = { 0, 0, }; +static int x1500_uart0_hwflow_funcs[] = { 0, 0, }; +static int x1500_uart1_data_a_funcs[] = { 2, 2, }; +static int x1500_uart1_data_d_funcs[] = { 1, 1, }; +static int x1500_uart1_hwflow_d_funcs[] = { 1, 1, }; +static int x1500_uart2_data_a_funcs[] = { 2, 2, }; +static int x1500_uart2_data_d_funcs[] = { 0, 0, }; +static int x1500_mmc0_1bit_funcs[] = { 1, 1, 1, }; +static int x1500_mmc0_4bit_funcs[] = { 1, 1, 1, }; +static int x1500_i2c0_funcs[] = { 0, 0, }; +static int x1500_i2c1_a_funcs[] = { 2, 2, }; +static int x1500_i2c1_c_funcs[] = { 0, 0, }; +static int x1500_i2c2_funcs[] = { 1, 1, }; +static int x1500_cim_funcs[] = { 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, }; +static int x1500_pwm_pwm0_funcs[] = { 0, }; +static int x1500_pwm_pwm1_funcs[] = { 1, }; +static int x1500_pwm_pwm2_funcs[] = { 1, }; +static int x1500_pwm_pwm3_funcs[] = { 2, }; +static int x1500_pwm_pwm4_funcs[] = { 0, }; + +static const struct group_desc x1500_groups[] = { + INGENIC_PIN_GROUP("uart0-data", x1500_uart0_data), + INGENIC_PIN_GROUP("uart0-hwflow", x1500_uart0_hwflow), + INGENIC_PIN_GROUP("uart1-data-a", x1500_uart1_data_a), + INGENIC_PIN_GROUP("uart1-data-d", x1500_uart1_data_d), + INGENIC_PIN_GROUP("uart1-hwflow-d", x1500_uart1_hwflow_d), + INGENIC_PIN_GROUP("uart2-data-a", x1500_uart2_data_a), + INGENIC_PIN_GROUP("uart2-data-d", x1500_uart2_data_d), + INGENIC_PIN_GROUP("mmc0-1bit", x1500_mmc0_1bit), + INGENIC_PIN_GROUP("mmc0-4bit", x1500_mmc0_4bit), + INGENIC_PIN_GROUP("i2c0-data", x1500_i2c0), + INGENIC_PIN_GROUP("i2c1-data-a", x1500_i2c1_a), + INGENIC_PIN_GROUP("i2c1-data-c", x1500_i2c1_c), + INGENIC_PIN_GROUP("i2c2-data", x1500_i2c2), + INGENIC_PIN_GROUP("cim-data", x1500_cim), + { "lcd-no-pins", }, + INGENIC_PIN_GROUP("pwm0", x1500_pwm_pwm0), + INGENIC_PIN_GROUP("pwm1", x1500_pwm_pwm1), + INGENIC_PIN_GROUP("pwm2", x1500_pwm_pwm2), + INGENIC_PIN_GROUP("pwm3", x1500_pwm_pwm3), + INGENIC_PIN_GROUP("pwm4", x1500_pwm_pwm4), +}; + +static const char *x1500_uart0_groups[] = { "uart0-data", "uart0-hwflow", }; +static const char *x1500_uart1_groups[] = { + "uart1-data-a", "uart1-data-d", "uart1-hwflow-d", +}; +static const char *x1500_uart2_groups[] = { "uart2-data-a", "uart2-data-d", }; +static const char *x1500_mmc0_groups[] = { "mmc0-1bit", "mmc0-4bit", }; +static const char *x1500_i2c0_groups[] = { "i2c0-data", }; +static const char *x1500_i2c1_groups[] = { "i2c1-data-a", "i2c1-data-c", }; +static const char *x1500_i2c2_groups[] = { "i2c2-data", }; +static const char *x1500_cim_groups[] = { "cim-data", }; +static const char *x1500_lcd_groups[] = { "lcd-no-pins", }; +static const char *x1500_pwm0_groups[] = { "pwm0", }; +static const char *x1500_pwm1_groups[] = { "pwm1", }; +static const char *x1500_pwm2_groups[] = { "pwm2", }; +static const char *x1500_pwm3_groups[] = { "pwm3", }; +static const char *x1500_pwm4_groups[] = { "pwm4", }; + +static const struct function_desc x1500_functions[] = { + { "uart0", x1500_uart0_groups, ARRAY_SIZE(x1500_uart0_groups), }, + { "uart1", x1500_uart1_groups, ARRAY_SIZE(x1500_uart1_groups), }, + { "uart2", x1500_uart2_groups, ARRAY_SIZE(x1500_uart2_groups), }, + { "mmc0", x1500_mmc0_groups, ARRAY_SIZE(x1500_mmc0_groups), }, + { "i2c0", x1500_i2c0_groups, ARRAY_SIZE(x1500_i2c0_groups), }, + { "i2c1", x1500_i2c1_groups, ARRAY_SIZE(x1500_i2c1_groups), }, + { "i2c2", x1500_i2c2_groups, ARRAY_SIZE(x1500_i2c2_groups), }, + { "cim", x1500_cim_groups, ARRAY_SIZE(x1500_cim_groups), }, + { "lcd", x1500_lcd_groups, ARRAY_SIZE(x1500_lcd_groups), }, + { "pwm0", x1500_pwm0_groups, ARRAY_SIZE(x1500_pwm0_groups), }, + { "pwm1", x1500_pwm1_groups, ARRAY_SIZE(x1500_pwm1_groups), }, + { "pwm2", x1500_pwm2_groups, ARRAY_SIZE(x1500_pwm2_groups), }, + { "pwm3", x1500_pwm3_groups, ARRAY_SIZE(x1500_pwm3_groups), }, + { "pwm4", x1500_pwm4_groups, ARRAY_SIZE(x1500_pwm4_groups), }, +}; + +static const struct ingenic_chip_info x1500_chip_info = { + .num_chips = 4, + .groups = x1500_groups, + .num_groups = ARRAY_SIZE(x1500_groups), + .functions = x1500_functions, + .num_functions = ARRAY_SIZE(x1500_functions), + .pull_ups = x1000_pull_ups, + .pull_downs = x1000_pull_downs, +}; + static u32 ingenic_gpio_read_reg(struct ingenic_gpio_chip *jzgc, u8 reg) { unsigned int val; @@ -764,6 +1350,23 @@ static void ingenic_gpio_set_bit(struct ingenic_gpio_chip *jzgc, regmap_write(jzgc->jzpc->map, jzgc->reg_base + reg, BIT(offset)); } +static void ingenic_gpio_shadow_set_bit(struct ingenic_gpio_chip *jzgc, + u8 reg, u8 offset, bool set) +{ + if (set) + reg = REG_SET(reg); + else + reg = REG_CLEAR(reg); + + regmap_write(jzgc->jzpc->map, X1000_GPIO_PZ_BASE + reg, BIT(offset)); +} + +static void ingenic_gpio_shadow_set_bit_load(struct ingenic_gpio_chip *jzgc) +{ + regmap_write(jzgc->jzpc->map, X1000_GPIO_PZ_GID2LD, + jzgc->gc.base / PINS_PER_GPIO_CHIP); +} + static inline bool ingenic_gpio_get_value(struct ingenic_gpio_chip *jzgc, u8 offset) { @@ -775,8 +1378,8 @@ static inline bool ingenic_gpio_get_value(struct ingenic_gpio_chip *jzgc, static void ingenic_gpio_set_value(struct ingenic_gpio_chip *jzgc, u8 offset, int value) { - if (jzgc->jzpc->version >= ID_JZ4770) - ingenic_gpio_set_bit(jzgc, JZ4770_GPIO_PAT0, offset, !!value); + if (jzgc->jzpc->version >= ID_JZ4760) + ingenic_gpio_set_bit(jzgc, JZ4760_GPIO_PAT0, offset, !!value); else ingenic_gpio_set_bit(jzgc, JZ4740_GPIO_DATA, offset, !!value); } @@ -786,9 +1389,9 @@ static void irq_set_type(struct ingenic_gpio_chip *jzgc, { u8 reg1, reg2; - if (jzgc->jzpc->version >= ID_JZ4770) { - reg1 = JZ4770_GPIO_PAT1; - reg2 = JZ4770_GPIO_PAT0; + if (jzgc->jzpc->version >= ID_JZ4760) { + reg1 = JZ4760_GPIO_PAT1; + reg2 = JZ4760_GPIO_PAT0; } else { reg1 = JZ4740_GPIO_TRIG; reg2 = JZ4740_GPIO_DIR; @@ -796,21 +1399,45 @@ static void irq_set_type(struct ingenic_gpio_chip *jzgc, switch (type) { case IRQ_TYPE_EDGE_RISING: - ingenic_gpio_set_bit(jzgc, reg2, offset, true); - ingenic_gpio_set_bit(jzgc, reg1, offset, true); + if (jzgc->jzpc->version >= ID_X1000) { + ingenic_gpio_shadow_set_bit(jzgc, reg2, offset, true); + ingenic_gpio_shadow_set_bit(jzgc, reg1, offset, true); + ingenic_gpio_shadow_set_bit_load(jzgc); + } else { + ingenic_gpio_set_bit(jzgc, reg2, offset, true); + ingenic_gpio_set_bit(jzgc, reg1, offset, true); + } break; case IRQ_TYPE_EDGE_FALLING: - ingenic_gpio_set_bit(jzgc, reg2, offset, false); - ingenic_gpio_set_bit(jzgc, reg1, offset, true); + if (jzgc->jzpc->version >= ID_X1000) { + ingenic_gpio_shadow_set_bit(jzgc, reg2, offset, false); + ingenic_gpio_shadow_set_bit(jzgc, reg1, offset, true); + ingenic_gpio_shadow_set_bit_load(jzgc); + } else { + ingenic_gpio_set_bit(jzgc, reg2, offset, false); + ingenic_gpio_set_bit(jzgc, reg1, offset, true); + } break; case IRQ_TYPE_LEVEL_HIGH: - ingenic_gpio_set_bit(jzgc, reg2, offset, true); - ingenic_gpio_set_bit(jzgc, reg1, offset, false); + if (jzgc->jzpc->version >= ID_X1000) { + ingenic_gpio_shadow_set_bit(jzgc, reg2, offset, true); + ingenic_gpio_shadow_set_bit(jzgc, reg1, offset, false); + ingenic_gpio_shadow_set_bit_load(jzgc); + } else { + ingenic_gpio_set_bit(jzgc, reg2, offset, true); + ingenic_gpio_set_bit(jzgc, reg1, offset, false); + } break; case IRQ_TYPE_LEVEL_LOW: default: - ingenic_gpio_set_bit(jzgc, reg2, offset, false); - ingenic_gpio_set_bit(jzgc, reg1, offset, false); + if (jzgc->jzpc->version >= ID_X1000) { + ingenic_gpio_shadow_set_bit(jzgc, reg2, offset, false); + ingenic_gpio_shadow_set_bit(jzgc, reg1, offset, false); + ingenic_gpio_shadow_set_bit_load(jzgc); + } else { + ingenic_gpio_set_bit(jzgc, reg2, offset, false); + ingenic_gpio_set_bit(jzgc, reg1, offset, false); + } break; } } @@ -837,8 +1464,8 @@ static void ingenic_gpio_irq_enable(struct irq_data *irqd) struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc); int irq = irqd->hwirq; - if (jzgc->jzpc->version >= ID_JZ4770) - ingenic_gpio_set_bit(jzgc, JZ4770_GPIO_INT, irq, true); + if (jzgc->jzpc->version >= ID_JZ4760) + ingenic_gpio_set_bit(jzgc, JZ4760_GPIO_INT, irq, true); else ingenic_gpio_set_bit(jzgc, JZ4740_GPIO_SELECT, irq, true); @@ -853,8 +1480,8 @@ static void ingenic_gpio_irq_disable(struct irq_data *irqd) ingenic_gpio_irq_mask(irqd); - if (jzgc->jzpc->version >= ID_JZ4770) - ingenic_gpio_set_bit(jzgc, JZ4770_GPIO_INT, irq, false); + if (jzgc->jzpc->version >= ID_JZ4760) + ingenic_gpio_set_bit(jzgc, JZ4760_GPIO_INT, irq, false); else ingenic_gpio_set_bit(jzgc, JZ4740_GPIO_SELECT, irq, false); } @@ -878,8 +1505,8 @@ static void ingenic_gpio_irq_ack(struct irq_data *irqd) irq_set_type(jzgc, irq, IRQ_TYPE_EDGE_RISING); } - if (jzgc->jzpc->version >= ID_JZ4770) - ingenic_gpio_set_bit(jzgc, JZ4770_GPIO_FLAG, irq, false); + if (jzgc->jzpc->version >= ID_JZ4760) + ingenic_gpio_set_bit(jzgc, JZ4760_GPIO_FLAG, irq, false); else ingenic_gpio_set_bit(jzgc, JZ4740_GPIO_DATA, irq, true); } @@ -935,8 +1562,8 @@ static void ingenic_gpio_irq_handler(struct irq_desc *desc) chained_irq_enter(irq_chip, desc); - if (jzgc->jzpc->version >= ID_JZ4770) - flag = ingenic_gpio_read_reg(jzgc, JZ4770_GPIO_FLAG); + if (jzgc->jzpc->version >= ID_JZ4760) + flag = ingenic_gpio_read_reg(jzgc, JZ4760_GPIO_FLAG); else flag = ingenic_gpio_read_reg(jzgc, JZ4740_GPIO_FLAG); @@ -983,6 +1610,21 @@ static inline void ingenic_config_pin(struct ingenic_pinctrl *jzpc, (set ? REG_SET(reg) : REG_CLEAR(reg)), BIT(idx)); } +static inline void ingenic_shadow_config_pin(struct ingenic_pinctrl *jzpc, + unsigned int pin, u8 reg, bool set) +{ + unsigned int idx = pin % PINS_PER_GPIO_CHIP; + + regmap_write(jzpc->map, X1000_GPIO_PZ_BASE + + (set ? REG_SET(reg) : REG_CLEAR(reg)), BIT(idx)); +} + +static inline void ingenic_shadow_config_pin_load(struct ingenic_pinctrl *jzpc, + unsigned int pin) +{ + regmap_write(jzpc->map, X1000_GPIO_PZ_GID2LD, pin / PINS_PER_GPIO_CHIP); +} + static inline bool ingenic_get_pin_config(struct ingenic_pinctrl *jzpc, unsigned int pin, u8 reg) { @@ -1001,8 +1643,8 @@ static int ingenic_gpio_get_direction(struct gpio_chip *gc, unsigned int offset) struct ingenic_pinctrl *jzpc = jzgc->jzpc; unsigned int pin = gc->base + offset; - if (jzpc->version >= ID_JZ4770) - return ingenic_get_pin_config(jzpc, pin, JZ4770_GPIO_PAT1); + if (jzpc->version >= ID_JZ4760) + return ingenic_get_pin_config(jzpc, pin, JZ4760_GPIO_PAT1); if (ingenic_get_pin_config(jzpc, pin, JZ4740_GPIO_SELECT)) return true; @@ -1027,11 +1669,17 @@ static int ingenic_pinmux_set_pin_fn(struct ingenic_pinctrl *jzpc, dev_dbg(jzpc->dev, "set pin P%c%u to function %u\n", 'A' + offt, idx, func); - if (jzpc->version >= ID_JZ4770) { - ingenic_config_pin(jzpc, pin, JZ4770_GPIO_INT, false); + if (jzpc->version >= ID_X1000) { + ingenic_shadow_config_pin(jzpc, pin, JZ4760_GPIO_INT, false); + ingenic_shadow_config_pin(jzpc, pin, GPIO_MSK, false); + ingenic_shadow_config_pin(jzpc, pin, JZ4760_GPIO_PAT1, func & 0x2); + ingenic_shadow_config_pin(jzpc, pin, JZ4760_GPIO_PAT0, func & 0x1); + ingenic_shadow_config_pin_load(jzpc, pin); + } else if (jzpc->version >= ID_JZ4760) { + ingenic_config_pin(jzpc, pin, JZ4760_GPIO_INT, false); ingenic_config_pin(jzpc, pin, GPIO_MSK, false); - ingenic_config_pin(jzpc, pin, JZ4770_GPIO_PAT1, func & 0x2); - ingenic_config_pin(jzpc, pin, JZ4770_GPIO_PAT0, func & 0x1); + ingenic_config_pin(jzpc, pin, JZ4760_GPIO_PAT1, func & 0x2); + ingenic_config_pin(jzpc, pin, JZ4760_GPIO_PAT0, func & 0x1); } else { ingenic_config_pin(jzpc, pin, JZ4740_GPIO_FUNC, true); ingenic_config_pin(jzpc, pin, JZ4740_GPIO_TRIG, func & 0x2); @@ -1080,10 +1728,15 @@ static int ingenic_pinmux_gpio_set_direction(struct pinctrl_dev *pctldev, dev_dbg(pctldev->dev, "set pin P%c%u to %sput\n", 'A' + offt, idx, input ? "in" : "out"); - if (jzpc->version >= ID_JZ4770) { - ingenic_config_pin(jzpc, pin, JZ4770_GPIO_INT, false); + if (jzpc->version >= ID_X1000) { + ingenic_shadow_config_pin(jzpc, pin, JZ4760_GPIO_INT, false); + ingenic_shadow_config_pin(jzpc, pin, GPIO_MSK, true); + ingenic_shadow_config_pin(jzpc, pin, JZ4760_GPIO_PAT1, input); + ingenic_shadow_config_pin_load(jzpc, pin); + } else if (jzpc->version >= ID_JZ4760) { + ingenic_config_pin(jzpc, pin, JZ4760_GPIO_INT, false); ingenic_config_pin(jzpc, pin, GPIO_MSK, true); - ingenic_config_pin(jzpc, pin, JZ4770_GPIO_PAT1, input); + ingenic_config_pin(jzpc, pin, JZ4760_GPIO_PAT1, input); } else { ingenic_config_pin(jzpc, pin, JZ4740_GPIO_SELECT, false); ingenic_config_pin(jzpc, pin, JZ4740_GPIO_DIR, !input); @@ -1110,8 +1763,8 @@ static int ingenic_pinconf_get(struct pinctrl_dev *pctldev, unsigned int offt = pin / PINS_PER_GPIO_CHIP; bool pull; - if (jzpc->version >= ID_JZ4770) - pull = !ingenic_get_pin_config(jzpc, pin, JZ4770_GPIO_PEN); + if (jzpc->version >= ID_JZ4760) + pull = !ingenic_get_pin_config(jzpc, pin, JZ4760_GPIO_PEN); else pull = !ingenic_get_pin_config(jzpc, pin, JZ4740_GPIO_PULL_DIS); @@ -1142,8 +1795,8 @@ static int ingenic_pinconf_get(struct pinctrl_dev *pctldev, static void ingenic_set_bias(struct ingenic_pinctrl *jzpc, unsigned int pin, bool enabled) { - if (jzpc->version >= ID_JZ4770) - ingenic_config_pin(jzpc, pin, JZ4770_GPIO_PEN, !enabled); + if (jzpc->version >= ID_JZ4760) + ingenic_config_pin(jzpc, pin, JZ4760_GPIO_PEN, !enabled); else ingenic_config_pin(jzpc, pin, JZ4740_GPIO_PULL_DIS, !enabled); } @@ -1263,15 +1916,22 @@ static const struct regmap_config ingenic_pinctrl_regmap_config = { static const struct of_device_id ingenic_pinctrl_of_match[] = { { .compatible = "ingenic,jz4740-pinctrl", .data = (void *) ID_JZ4740 }, { .compatible = "ingenic,jz4725b-pinctrl", .data = (void *)ID_JZ4725B }, + { .compatible = "ingenic,jz4760-pinctrl", .data = (void *) ID_JZ4760 }, + { .compatible = "ingenic,jz4760b-pinctrl", .data = (void *) ID_JZ4760B }, { .compatible = "ingenic,jz4770-pinctrl", .data = (void *) ID_JZ4770 }, { .compatible = "ingenic,jz4780-pinctrl", .data = (void *) ID_JZ4780 }, + { .compatible = "ingenic,x1000-pinctrl", .data = (void *) ID_X1000 }, + { .compatible = "ingenic,x1000e-pinctrl", .data = (void *) ID_X1000E }, + { .compatible = "ingenic,x1500-pinctrl", .data = (void *) ID_X1500 }, {}, }; static const struct of_device_id ingenic_gpio_of_match[] __initconst = { { .compatible = "ingenic,jz4740-gpio", }, + { .compatible = "ingenic,jz4760-gpio", }, { .compatible = "ingenic,jz4770-gpio", }, { .compatible = "ingenic,jz4780-gpio", }, + { .compatible = "ingenic,x1000-gpio", }, {}, }; @@ -1387,10 +2047,20 @@ static int __init ingenic_pinctrl_probe(struct platform_device *pdev) else jzpc->version = (enum jz_version)id->driver_data; - if (jzpc->version >= ID_JZ4780) + if (jzpc->version >= ID_X1500) + chip_info = &x1500_chip_info; + else if (jzpc->version >= ID_X1000E) + chip_info = &x1000e_chip_info; + else if (jzpc->version >= ID_X1000) + chip_info = &x1000_chip_info; + else if (jzpc->version >= ID_JZ4780) chip_info = &jz4780_chip_info; else if (jzpc->version >= ID_JZ4770) chip_info = &jz4770_chip_info; + else if (jzpc->version >= ID_JZ4760B) + chip_info = &jz4760b_chip_info; + else if (jzpc->version >= ID_JZ4760) + chip_info = &jz4760_chip_info; else if (jzpc->version >= ID_JZ4725B) chip_info = &jz4725b_chip_info; else @@ -1467,8 +2137,13 @@ static int __init ingenic_pinctrl_probe(struct platform_device *pdev) static const struct platform_device_id ingenic_pinctrl_ids[] = { { "jz4740-pinctrl", ID_JZ4740 }, { "jz4725b-pinctrl", ID_JZ4725B }, + { "jz4760-pinctrl", ID_JZ4760 }, + { "jz4760b-pinctrl", ID_JZ4760B }, { "jz4770-pinctrl", ID_JZ4770 }, { "jz4780-pinctrl", ID_JZ4780 }, + { "x1000-pinctrl", ID_X1000 }, + { "x1000e-pinctrl", ID_X1000E }, + { "x1500-pinctrl", ID_X1500 }, {}, }; diff --git a/drivers/pinctrl/pinctrl-oxnas.c b/drivers/pinctrl/pinctrl-oxnas.c index b4edbe0d9a73..55488ca246f1 100644 --- a/drivers/pinctrl/pinctrl-oxnas.c +++ b/drivers/pinctrl/pinctrl-oxnas.c @@ -902,7 +902,6 @@ static int oxnas_ox810se_pinconf_set(struct pinctrl_dev *pctldev, struct oxnas_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); struct oxnas_gpio_bank *bank = pctl_to_bank(pctl, pin); unsigned int param; - u32 arg; unsigned int i; u32 offset = pin - bank->gpio_chip.base; u32 mask = BIT(offset); @@ -912,7 +911,6 @@ static int oxnas_ox810se_pinconf_set(struct pinctrl_dev *pctldev, for (i = 0; i < num_configs; i++) { param = pinconf_to_config_param(configs[i]); - arg = pinconf_to_config_argument(configs[i]); switch (param) { case PIN_CONFIG_BIAS_PULL_UP: @@ -941,7 +939,6 @@ static int oxnas_ox820_pinconf_set(struct pinctrl_dev *pctldev, struct oxnas_gpio_bank *bank = pctl_to_bank(pctl, pin); unsigned int bank_offset = (bank->id ? PINMUX_820_BANK_OFFSET : 0); unsigned int param; - u32 arg; unsigned int i; u32 offset = pin - bank->gpio_chip.base; u32 mask = BIT(offset); @@ -951,7 +948,6 @@ static int oxnas_ox820_pinconf_set(struct pinctrl_dev *pctldev, for (i = 0; i < num_configs; i++) { param = pinconf_to_config_param(configs[i]); - arg = pinconf_to_config_argument(configs[i]); switch (param) { case PIN_CONFIG_BIAS_PULL_UP: @@ -1229,10 +1225,8 @@ static int oxnas_gpio_probe(struct platform_device *pdev) return PTR_ERR(bank->reg_base); irq = platform_get_irq(pdev, 0); - if (irq < 0) { - dev_err(&pdev->dev, "irq get failed\n"); + if (irq < 0) return irq; - } bank->id = id; bank->gpio_chip.parent = &pdev->dev; diff --git a/drivers/pinctrl/pinctrl-pic32.c b/drivers/pinctrl/pinctrl-pic32.c index 6dc98e22f9f5..e7f6dd5ab578 100644 --- a/drivers/pinctrl/pinctrl-pic32.c +++ b/drivers/pinctrl/pinctrl-pic32.c @@ -2222,10 +2222,8 @@ static int pic32_gpio_probe(struct platform_device *pdev) return PTR_ERR(bank->reg_base); irq = platform_get_irq(pdev, 0); - if (irq < 0) { - dev_err(&pdev->dev, "irq get failed\n"); + if (irq < 0) return irq; - } bank->clk = devm_clk_get(&pdev->dev, NULL); if (IS_ERR(bank->clk)) { diff --git a/drivers/pinctrl/pinctrl-rk805.c b/drivers/pinctrl/pinctrl-rk805.c index a8459cafd4ea..26adbe9d6d42 100644 --- a/drivers/pinctrl/pinctrl-rk805.c +++ b/drivers/pinctrl/pinctrl-rk805.c @@ -197,7 +197,7 @@ static int rk805_gpio_get_direction(struct gpio_chip *chip, unsigned int offset) return !(val & pci->pin_cfg[offset].dir_msk); } -static struct gpio_chip rk805_gpio_chip = { +static const struct gpio_chip rk805_gpio_chip = { .label = "rk805-gpio", .request = gpiochip_generic_request, .free = gpiochip_generic_free, @@ -404,7 +404,7 @@ static const struct pinconf_ops rk805_pinconf_ops = { .pin_config_set = rk805_pinconf_set, }; -static struct pinctrl_desc rk805_pinctrl_desc = { +static const struct pinctrl_desc rk805_pinctrl_desc = { .name = "rk805-pinctrl", .pctlops = &rk805_pinctrl_ops, .pmxops = &rk805_pinmux_ops, diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c index 62a622159006..dc0bbf198cbc 100644 --- a/drivers/pinctrl/pinctrl-rockchip.c +++ b/drivers/pinctrl/pinctrl-rockchip.c @@ -2792,6 +2792,7 @@ static int rockchip_gpio_set_config(struct gpio_chip *gc, unsigned int offset, * still return -ENOTSUPP as before, to make sure the caller * of gpiod_set_debounce won't change its behaviour. */ + return -ENOTSUPP; default: return -ENOTSUPP; } diff --git a/drivers/pinctrl/pinctrl-rza1.c b/drivers/pinctrl/pinctrl-rza1.c index 021e37b7689e..017fc6b3e27e 100644 --- a/drivers/pinctrl/pinctrl-rza1.c +++ b/drivers/pinctrl/pinctrl-rza1.c @@ -866,8 +866,10 @@ static int rza1_dt_node_pin_count(struct device_node *np) npins = 0; for_each_child_of_node(np, child) { of_pins = of_find_property(child, "pinmux", NULL); - if (!of_pins) + if (!of_pins) { + of_node_put(child); return -EINVAL; + } npins += of_pins->length / sizeof(u32); } @@ -1025,8 +1027,10 @@ static int rza1_dt_node_to_map(struct pinctrl_dev *pctldev, for_each_child_of_node(np, child) { ret = rza1_parse_pinmux_node(rza1_pctl, child, mux_conf, grpin); - if (ret < 0) + if (ret < 0) { + of_node_put(child); return ret; + } grpin += ret; mux_conf += ret; @@ -1272,8 +1276,10 @@ static int rza1_gpio_register(struct rza1_pinctrl *rza1_pctl) ret = rza1_parse_gpiochip(rza1_pctl, child, &gpio_chips[i], &gpio_ranges[i]); - if (ret) + if (ret) { + of_node_put(child); return ret; + } ++i; } @@ -1359,7 +1365,6 @@ static int rza1_pinctrl_register(struct rza1_pinctrl *rza1_pctl) static int rza1_pinctrl_probe(struct platform_device *pdev) { struct rza1_pinctrl *rza1_pctl; - struct resource *res; int ret; rza1_pctl = devm_kzalloc(&pdev->dev, sizeof(*rza1_pctl), GFP_KERNEL); @@ -1368,8 +1373,7 @@ static int rza1_pinctrl_probe(struct platform_device *pdev) rza1_pctl->dev = &pdev->dev; - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - rza1_pctl->base = devm_ioremap_resource(&pdev->dev, res); + rza1_pctl->base = devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(rza1_pctl->base)) return PTR_ERR(rza1_pctl->base); diff --git a/drivers/pinctrl/pinctrl-rza2.c b/drivers/pinctrl/pinctrl-rza2.c index 5b951c7422cc..3be1d833bf25 100644 --- a/drivers/pinctrl/pinctrl-rza2.c +++ b/drivers/pinctrl/pinctrl-rza2.c @@ -11,7 +11,8 @@ */ #include <linux/bitops.h> -#include <linux/gpio.h> +#include <linux/gpio/driver.h> +#include <linux/io.h> #include <linux/module.h> #include <linux/of_device.h> #include <linux/pinctrl/pinmux.h> @@ -115,7 +116,7 @@ static void rza2_pin_to_gpio(void __iomem *pfc_base, unsigned int offset, mask16 = RZA2_PDR_MASK << (pin * 2); reg16 &= ~mask16; - if (dir == GPIOF_DIR_IN) + if (dir) reg16 |= RZA2_PDR_INPUT << (pin * 2); /* pin as input */ else reg16 |= RZA2_PDR_OUTPUT << (pin * 2); /* pin as output */ @@ -134,18 +135,18 @@ static int rza2_chip_get_direction(struct gpio_chip *chip, unsigned int offset) reg16 = (reg16 >> (pin * 2)) & RZA2_PDR_MASK; if (reg16 == RZA2_PDR_OUTPUT) - return GPIOF_DIR_OUT; + return 0; if (reg16 == RZA2_PDR_INPUT) - return GPIOF_DIR_IN; + return 1; /* * This GPIO controller has a default Hi-Z state that is not input or * output, so force the pin to input now. */ - rza2_pin_to_gpio(priv->base, offset, GPIOF_DIR_IN); + rza2_pin_to_gpio(priv->base, offset, 1); - return GPIOF_DIR_IN; + return 1; } static int rza2_chip_direction_input(struct gpio_chip *chip, @@ -153,7 +154,7 @@ static int rza2_chip_direction_input(struct gpio_chip *chip, { struct rza2_pinctrl_priv *priv = gpiochip_get_data(chip); - rza2_pin_to_gpio(priv->base, offset, GPIOF_DIR_IN); + rza2_pin_to_gpio(priv->base, offset, 1); return 0; } @@ -191,7 +192,7 @@ static int rza2_chip_direction_output(struct gpio_chip *chip, struct rza2_pinctrl_priv *priv = gpiochip_get_data(chip); rza2_chip_set(chip, offset, val); - rza2_pin_to_gpio(priv->base, offset, GPIOF_DIR_OUT); + rza2_pin_to_gpio(priv->base, offset, 0); return 0; } diff --git a/drivers/pinctrl/pinctrl-rzn1.c b/drivers/pinctrl/pinctrl-rzn1.c index cc0e5aa9128a..0f6f8a10a53a 100644 --- a/drivers/pinctrl/pinctrl-rzn1.c +++ b/drivers/pinctrl/pinctrl-rzn1.c @@ -412,8 +412,10 @@ static int rzn1_dt_node_to_map(struct pinctrl_dev *pctldev, for_each_child_of_node(np, child) { ret = rzn1_dt_node_to_map_one(pctldev, child, map, num_maps); - if (ret < 0) + if (ret < 0) { + of_node_put(child); return ret; + } } return 0; @@ -792,8 +794,10 @@ static int rzn1_pinctrl_parse_functions(struct device_node *np, grp = &ipctl->groups[ipctl->ngroups]; grp->func = func->name; ret = rzn1_pinctrl_parse_groups(child, grp, ipctl); - if (ret < 0) + if (ret < 0) { + of_node_put(child); return ret; + } i++; ipctl->ngroups++; } @@ -838,8 +842,10 @@ static int rzn1_pinctrl_probe_dt(struct platform_device *pdev, for_each_child_of_node(np, child) { ret = rzn1_pinctrl_parse_functions(child, ipctl, i++); - if (ret < 0) + if (ret < 0) { + of_node_put(child); return ret; + } } return 0; diff --git a/drivers/pinctrl/pinctrl-st.c b/drivers/pinctrl/pinctrl-st.c index b9688ea548da..00db8b9efb2c 100644 --- a/drivers/pinctrl/pinctrl-st.c +++ b/drivers/pinctrl/pinctrl-st.c @@ -12,8 +12,9 @@ #include <linux/io.h> #include <linux/of.h> #include <linux/of_irq.h> -#include <linux/of_gpio.h> +#include <linux/of_gpio.h> /* of_get_named_gpio() */ #include <linux/of_address.h> +#include <linux/gpio/driver.h> #include <linux/regmap.h> #include <linux/mfd/syscon.h> #include <linux/pinctrl/pinctrl.h> @@ -1262,8 +1263,10 @@ static int st_pctl_parse_functions(struct device_node *np, grp = &info->groups[*grp_index]; *grp_index += 1; ret = st_pctl_dt_parse_groups(child, grp, info, i++); - if (ret) + if (ret) { + of_node_put(child); return ret; + } } dev_info(info->dev, "Function[%d\t name:%s,\tgroups:%d]\n", index, func->name, func->ngroups); @@ -1623,8 +1626,10 @@ static int st_pctl_probe_dt(struct platform_device *pdev, if (of_property_read_bool(child, "gpio-controller")) { const char *bank_name = NULL; ret = st_gpiolib_register_bank(info, bank, child); - if (ret) + if (ret) { + of_node_put(child); return ret; + } k = info->banks[bank].range.pin_base; bank_name = info->banks[bank].range.name; @@ -1641,6 +1646,7 @@ static int st_pctl_probe_dt(struct platform_device *pdev, i++, &grp_index); if (ret) { dev_err(&pdev->dev, "No functions found.\n"); + of_node_put(child); return ret; } } diff --git a/drivers/pinctrl/pinctrl-stmfx.c b/drivers/pinctrl/pinctrl-stmfx.c index dd5aa9a2dfe5..974973777395 100644 --- a/drivers/pinctrl/pinctrl-stmfx.c +++ b/drivers/pinctrl/pinctrl-stmfx.c @@ -296,29 +296,29 @@ static int stmfx_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, switch (param) { case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT: case PIN_CONFIG_BIAS_DISABLE: + case PIN_CONFIG_DRIVE_PUSH_PULL: + ret = stmfx_pinconf_set_type(pctl, pin, 0); + if (ret) + return ret; + break; case PIN_CONFIG_BIAS_PULL_DOWN: + ret = stmfx_pinconf_set_type(pctl, pin, 1); + if (ret) + return ret; ret = stmfx_pinconf_set_pupd(pctl, pin, 0); if (ret) return ret; break; case PIN_CONFIG_BIAS_PULL_UP: - ret = stmfx_pinconf_set_pupd(pctl, pin, 1); + ret = stmfx_pinconf_set_type(pctl, pin, 1); if (ret) return ret; - break; - case PIN_CONFIG_DRIVE_OPEN_DRAIN: - if (!dir) - ret = stmfx_pinconf_set_type(pctl, pin, 1); - else - ret = stmfx_pinconf_set_type(pctl, pin, 0); + ret = stmfx_pinconf_set_pupd(pctl, pin, 1); if (ret) return ret; break; - case PIN_CONFIG_DRIVE_PUSH_PULL: - if (!dir) - ret = stmfx_pinconf_set_type(pctl, pin, 0); - else - ret = stmfx_pinconf_set_type(pctl, pin, 1); + case PIN_CONFIG_DRIVE_OPEN_DRAIN: + ret = stmfx_pinconf_set_type(pctl, pin, 1); if (ret) return ret; break; @@ -620,10 +620,8 @@ static int stmfx_pinctrl_probe(struct platform_device *pdev) } irq = platform_get_irq(pdev, 0); - if (irq <= 0) { - dev_err(pctl->dev, "failed to get irq\n"); + if (irq <= 0) return -ENXIO; - } mutex_init(&pctl->lock); diff --git a/drivers/pinctrl/pinctrl-xway.c b/drivers/pinctrl/pinctrl-xway.c index 376222d0e5c5..913d38f29b73 100644 --- a/drivers/pinctrl/pinctrl-xway.c +++ b/drivers/pinctrl/pinctrl-xway.c @@ -1731,13 +1731,11 @@ static int pinmux_xway_probe(struct platform_device *pdev) return -ENOMEM; for (i = 0; i < xway_chip.ngpio; i++) { - /* strlen("ioXY") + 1 = 5 */ - char *name = devm_kzalloc(&pdev->dev, 5, GFP_KERNEL); + char *name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "io%d", i); if (!name) return -ENOMEM; - snprintf(name, 5, "io%d", i); xway_info.pads[i].number = GPIO0 + i; xway_info.pads[i].name = name; } diff --git a/drivers/pinctrl/pinmux.c b/drivers/pinctrl/pinmux.c index 020e54f843f9..e914f6efd39e 100644 --- a/drivers/pinctrl/pinmux.c +++ b/drivers/pinctrl/pinmux.c @@ -71,6 +71,30 @@ int pinmux_validate_map(const struct pinctrl_map *map, int i) } /** + * pinmux_can_be_used_for_gpio() - check if a specific pin + * is either muxed to a different function or used as gpio. + * + * @pin: the pin number in the global pin space + * + * Controllers not defined as strict will always return true, + * menaning that the gpio can be used. + */ +bool pinmux_can_be_used_for_gpio(struct pinctrl_dev *pctldev, unsigned pin) +{ + struct pin_desc *desc = pin_desc_get(pctldev, pin); + const struct pinmux_ops *ops = pctldev->desc->pmxops; + + /* Can't inspect pin, assume it can be used */ + if (!desc) + return true; + + if (ops->strict && desc->mux_usecount) + return false; + + return !(ops->strict && !!desc->gpio_owner); +} + +/** * pin_request() - request a single pin to be muxed in, typically for GPIO * @pin: the pin number in the global pin space * @owner: a representation of the owner of this pin; typically the device diff --git a/drivers/pinctrl/pinmux.h b/drivers/pinctrl/pinmux.h index 794cb3a003ff..78c3a31be882 100644 --- a/drivers/pinctrl/pinmux.h +++ b/drivers/pinctrl/pinmux.h @@ -15,6 +15,8 @@ int pinmux_check_ops(struct pinctrl_dev *pctldev); int pinmux_validate_map(const struct pinctrl_map *map, int i); +bool pinmux_can_be_used_for_gpio(struct pinctrl_dev *pctldev, unsigned pin); + int pinmux_request_gpio(struct pinctrl_dev *pctldev, struct pinctrl_gpio_range *range, unsigned pin, unsigned gpio); @@ -42,6 +44,12 @@ static inline int pinmux_validate_map(const struct pinctrl_map *map, int i) return 0; } +static inline bool pinmux_can_be_used_for_gpio(struct pinctrl_dev *pctldev, + unsigned pin) +{ + return true; +} + static inline int pinmux_request_gpio(struct pinctrl_dev *pctldev, struct pinctrl_gpio_range *range, unsigned pin, unsigned gpio) diff --git a/drivers/pinctrl/qcom/Kconfig b/drivers/pinctrl/qcom/Kconfig index fa2c87821401..32fc2458b8eb 100644 --- a/drivers/pinctrl/qcom/Kconfig +++ b/drivers/pinctrl/qcom/Kconfig @@ -159,6 +159,15 @@ config PINCTRL_QCOM_SSBI_PMIC which are using SSBI for communication with SoC. Example PMIC's devices are pm8058 and pm8921. +config PINCTRL_SC7180 + tristate "Qualcomm Technologies Inc SC7180 pin controller driver" + depends on GPIOLIB && OF + select PINCTRL_MSM + help + This is the pinctrl, pinmux, pinconf and gpiolib driver for the + Qualcomm Technologies Inc TLMM block found on the Qualcomm + Technologies Inc SC7180 platform. + config PINCTRL_SDM660 tristate "Qualcomm Technologies Inc SDM660 pin controller driver" depends on GPIOLIB && OF diff --git a/drivers/pinctrl/qcom/Makefile b/drivers/pinctrl/qcom/Makefile index ebe906872272..f8bb0c265381 100644 --- a/drivers/pinctrl/qcom/Makefile +++ b/drivers/pinctrl/qcom/Makefile @@ -20,6 +20,7 @@ obj-$(CONFIG_PINCTRL_QCOM_SPMI_PMIC) += pinctrl-spmi-gpio.o obj-$(CONFIG_PINCTRL_QCOM_SPMI_PMIC) += pinctrl-spmi-mpp.o obj-$(CONFIG_PINCTRL_QCOM_SSBI_PMIC) += pinctrl-ssbi-gpio.o obj-$(CONFIG_PINCTRL_QCOM_SSBI_PMIC) += pinctrl-ssbi-mpp.o +obj-$(CONFIG_PINCTRL_SC7180) += pinctrl-sc7180.o obj-$(CONFIG_PINCTRL_SDM660) += pinctrl-sdm660.o obj-$(CONFIG_PINCTRL_SDM845) += pinctrl-sdm845.o obj-$(CONFIG_PINCTRL_SM8150) += pinctrl-sm8150.o diff --git a/drivers/pinctrl/qcom/pinctrl-msm.c b/drivers/pinctrl/qcom/pinctrl-msm.c index b8a1c43222f8..763da0be10d6 100644 --- a/drivers/pinctrl/qcom/pinctrl-msm.c +++ b/drivers/pinctrl/qcom/pinctrl-msm.c @@ -618,8 +618,7 @@ static int msm_gpio_init_valid_mask(struct gpio_chip *gc, } /* The number of GPIOs in the ACPI tables */ - len = ret = device_property_read_u16_array(pctrl->dev, "gpios", NULL, - 0); + len = ret = device_property_count_u16(pctrl->dev, "gpios"); if (ret < 0) return 0; @@ -996,12 +995,13 @@ static bool msm_gpio_needs_valid_mask(struct msm_pinctrl *pctrl) if (pctrl->soc->reserved_gpios) return true; - return device_property_read_u16_array(pctrl->dev, "gpios", NULL, 0) > 0; + return device_property_count_u16(pctrl->dev, "gpios") > 0; } static int msm_gpio_init(struct msm_pinctrl *pctrl) { struct gpio_chip *chip; + struct gpio_irq_chip *girq; int ret; unsigned ngpio = pctrl->soc->ngpios; @@ -1028,6 +1028,18 @@ static int msm_gpio_init(struct msm_pinctrl *pctrl) pctrl->irq_chip.irq_request_resources = msm_gpio_irq_reqres; pctrl->irq_chip.irq_release_resources = msm_gpio_irq_relres; + girq = &chip->irq; + girq->chip = &pctrl->irq_chip; + girq->parent_handler = msm_gpio_irq_handler; + girq->num_parents = 1; + girq->parents = devm_kcalloc(pctrl->dev, 1, sizeof(*girq->parents), + GFP_KERNEL); + if (!girq->parents) + return -ENOMEM; + girq->default_type = IRQ_TYPE_NONE; + girq->handler = handle_bad_irq; + girq->parents[0] = pctrl->irq; + ret = gpiochip_add_data(&pctrl->chip, pctrl); if (ret) { dev_err(pctrl->dev, "Failed register gpiochip\n"); @@ -1054,20 +1066,6 @@ static int msm_gpio_init(struct msm_pinctrl *pctrl) } } - ret = gpiochip_irqchip_add(chip, - &pctrl->irq_chip, - 0, - handle_edge_irq, - IRQ_TYPE_NONE); - if (ret) { - dev_err(pctrl->dev, "Failed to add irqchip to gpiochip\n"); - gpiochip_remove(&pctrl->chip); - return -ENOSYS; - } - - gpiochip_set_chained_irqchip(chip, &pctrl->irq_chip, pctrl->irq, - msm_gpio_irq_handler); - return 0; } @@ -1161,10 +1159,8 @@ int msm_pinctrl_probe(struct platform_device *pdev, msm_pinctrl_setup_pm_reset(pctrl); pctrl->irq = platform_get_irq(pdev, 0); - if (pctrl->irq < 0) { - dev_err(&pdev->dev, "No interrupt defined for msmgpio\n"); + if (pctrl->irq < 0) return pctrl->irq; - } pctrl->desc.owner = THIS_MODULE; pctrl->desc.pctlops = &msm_pinctrl_ops; diff --git a/drivers/pinctrl/qcom/pinctrl-msm8998.c b/drivers/pinctrl/qcom/pinctrl-msm8998.c index 00d7b94bc3f1..a05f41fe2706 100644 --- a/drivers/pinctrl/qcom/pinctrl-msm8998.c +++ b/drivers/pinctrl/qcom/pinctrl-msm8998.c @@ -581,16 +581,8 @@ enum msm8998_functions { msm_mux_tgu_ch1, msm_mux_tsense_pwm1, msm_mux_tsense_pwm2, - msm_mux_tsif1_clk, - msm_mux_tsif1_data, - msm_mux_tsif1_en, - msm_mux_tsif1_error, - msm_mux_tsif1_sync, - msm_mux_tsif2_clk, - msm_mux_tsif2_data, - msm_mux_tsif2_en, - msm_mux_tsif2_error, - msm_mux_tsif2_sync, + msm_mux_tsif0, + msm_mux_tsif1, msm_mux_uim1_clk, msm_mux_uim1_data, msm_mux_uim1_present, @@ -692,9 +684,6 @@ static const char * const atest_usb13_groups[] = { static const char * const bimc_dte1_groups[] = { "gpio8", "gpio10", }; -static const char * const tsif1_sync_groups[] = { - "gpio9", -}; static const char * const wlan1_adc0_groups[] = { "gpio9", }; @@ -863,9 +852,6 @@ static const char * const lpass_slimbus_groups[] = { static const char * const sd_write_groups[] = { "gpio40", }; -static const char * const tsif1_error_groups[] = { - "gpio40", -}; static const char * const blsp_spi6_groups[] = { "gpio41", "gpio42", "gpio43", "gpio44", }; @@ -1048,11 +1034,8 @@ static const char * const blsp_uim2_b_groups[] = { static const char * const blsp_i2c5_groups[] = { "gpio87", "gpio88", }; -static const char * const tsif1_clk_groups[] = { - "gpio89", -}; -static const char * const tsif1_en_groups[] = { - "gpio90", +static const char * const tsif0_groups[] = { + "gpio9", "gpio40", "gpio89", "gpio90", "gpio91", }; static const char * const mdp_vsync0_groups[] = { "gpio90", @@ -1075,17 +1058,14 @@ static const char * const tgu_ch0_groups[] = { static const char * const qdss_cti1_b_groups[] = { "gpio90", "gpio91", }; -static const char * const tsif1_data_groups[] = { - "gpio91", -}; static const char * const sdc4_cmd_groups[] = { "gpio91", }; static const char * const tgu_ch1_groups[] = { "gpio91", }; -static const char * const tsif2_error_groups[] = { - "gpio92", +static const char * const tsif1_groups[] = { + "gpio92", "gpio93", "gpio94", "gpio95", "gpio96", }; static const char * const sdc43_groups[] = { "gpio92", @@ -1093,30 +1073,18 @@ static const char * const sdc43_groups[] = { static const char * const vfr_1_groups[] = { "gpio92", }; -static const char * const tsif2_clk_groups[] = { - "gpio93", -}; static const char * const sdc4_clk_groups[] = { "gpio93", }; -static const char * const tsif2_en_groups[] = { - "gpio94", -}; static const char * const sdc42_groups[] = { "gpio94", }; static const char * const sd_card_groups[] = { "gpio95", }; -static const char * const tsif2_data_groups[] = { - "gpio95", -}; static const char * const sdc41_groups[] = { "gpio95", }; -static const char * const tsif2_sync_groups[] = { - "gpio96", -}; static const char * const sdc40_groups[] = { "gpio96", }; @@ -1355,16 +1323,8 @@ static const struct msm_function msm8998_functions[] = { FUNCTION(tgu_ch1), FUNCTION(tsense_pwm1), FUNCTION(tsense_pwm2), - FUNCTION(tsif1_clk), - FUNCTION(tsif1_data), - FUNCTION(tsif1_en), - FUNCTION(tsif1_error), - FUNCTION(tsif1_sync), - FUNCTION(tsif2_clk), - FUNCTION(tsif2_data), - FUNCTION(tsif2_en), - FUNCTION(tsif2_error), - FUNCTION(tsif2_sync), + FUNCTION(tsif0), + FUNCTION(tsif1), FUNCTION(uim1_clk), FUNCTION(uim1_data), FUNCTION(uim1_present), @@ -1396,7 +1356,7 @@ static const struct msm_pingroup msm8998_groups[] = { PINGROUP(6, WEST, blsp_spi8, blsp_uart8_a, blsp_i2c8, _, _, _, _, _, _), PINGROUP(7, WEST, blsp_spi8, blsp_uart8_a, blsp_i2c8, ddr_bist, _, atest_tsens2, atest_usb1, _, _), PINGROUP(8, EAST, blsp_spi4, blsp_uart1_b, blsp_uim1_b, _, ddr_bist, _, wlan1_adc1, atest_usb13, bimc_dte1), - PINGROUP(9, EAST, blsp_spi4, blsp_uart1_b, blsp_uim1_b, tsif1_sync, ddr_bist, _, wlan1_adc0, atest_usb12, bimc_dte0), + PINGROUP(9, EAST, blsp_spi4, blsp_uart1_b, blsp_uim1_b, tsif0, ddr_bist, _, wlan1_adc0, atest_usb12, bimc_dte0), PINGROUP(10, EAST, mdp_vsync_a, blsp_spi4, blsp_uart1_b, blsp_i2c4, ddr_bist, atest_gpsadc1, wlan2_adc1, atest_usb11, bimc_dte1), PINGROUP(11, EAST, mdp_vsync_a, edp_lcd, blsp_spi4, blsp_uart1_b, blsp_i2c4, dbg_out, atest_gpsadc0, wlan2_adc0, atest_usb10), PINGROUP(12, EAST, mdp_vsync, m_voc, _, _, _, _, _, _, _), @@ -1427,7 +1387,7 @@ static const struct msm_pingroup msm8998_groups[] = { PINGROUP(37, NORTH, agera_pll, _, _, _, _, _, _, _, _), PINGROUP(38, WEST, usb_phy, _, _, _, _, _, _, _, _), PINGROUP(39, WEST, lpass_slimbus, _, _, _, _, _, _, _, _), - PINGROUP(40, EAST, sd_write, tsif1_error, _, _, _, _, _, _, _), + PINGROUP(40, EAST, sd_write, tsif0, _, _, _, _, _, _, _), PINGROUP(41, EAST, blsp_spi6, blsp_uart3_b, blsp_uim3_b, _, qdss, _, _, _, _), PINGROUP(42, EAST, blsp_spi6, blsp_uart3_b, blsp_uim3_b, _, qdss, _, _, _, _), PINGROUP(43, EAST, blsp_spi6, blsp_uart3_b, blsp_i2c6, _, qdss, _, _, _, _), @@ -1476,14 +1436,14 @@ static const struct msm_pingroup msm8998_groups[] = { PINGROUP(86, EAST, blsp_spi5, blsp_uart2_b, blsp_uim2_b, _, _, _, _, _, _), PINGROUP(87, EAST, blsp_spi5, blsp_uart2_b, blsp_i2c5, _, _, _, _, _, _), PINGROUP(88, EAST, blsp_spi5, blsp_uart2_b, blsp_i2c5, _, _, _, _, _, _), - PINGROUP(89, EAST, tsif1_clk, phase_flag, _, _, _, _, _, _, _), - PINGROUP(90, EAST, tsif1_en, mdp_vsync0, mdp_vsync1, mdp_vsync2, mdp_vsync3, blsp1_spi, tgu_ch0, qdss_cti1_b, _), - PINGROUP(91, EAST, tsif1_data, sdc4_cmd, tgu_ch1, phase_flag, qdss_cti1_b, _, _, _, _), - PINGROUP(92, EAST, tsif2_error, sdc43, vfr_1, phase_flag, _, _, _, _, _), - PINGROUP(93, EAST, tsif2_clk, sdc4_clk, _, qdss, _, _, _, _, _), - PINGROUP(94, EAST, tsif2_en, sdc42, _, _, _, _, _, _, _), - PINGROUP(95, EAST, tsif2_data, sdc41, _, _, _, _, _, _, _), - PINGROUP(96, EAST, tsif2_sync, sdc40, phase_flag, _, _, _, _, _, _), + PINGROUP(89, EAST, tsif0, phase_flag, _, _, _, _, _, _, _), + PINGROUP(90, EAST, tsif0, mdp_vsync0, mdp_vsync1, mdp_vsync2, mdp_vsync3, blsp1_spi, tgu_ch0, qdss_cti1_b, _), + PINGROUP(91, EAST, tsif0, sdc4_cmd, tgu_ch1, phase_flag, qdss_cti1_b, _, _, _, _), + PINGROUP(92, EAST, tsif1, sdc43, vfr_1, phase_flag, _, _, _, _, _), + PINGROUP(93, EAST, tsif1, sdc4_clk, _, qdss, _, _, _, _, _), + PINGROUP(94, EAST, tsif1, sdc42, _, _, _, _, _, _, _), + PINGROUP(95, EAST, tsif1, sdc41, _, _, _, _, _, _, _), + PINGROUP(96, EAST, tsif1, sdc40, phase_flag, _, _, _, _, _, _), PINGROUP(97, WEST, _, mdp_vsync_b, ldo_en, _, _, _, _, _, _), PINGROUP(98, WEST, _, mdp_vsync_b, ldo_update, _, _, _, _, _, _), PINGROUP(99, WEST, _, _, _, _, _, _, _, _, _), diff --git a/drivers/pinctrl/qcom/pinctrl-qdf2xxx.c b/drivers/pinctrl/qcom/pinctrl-qdf2xxx.c index 5da5dd51542c..43bd15f16377 100644 --- a/drivers/pinctrl/qcom/pinctrl-qdf2xxx.c +++ b/drivers/pinctrl/qcom/pinctrl-qdf2xxx.c @@ -52,7 +52,7 @@ static int qdf2xxx_pinctrl_probe(struct platform_device *pdev) } /* The number of GPIOs in the approved list */ - ret = device_property_read_u8_array(&pdev->dev, "gpios", NULL, 0); + ret = device_property_count_u8(&pdev->dev, "gpios"); if (ret < 0) { dev_err(&pdev->dev, "missing 'gpios' property\n"); return ret; diff --git a/drivers/pinctrl/qcom/pinctrl-sc7180.c b/drivers/pinctrl/qcom/pinctrl-sc7180.c new file mode 100644 index 000000000000..6399c8a2bc22 --- /dev/null +++ b/drivers/pinctrl/qcom/pinctrl-sc7180.c @@ -0,0 +1,1146 @@ +// SPDX-License-Identifier: GPL-2.0 +// Copyright (c) 2019, The Linux Foundation. All rights reserved. + +#include <linux/module.h> +#include <linux/of.h> +#include <linux/platform_device.h> +#include <linux/pinctrl/pinctrl.h> + +#include "pinctrl-msm.h" + +static const char * const sc7180_tiles[] = { + "north", + "south", + "west", +}; + +enum { + NORTH, + SOUTH, + WEST +}; + +#define FUNCTION(fname) \ + [msm_mux_##fname] = { \ + .name = #fname, \ + .groups = fname##_groups, \ + .ngroups = ARRAY_SIZE(fname##_groups), \ + } + +#define PINGROUP(id, _tile, f1, f2, f3, f4, f5, f6, f7, f8, f9) \ + { \ + .name = "gpio" #id, \ + .pins = gpio##id##_pins, \ + .npins = ARRAY_SIZE(gpio##id##_pins), \ + .funcs = (int[]){ \ + msm_mux_gpio, /* gpio mode */ \ + msm_mux_##f1, \ + msm_mux_##f2, \ + msm_mux_##f3, \ + msm_mux_##f4, \ + msm_mux_##f5, \ + msm_mux_##f6, \ + msm_mux_##f7, \ + msm_mux_##f8, \ + msm_mux_##f9 \ + }, \ + .nfuncs = 10, \ + .ctl_reg = 0x1000 * id, \ + .io_reg = 0x1000 * id + 0x4, \ + .intr_cfg_reg = 0x1000 * id + 0x8, \ + .intr_status_reg = 0x1000 * id + 0xc, \ + .intr_target_reg = 0x1000 * id + 0x8, \ + .tile = _tile, \ + .mux_bit = 2, \ + .pull_bit = 0, \ + .drv_bit = 6, \ + .oe_bit = 9, \ + .in_bit = 0, \ + .out_bit = 1, \ + .intr_enable_bit = 0, \ + .intr_status_bit = 0, \ + .intr_target_bit = 5, \ + .intr_target_kpss_val = 3, \ + .intr_raw_status_bit = 4, \ + .intr_polarity_bit = 1, \ + .intr_detection_bit = 2, \ + .intr_detection_width = 2, \ + } + +#define SDC_QDSD_PINGROUP(pg_name, ctl, pull, drv) \ + { \ + .name = #pg_name, \ + .pins = pg_name##_pins, \ + .npins = ARRAY_SIZE(pg_name##_pins), \ + .ctl_reg = ctl, \ + .io_reg = 0, \ + .intr_cfg_reg = 0, \ + .intr_status_reg = 0, \ + .intr_target_reg = 0, \ + .mux_bit = -1, \ + .pull_bit = pull, \ + .drv_bit = drv, \ + .oe_bit = -1, \ + .in_bit = -1, \ + .out_bit = -1, \ + .intr_enable_bit = -1, \ + .intr_status_bit = -1, \ + .intr_target_bit = -1, \ + .intr_raw_status_bit = -1, \ + .intr_polarity_bit = -1, \ + .intr_detection_bit = -1, \ + .intr_detection_width = -1, \ + } + +#define UFS_RESET(pg_name, offset) \ + { \ + .name = #pg_name, \ + .pins = pg_name##_pins, \ + .npins = ARRAY_SIZE(pg_name##_pins), \ + .ctl_reg = offset, \ + .io_reg = offset + 0x4, \ + .intr_cfg_reg = 0, \ + .intr_status_reg = 0, \ + .intr_target_reg = 0, \ + .mux_bit = -1, \ + .pull_bit = 3, \ + .drv_bit = 0, \ + .oe_bit = -1, \ + .in_bit = -1, \ + .out_bit = 0, \ + .intr_enable_bit = -1, \ + .intr_status_bit = -1, \ + .intr_target_bit = -1, \ + .intr_raw_status_bit = -1, \ + .intr_polarity_bit = -1, \ + .intr_detection_bit = -1, \ + .intr_detection_width = -1, \ + } +static const struct pinctrl_pin_desc sc7180_pins[] = { + PINCTRL_PIN(0, "GPIO_0"), + PINCTRL_PIN(1, "GPIO_1"), + PINCTRL_PIN(2, "GPIO_2"), + PINCTRL_PIN(3, "GPIO_3"), + PINCTRL_PIN(4, "GPIO_4"), + PINCTRL_PIN(5, "GPIO_5"), + PINCTRL_PIN(6, "GPIO_6"), + PINCTRL_PIN(7, "GPIO_7"), + PINCTRL_PIN(8, "GPIO_8"), + PINCTRL_PIN(9, "GPIO_9"), + PINCTRL_PIN(10, "GPIO_10"), + PINCTRL_PIN(11, "GPIO_11"), + PINCTRL_PIN(12, "GPIO_12"), + PINCTRL_PIN(13, "GPIO_13"), + PINCTRL_PIN(14, "GPIO_14"), + PINCTRL_PIN(15, "GPIO_15"), + PINCTRL_PIN(16, "GPIO_16"), + PINCTRL_PIN(17, "GPIO_17"), + PINCTRL_PIN(18, "GPIO_18"), + PINCTRL_PIN(19, "GPIO_19"), + PINCTRL_PIN(20, "GPIO_20"), + PINCTRL_PIN(21, "GPIO_21"), + PINCTRL_PIN(22, "GPIO_22"), + PINCTRL_PIN(23, "GPIO_23"), + PINCTRL_PIN(24, "GPIO_24"), + PINCTRL_PIN(25, "GPIO_25"), + PINCTRL_PIN(26, "GPIO_26"), + PINCTRL_PIN(27, "GPIO_27"), + PINCTRL_PIN(28, "GPIO_28"), + PINCTRL_PIN(29, "GPIO_29"), + PINCTRL_PIN(30, "GPIO_30"), + PINCTRL_PIN(31, "GPIO_31"), + PINCTRL_PIN(32, "GPIO_32"), + PINCTRL_PIN(33, "GPIO_33"), + PINCTRL_PIN(34, "GPIO_34"), + PINCTRL_PIN(35, "GPIO_35"), + PINCTRL_PIN(36, "GPIO_36"), + PINCTRL_PIN(37, "GPIO_37"), + PINCTRL_PIN(38, "GPIO_38"), + PINCTRL_PIN(39, "GPIO_39"), + PINCTRL_PIN(40, "GPIO_40"), + PINCTRL_PIN(41, "GPIO_41"), + PINCTRL_PIN(42, "GPIO_42"), + PINCTRL_PIN(43, "GPIO_43"), + PINCTRL_PIN(44, "GPIO_44"), + PINCTRL_PIN(45, "GPIO_45"), + PINCTRL_PIN(46, "GPIO_46"), + PINCTRL_PIN(47, "GPIO_47"), + PINCTRL_PIN(48, "GPIO_48"), + PINCTRL_PIN(49, "GPIO_49"), + PINCTRL_PIN(50, "GPIO_50"), + PINCTRL_PIN(51, "GPIO_51"), + PINCTRL_PIN(52, "GPIO_52"), + PINCTRL_PIN(53, "GPIO_53"), + PINCTRL_PIN(54, "GPIO_54"), + PINCTRL_PIN(55, "GPIO_55"), + PINCTRL_PIN(56, "GPIO_56"), + PINCTRL_PIN(57, "GPIO_57"), + PINCTRL_PIN(58, "GPIO_58"), + PINCTRL_PIN(59, "GPIO_59"), + PINCTRL_PIN(60, "GPIO_60"), + PINCTRL_PIN(61, "GPIO_61"), + PINCTRL_PIN(62, "GPIO_62"), + PINCTRL_PIN(63, "GPIO_63"), + PINCTRL_PIN(64, "GPIO_64"), + PINCTRL_PIN(65, "GPIO_65"), + PINCTRL_PIN(66, "GPIO_66"), + PINCTRL_PIN(67, "GPIO_67"), + PINCTRL_PIN(68, "GPIO_68"), + PINCTRL_PIN(69, "GPIO_69"), + PINCTRL_PIN(70, "GPIO_70"), + PINCTRL_PIN(71, "GPIO_71"), + PINCTRL_PIN(72, "GPIO_72"), + PINCTRL_PIN(73, "GPIO_73"), + PINCTRL_PIN(74, "GPIO_74"), + PINCTRL_PIN(75, "GPIO_75"), + PINCTRL_PIN(76, "GPIO_76"), + PINCTRL_PIN(77, "GPIO_77"), + PINCTRL_PIN(78, "GPIO_78"), + PINCTRL_PIN(79, "GPIO_79"), + PINCTRL_PIN(80, "GPIO_80"), + PINCTRL_PIN(81, "GPIO_81"), + PINCTRL_PIN(82, "GPIO_82"), + PINCTRL_PIN(83, "GPIO_83"), + PINCTRL_PIN(84, "GPIO_84"), + PINCTRL_PIN(85, "GPIO_85"), + PINCTRL_PIN(86, "GPIO_86"), + PINCTRL_PIN(87, "GPIO_87"), + PINCTRL_PIN(88, "GPIO_88"), + PINCTRL_PIN(89, "GPIO_89"), + PINCTRL_PIN(90, "GPIO_90"), + PINCTRL_PIN(91, "GPIO_91"), + PINCTRL_PIN(92, "GPIO_92"), + PINCTRL_PIN(93, "GPIO_93"), + PINCTRL_PIN(94, "GPIO_94"), + PINCTRL_PIN(95, "GPIO_95"), + PINCTRL_PIN(96, "GPIO_96"), + PINCTRL_PIN(97, "GPIO_97"), + PINCTRL_PIN(98, "GPIO_98"), + PINCTRL_PIN(99, "GPIO_99"), + PINCTRL_PIN(100, "GPIO_100"), + PINCTRL_PIN(101, "GPIO_101"), + PINCTRL_PIN(102, "GPIO_102"), + PINCTRL_PIN(103, "GPIO_103"), + PINCTRL_PIN(104, "GPIO_104"), + PINCTRL_PIN(105, "GPIO_105"), + PINCTRL_PIN(106, "GPIO_106"), + PINCTRL_PIN(107, "GPIO_107"), + PINCTRL_PIN(108, "GPIO_108"), + PINCTRL_PIN(109, "GPIO_109"), + PINCTRL_PIN(110, "GPIO_110"), + PINCTRL_PIN(111, "GPIO_111"), + PINCTRL_PIN(112, "GPIO_112"), + PINCTRL_PIN(113, "GPIO_113"), + PINCTRL_PIN(114, "GPIO_114"), + PINCTRL_PIN(115, "GPIO_115"), + PINCTRL_PIN(116, "GPIO_116"), + PINCTRL_PIN(117, "GPIO_117"), + PINCTRL_PIN(118, "GPIO_118"), + PINCTRL_PIN(119, "UFS_RESET"), + PINCTRL_PIN(120, "SDC1_RCLK"), + PINCTRL_PIN(121, "SDC1_CLK"), + PINCTRL_PIN(122, "SDC1_CMD"), + PINCTRL_PIN(123, "SDC1_DATA"), + PINCTRL_PIN(124, "SDC2_CLK"), + PINCTRL_PIN(125, "SDC2_CMD"), + PINCTRL_PIN(126, "SDC2_DATA"), +}; + +#define DECLARE_MSM_GPIO_PINS(pin) \ + static const unsigned int gpio##pin##_pins[] = { pin } +DECLARE_MSM_GPIO_PINS(0); +DECLARE_MSM_GPIO_PINS(1); +DECLARE_MSM_GPIO_PINS(2); +DECLARE_MSM_GPIO_PINS(3); +DECLARE_MSM_GPIO_PINS(4); +DECLARE_MSM_GPIO_PINS(5); +DECLARE_MSM_GPIO_PINS(6); +DECLARE_MSM_GPIO_PINS(7); +DECLARE_MSM_GPIO_PINS(8); +DECLARE_MSM_GPIO_PINS(9); +DECLARE_MSM_GPIO_PINS(10); +DECLARE_MSM_GPIO_PINS(11); +DECLARE_MSM_GPIO_PINS(12); +DECLARE_MSM_GPIO_PINS(13); +DECLARE_MSM_GPIO_PINS(14); +DECLARE_MSM_GPIO_PINS(15); +DECLARE_MSM_GPIO_PINS(16); +DECLARE_MSM_GPIO_PINS(17); +DECLARE_MSM_GPIO_PINS(18); +DECLARE_MSM_GPIO_PINS(19); +DECLARE_MSM_GPIO_PINS(20); +DECLARE_MSM_GPIO_PINS(21); +DECLARE_MSM_GPIO_PINS(22); +DECLARE_MSM_GPIO_PINS(23); +DECLARE_MSM_GPIO_PINS(24); +DECLARE_MSM_GPIO_PINS(25); +DECLARE_MSM_GPIO_PINS(26); +DECLARE_MSM_GPIO_PINS(27); +DECLARE_MSM_GPIO_PINS(28); +DECLARE_MSM_GPIO_PINS(29); +DECLARE_MSM_GPIO_PINS(30); +DECLARE_MSM_GPIO_PINS(31); +DECLARE_MSM_GPIO_PINS(32); +DECLARE_MSM_GPIO_PINS(33); +DECLARE_MSM_GPIO_PINS(34); +DECLARE_MSM_GPIO_PINS(35); +DECLARE_MSM_GPIO_PINS(36); +DECLARE_MSM_GPIO_PINS(37); +DECLARE_MSM_GPIO_PINS(38); +DECLARE_MSM_GPIO_PINS(39); +DECLARE_MSM_GPIO_PINS(40); +DECLARE_MSM_GPIO_PINS(41); +DECLARE_MSM_GPIO_PINS(42); +DECLARE_MSM_GPIO_PINS(43); +DECLARE_MSM_GPIO_PINS(44); +DECLARE_MSM_GPIO_PINS(45); +DECLARE_MSM_GPIO_PINS(46); +DECLARE_MSM_GPIO_PINS(47); +DECLARE_MSM_GPIO_PINS(48); +DECLARE_MSM_GPIO_PINS(49); +DECLARE_MSM_GPIO_PINS(50); +DECLARE_MSM_GPIO_PINS(51); +DECLARE_MSM_GPIO_PINS(52); +DECLARE_MSM_GPIO_PINS(53); +DECLARE_MSM_GPIO_PINS(54); +DECLARE_MSM_GPIO_PINS(55); +DECLARE_MSM_GPIO_PINS(56); +DECLARE_MSM_GPIO_PINS(57); +DECLARE_MSM_GPIO_PINS(58); +DECLARE_MSM_GPIO_PINS(59); +DECLARE_MSM_GPIO_PINS(60); +DECLARE_MSM_GPIO_PINS(61); +DECLARE_MSM_GPIO_PINS(62); +DECLARE_MSM_GPIO_PINS(63); +DECLARE_MSM_GPIO_PINS(64); +DECLARE_MSM_GPIO_PINS(65); +DECLARE_MSM_GPIO_PINS(66); +DECLARE_MSM_GPIO_PINS(67); +DECLARE_MSM_GPIO_PINS(68); +DECLARE_MSM_GPIO_PINS(69); +DECLARE_MSM_GPIO_PINS(70); +DECLARE_MSM_GPIO_PINS(71); +DECLARE_MSM_GPIO_PINS(72); +DECLARE_MSM_GPIO_PINS(73); +DECLARE_MSM_GPIO_PINS(74); +DECLARE_MSM_GPIO_PINS(75); +DECLARE_MSM_GPIO_PINS(76); +DECLARE_MSM_GPIO_PINS(77); +DECLARE_MSM_GPIO_PINS(78); +DECLARE_MSM_GPIO_PINS(79); +DECLARE_MSM_GPIO_PINS(80); +DECLARE_MSM_GPIO_PINS(81); +DECLARE_MSM_GPIO_PINS(82); +DECLARE_MSM_GPIO_PINS(83); +DECLARE_MSM_GPIO_PINS(84); +DECLARE_MSM_GPIO_PINS(85); +DECLARE_MSM_GPIO_PINS(86); +DECLARE_MSM_GPIO_PINS(87); +DECLARE_MSM_GPIO_PINS(88); +DECLARE_MSM_GPIO_PINS(89); +DECLARE_MSM_GPIO_PINS(90); +DECLARE_MSM_GPIO_PINS(91); +DECLARE_MSM_GPIO_PINS(92); +DECLARE_MSM_GPIO_PINS(93); +DECLARE_MSM_GPIO_PINS(94); +DECLARE_MSM_GPIO_PINS(95); +DECLARE_MSM_GPIO_PINS(96); +DECLARE_MSM_GPIO_PINS(97); +DECLARE_MSM_GPIO_PINS(98); +DECLARE_MSM_GPIO_PINS(99); +DECLARE_MSM_GPIO_PINS(100); +DECLARE_MSM_GPIO_PINS(101); +DECLARE_MSM_GPIO_PINS(102); +DECLARE_MSM_GPIO_PINS(103); +DECLARE_MSM_GPIO_PINS(104); +DECLARE_MSM_GPIO_PINS(105); +DECLARE_MSM_GPIO_PINS(106); +DECLARE_MSM_GPIO_PINS(107); +DECLARE_MSM_GPIO_PINS(108); +DECLARE_MSM_GPIO_PINS(109); +DECLARE_MSM_GPIO_PINS(110); +DECLARE_MSM_GPIO_PINS(111); +DECLARE_MSM_GPIO_PINS(112); +DECLARE_MSM_GPIO_PINS(113); +DECLARE_MSM_GPIO_PINS(114); +DECLARE_MSM_GPIO_PINS(115); +DECLARE_MSM_GPIO_PINS(116); +DECLARE_MSM_GPIO_PINS(117); +DECLARE_MSM_GPIO_PINS(118); + +static const unsigned int ufs_reset_pins[] = { 119 }; +static const unsigned int sdc1_rclk_pins[] = { 120 }; +static const unsigned int sdc1_clk_pins[] = { 121 }; +static const unsigned int sdc1_cmd_pins[] = { 122 }; +static const unsigned int sdc1_data_pins[] = { 123 }; +static const unsigned int sdc2_clk_pins[] = { 124 }; +static const unsigned int sdc2_cmd_pins[] = { 125 }; +static const unsigned int sdc2_data_pins[] = { 126 }; + +enum sc7180_functions { + msm_mux_adsp_ext, + msm_mux_agera_pll, + msm_mux_aoss_cti, + msm_mux_atest_char, + msm_mux_atest_char0, + msm_mux_atest_char1, + msm_mux_atest_char2, + msm_mux_atest_char3, + msm_mux_atest_tsens, + msm_mux_atest_tsens2, + msm_mux_atest_usb1, + msm_mux_atest_usb2, + msm_mux_atest_usb10, + msm_mux_atest_usb11, + msm_mux_atest_usb12, + msm_mux_atest_usb13, + msm_mux_atest_usb20, + msm_mux_atest_usb21, + msm_mux_atest_usb22, + msm_mux_atest_usb23, + msm_mux_audio_ref, + msm_mux_btfm_slimbus, + msm_mux_cam_mclk, + msm_mux_cci_async, + msm_mux_cci_i2c, + msm_mux_cci_timer0, + msm_mux_cci_timer1, + msm_mux_cci_timer2, + msm_mux_cci_timer3, + msm_mux_cci_timer4, + msm_mux_cri_trng, + msm_mux_dbg_out, + msm_mux_ddr_bist, + msm_mux_ddr_pxi0, + msm_mux_ddr_pxi1, + msm_mux_ddr_pxi2, + msm_mux_ddr_pxi3, + msm_mux_dp_hot, + msm_mux_edp_lcd, + msm_mux_gcc_gp1, + msm_mux_gcc_gp2, + msm_mux_gcc_gp3, + msm_mux_gpio, + msm_mux_gp_pdm0, + msm_mux_gp_pdm1, + msm_mux_gp_pdm2, + msm_mux_gps_tx, + msm_mux_jitter_bist, + msm_mux_ldo_en, + msm_mux_ldo_update, + msm_mux_lpass_ext, + msm_mux_mdp_vsync, + msm_mux_mdp_vsync0, + msm_mux_mdp_vsync1, + msm_mux_mdp_vsync2, + msm_mux_mdp_vsync3, + msm_mux_mi2s_1, + msm_mux_mi2s_0, + msm_mux_mi2s_2, + msm_mux_mss_lte, + msm_mux_m_voc, + msm_mux_pa_indicator, + msm_mux_phase_flag, + msm_mux_PLL_BIST, + msm_mux_pll_bypassnl, + msm_mux_pll_reset, + msm_mux_prng_rosc, + msm_mux_qdss, + msm_mux_qdss_cti, + msm_mux_qlink_enable, + msm_mux_qlink_request, + msm_mux_qspi_clk, + msm_mux_qspi_cs, + msm_mux_qspi_data, + msm_mux_qup00, + msm_mux_qup01, + msm_mux_qup02, + msm_mux_qup03, + msm_mux_qup04, + msm_mux_qup05, + msm_mux_qup10, + msm_mux_qup11, + msm_mux_qup12, + msm_mux_qup13, + msm_mux_qup14, + msm_mux_qup15, + msm_mux_sdc1_tb, + msm_mux_sdc2_tb, + msm_mux_sd_write, + msm_mux_sp_cmu, + msm_mux_tgu_ch0, + msm_mux_tgu_ch1, + msm_mux_tgu_ch2, + msm_mux_tgu_ch3, + msm_mux_tsense_pwm1, + msm_mux_tsense_pwm2, + msm_mux_uim1, + msm_mux_uim2, + msm_mux_uim_batt, + msm_mux_usb_phy, + msm_mux_vfr_1, + msm_mux__V_GPIO, + msm_mux__V_PPS_IN, + msm_mux__V_PPS_OUT, + msm_mux_vsense_trigger, + msm_mux_wlan1_adc0, + msm_mux_wlan1_adc1, + msm_mux_wlan2_adc0, + msm_mux_wlan2_adc1, + msm_mux__, +}; + +static const char * const qup01_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3", "gpio12", "gpio94", +}; +static const char * const gpio_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7", + "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14", + "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21", + "gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28", + "gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35", + "gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42", + "gpio43", "gpio44", "gpio45", "gpio46", "gpio47", "gpio48", "gpio49", + "gpio50", "gpio51", "gpio52", "gpio53", "gpio54", "gpio55", "gpio56", + "gpio57", "gpio58", "gpio59", "gpio60", "gpio61", "gpio62", "gpio63", + "gpio64", "gpio65", "gpio66", "gpio67", "gpio68", "gpio69", "gpio70", + "gpio71", "gpio72", "gpio73", "gpio74", "gpio75", "gpio76", "gpio77", + "gpio78", "gpio79", "gpio80", "gpio81", "gpio82", "gpio83", "gpio84", + "gpio85", "gpio86", "gpio87", "gpio88", "gpio89", "gpio90", "gpio91", + "gpio92", "gpio93", "gpio94", "gpio95", "gpio96", "gpio97", "gpio98", + "gpio99", "gpio100", "gpio101", "gpio102", "gpio103", "gpio104", + "gpio105", "gpio106", "gpio107", "gpio108", "gpio109", "gpio110", + "gpio111", "gpio112", "gpio113", "gpio114", "gpio115", "gpio116", + "gpio117", "gpio118", +}; +static const char * const phase_flag_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio8", "gpio9", + "gpio11", "gpio12", "gpio17", "gpio18", "gpio19", + "gpio20", "gpio25", "gpio26", "gpio27", "gpio28", + "gpio32", "gpio33", "gpio34", "gpio35", "gpio36", + "gpio37", "gpio38", "gpio39", "gpio42", "gpio44", + "gpio56", "gpio57", "gpio58", "gpio63", "gpio64", + "gpio108", "gpio109", +}; +static const char * const cri_trng_groups[] = { + "gpio0", "gpio1", "gpio2", +}; +static const char * const sp_cmu_groups[] = { + "gpio3", +}; +static const char * const dbg_out_groups[] = { + "gpio3", +}; +static const char * const qdss_cti_groups[] = { + "gpio3", "gpio4", "gpio8", "gpio9", "gpio33", "gpio44", "gpio45", + "gpio72", +}; +static const char * const sdc1_tb_groups[] = { + "gpio4", +}; +static const char * const sdc2_tb_groups[] = { + "gpio5", +}; +static const char * const qup11_groups[] = { + "gpio6", "gpio7", +}; +static const char * const ddr_bist_groups[] = { + "gpio7", "gpio8", "gpio9", "gpio10", +}; +static const char * const gp_pdm1_groups[] = { + "gpio8", "gpio50", +}; +static const char * const mdp_vsync_groups[] = { + "gpio10", "gpio11", "gpio12", "gpio70", "gpio71", +}; +static const char * const edp_lcd_groups[] = { + "gpio11", +}; +static const char * const ddr_pxi2_groups[] = { + "gpio11", "gpio26", +}; +static const char * const m_voc_groups[] = { + "gpio12", +}; +static const char * const wlan2_adc0_groups[] = { + "gpio12", +}; +static const char * const atest_usb10_groups[] = { + "gpio12", +}; +static const char * const ddr_pxi3_groups[] = { + "gpio12", "gpio108", +}; +static const char * const cam_mclk_groups[] = { + "gpio13", "gpio14", "gpio15", "gpio16", "gpio23", +}; +static const char * const pll_bypassnl_groups[] = { + "gpio13", +}; +static const char * const qdss_groups[] = { + "gpio13", "gpio86", "gpio14", "gpio87", + "gpio15", "gpio88", "gpio16", "gpio89", + "gpio17", "gpio90", "gpio18", "gpio91", + "gpio19", "gpio21", "gpio20", "gpio22", + "gpio23", "gpio54", "gpio24", "gpio36", + "gpio25", "gpio57", "gpio26", "gpio31", + "gpio27", "gpio56", "gpio28", "gpio29", + "gpio30", "gpio35", "gpio93", "gpio104", + "gpio34", "gpio53", "gpio37", "gpio55", +}; +static const char * const pll_reset_groups[] = { + "gpio14", +}; +static const char * const qup02_groups[] = { + "gpio15", "gpio16", +}; +static const char * const cci_i2c_groups[] = { + "gpio17", "gpio18", "gpio19", "gpio20", "gpio27", "gpio28", +}; +static const char * const wlan1_adc0_groups[] = { + "gpio17", +}; +static const char * const atest_usb12_groups[] = { + "gpio17", +}; +static const char * const ddr_pxi1_groups[] = { + "gpio17", "gpio44", +}; +static const char * const atest_char_groups[] = { + "gpio17", +}; +static const char * const agera_pll_groups[] = { + "gpio18", +}; +static const char * const vsense_trigger_groups[] = { + "gpio18", +}; +static const char * const ddr_pxi0_groups[] = { + "gpio18", "gpio27", +}; +static const char * const atest_char3_groups[] = { + "gpio18", +}; +static const char * const atest_char2_groups[] = { + "gpio19", +}; +static const char * const atest_char1_groups[] = { + "gpio20", +}; +static const char * const cci_timer0_groups[] = { + "gpio21", +}; +static const char * const gcc_gp2_groups[] = { + "gpio21", +}; +static const char * const atest_char0_groups[] = { + "gpio21", +}; +static const char * const cci_timer1_groups[] = { + "gpio22", +}; +static const char * const gcc_gp3_groups[] = { + "gpio22", +}; +static const char * const cci_timer2_groups[] = { + "gpio23", +}; +static const char * const cci_timer3_groups[] = { + "gpio24", +}; +static const char * const cci_async_groups[] = { + "gpio24", "gpio25", "gpio26", +}; +static const char * const cci_timer4_groups[] = { + "gpio25", +}; +static const char * const qup05_groups[] = { + "gpio25", "gpio26", "gpio27", "gpio28", +}; +static const char * const atest_tsens_groups[] = { + "gpio26", +}; +static const char * const atest_usb11_groups[] = { + "gpio26", +}; +static const char * const PLL_BIST_groups[] = { + "gpio27", +}; +static const char * const sd_write_groups[] = { + "gpio33", +}; +static const char * const qup00_groups[] = { + "gpio34", "gpio35", "gpio36", "gpio37", +}; +static const char * const gp_pdm0_groups[] = { + "gpio37", "gpio68", +}; +static const char * const qup03_groups[] = { + "gpio38", "gpio39", "gpio40", "gpio41", +}; +static const char * const atest_tsens2_groups[] = { + "gpio39", +}; +static const char * const wlan2_adc1_groups[] = { + "gpio39", +}; +static const char * const atest_usb1_groups[] = { + "gpio39", +}; +static const char * const qup12_groups[] = { + "gpio42", "gpio43", "gpio44", "gpio45", +}; +static const char * const wlan1_adc1_groups[] = { + "gpio44", +}; +static const char * const atest_usb13_groups[] = { + "gpio44", +}; +static const char * const qup13_groups[] = { + "gpio46", "gpio47", +}; +static const char * const gcc_gp1_groups[] = { + "gpio48", "gpio56", +}; +static const char * const mi2s_1_groups[] = { + "gpio49", "gpio50", "gpio51", "gpio52", +}; +static const char * const btfm_slimbus_groups[] = { + "gpio49", "gpio50", "gpio51", "gpio52", +}; +static const char * const atest_usb2_groups[] = { + "gpio51", +}; +static const char * const atest_usb23_groups[] = { + "gpio52", +}; +static const char * const mi2s_0_groups[] = { + "gpio53", "gpio54", "gpio55", "gpio56", +}; +static const char * const qup15_groups[] = { + "gpio53", "gpio54", "gpio55", "gpio56", +}; +static const char * const atest_usb22_groups[] = { + "gpio53", +}; +static const char * const atest_usb21_groups[] = { + "gpio54", +}; +static const char * const atest_usb20_groups[] = { + "gpio55", +}; +static const char * const lpass_ext_groups[] = { + "gpio57", "gpio58", +}; +static const char * const audio_ref_groups[] = { + "gpio57", +}; +static const char * const jitter_bist_groups[] = { + "gpio57", +}; +static const char * const gp_pdm2_groups[] = { + "gpio57", +}; +static const char * const qup10_groups[] = { + "gpio59", "gpio60", "gpio61", "gpio62", "gpio68", "gpio72", +}; +static const char * const tgu_ch3_groups[] = { + "gpio62", +}; +static const char * const qspi_clk_groups[] = { + "gpio63", +}; +static const char * const mdp_vsync0_groups[] = { + "gpio63", +}; +static const char * const mi2s_2_groups[] = { + "gpio63", "gpio64", "gpio65", "gpio66", +}; +static const char * const mdp_vsync1_groups[] = { + "gpio63", +}; +static const char * const mdp_vsync2_groups[] = { + "gpio63", +}; +static const char * const mdp_vsync3_groups[] = { + "gpio63", +}; +static const char * const tgu_ch0_groups[] = { + "gpio63", +}; +static const char * const qspi_data_groups[] = { + "gpio64", "gpio65", "gpio66", "gpio67", +}; +static const char * const tgu_ch1_groups[] = { + "gpio64", +}; +static const char * const vfr_1_groups[] = { + "gpio65", +}; +static const char * const tgu_ch2_groups[] = { + "gpio65", +}; +static const char * const qspi_cs_groups[] = { + "gpio68", "gpio72", +}; +static const char * const ldo_en_groups[] = { + "gpio70", +}; +static const char * const ldo_update_groups[] = { + "gpio71", +}; +static const char * const prng_rosc_groups[] = { + "gpio72", +}; +static const char * const uim2_groups[] = { + "gpio75", "gpio76", "gpio77", "gpio78", +}; +static const char * const uim1_groups[] = { + "gpio79", "gpio80", "gpio81", "gpio82", +}; +static const char * const _V_GPIO_groups[] = { + "gpio83", "gpio84", "gpio107", +}; +static const char * const _V_PPS_IN_groups[] = { + "gpio83", "gpio84", "gpio107", +}; +static const char * const _V_PPS_OUT_groups[] = { + "gpio83", "gpio84", "gpio107", +}; +static const char * const gps_tx_groups[] = { + "gpio83", "gpio84", "gpio107", "gpio109", +}; +static const char * const uim_batt_groups[] = { + "gpio85", +}; +static const char * const dp_hot_groups[] = { + "gpio85", "gpio117", +}; +static const char * const aoss_cti_groups[] = { + "gpio85", +}; +static const char * const qup14_groups[] = { + "gpio86", "gpio87", "gpio88", "gpio89", "gpio90", "gpio91", +}; +static const char * const adsp_ext_groups[] = { + "gpio87", +}; +static const char * const tsense_pwm1_groups[] = { + "gpio88", +}; +static const char * const tsense_pwm2_groups[] = { + "gpio88", +}; +static const char * const qlink_request_groups[] = { + "gpio96", +}; +static const char * const qlink_enable_groups[] = { + "gpio97", +}; +static const char * const pa_indicator_groups[] = { + "gpio99", +}; +static const char * const usb_phy_groups[] = { + "gpio104", +}; +static const char * const mss_lte_groups[] = { + "gpio108", "gpio109", +}; +static const char * const qup04_groups[] = { + "gpio115", "gpio116", +}; + +static const struct msm_function sc7180_functions[] = { + FUNCTION(adsp_ext), + FUNCTION(agera_pll), + FUNCTION(aoss_cti), + FUNCTION(atest_char), + FUNCTION(atest_char0), + FUNCTION(atest_char1), + FUNCTION(atest_char2), + FUNCTION(atest_char3), + FUNCTION(atest_tsens), + FUNCTION(atest_tsens2), + FUNCTION(atest_usb1), + FUNCTION(atest_usb2), + FUNCTION(atest_usb10), + FUNCTION(atest_usb11), + FUNCTION(atest_usb12), + FUNCTION(atest_usb13), + FUNCTION(atest_usb20), + FUNCTION(atest_usb21), + FUNCTION(atest_usb22), + FUNCTION(atest_usb23), + FUNCTION(audio_ref), + FUNCTION(btfm_slimbus), + FUNCTION(cam_mclk), + FUNCTION(cci_async), + FUNCTION(cci_i2c), + FUNCTION(cci_timer0), + FUNCTION(cci_timer1), + FUNCTION(cci_timer2), + FUNCTION(cci_timer3), + FUNCTION(cci_timer4), + FUNCTION(cri_trng), + FUNCTION(dbg_out), + FUNCTION(ddr_bist), + FUNCTION(ddr_pxi0), + FUNCTION(ddr_pxi1), + FUNCTION(ddr_pxi2), + FUNCTION(ddr_pxi3), + FUNCTION(dp_hot), + FUNCTION(edp_lcd), + FUNCTION(gcc_gp1), + FUNCTION(gcc_gp2), + FUNCTION(gcc_gp3), + FUNCTION(gpio), + FUNCTION(gp_pdm0), + FUNCTION(gp_pdm1), + FUNCTION(gp_pdm2), + FUNCTION(gps_tx), + FUNCTION(jitter_bist), + FUNCTION(ldo_en), + FUNCTION(ldo_update), + FUNCTION(lpass_ext), + FUNCTION(mdp_vsync), + FUNCTION(mdp_vsync0), + FUNCTION(mdp_vsync1), + FUNCTION(mdp_vsync2), + FUNCTION(mdp_vsync3), + FUNCTION(mi2s_0), + FUNCTION(mi2s_1), + FUNCTION(mi2s_2), + FUNCTION(mss_lte), + FUNCTION(m_voc), + FUNCTION(pa_indicator), + FUNCTION(phase_flag), + FUNCTION(PLL_BIST), + FUNCTION(pll_bypassnl), + FUNCTION(pll_reset), + FUNCTION(prng_rosc), + FUNCTION(qdss), + FUNCTION(qdss_cti), + FUNCTION(qlink_enable), + FUNCTION(qlink_request), + FUNCTION(qspi_clk), + FUNCTION(qspi_cs), + FUNCTION(qspi_data), + FUNCTION(qup00), + FUNCTION(qup01), + FUNCTION(qup02), + FUNCTION(qup03), + FUNCTION(qup04), + FUNCTION(qup05), + FUNCTION(qup10), + FUNCTION(qup11), + FUNCTION(qup12), + FUNCTION(qup13), + FUNCTION(qup14), + FUNCTION(qup15), + FUNCTION(sdc1_tb), + FUNCTION(sdc2_tb), + FUNCTION(sd_write), + FUNCTION(sp_cmu), + FUNCTION(tgu_ch0), + FUNCTION(tgu_ch1), + FUNCTION(tgu_ch2), + FUNCTION(tgu_ch3), + FUNCTION(tsense_pwm1), + FUNCTION(tsense_pwm2), + FUNCTION(uim1), + FUNCTION(uim2), + FUNCTION(uim_batt), + FUNCTION(usb_phy), + FUNCTION(vfr_1), + FUNCTION(_V_GPIO), + FUNCTION(_V_PPS_IN), + FUNCTION(_V_PPS_OUT), + FUNCTION(vsense_trigger), + FUNCTION(wlan1_adc0), + FUNCTION(wlan1_adc1), + FUNCTION(wlan2_adc0), + FUNCTION(wlan2_adc1), +}; + +/* Every pin is maintained as a single group, and missing or non-existing pin + * would be maintained as dummy group to synchronize pin group index with + * pin descriptor registered with pinctrl core. + * Clients would not be able to request these dummy pin groups. + */ +static const struct msm_pingroup sc7180_groups[] = { + [0] = PINGROUP(0, SOUTH, qup01, cri_trng, _, phase_flag, _, _, _, _, _), + [1] = PINGROUP(1, SOUTH, qup01, cri_trng, _, phase_flag, _, _, _, _, _), + [2] = PINGROUP(2, SOUTH, qup01, cri_trng, _, phase_flag, _, _, _, _, _), + [3] = PINGROUP(3, SOUTH, qup01, sp_cmu, dbg_out, qdss_cti, _, _, _, _, _), + [4] = PINGROUP(4, NORTH, sdc1_tb, _, qdss_cti, _, _, _, _, _, _), + [5] = PINGROUP(5, NORTH, sdc2_tb, _, _, _, _, _, _, _, _), + [6] = PINGROUP(6, NORTH, qup11, qup11, _, _, _, _, _, _, _), + [7] = PINGROUP(7, NORTH, qup11, qup11, ddr_bist, _, _, _, _, _, _), + [8] = PINGROUP(8, NORTH, gp_pdm1, ddr_bist, _, phase_flag, qdss_cti, _, _, _, _), + [9] = PINGROUP(9, NORTH, ddr_bist, _, phase_flag, qdss_cti, _, _, _, _, _), + [10] = PINGROUP(10, NORTH, mdp_vsync, ddr_bist, _, _, _, _, _, _, _), + [11] = PINGROUP(11, NORTH, mdp_vsync, edp_lcd, _, phase_flag, ddr_pxi2, _, _, _, _), + [12] = PINGROUP(12, SOUTH, mdp_vsync, m_voc, qup01, _, phase_flag, wlan2_adc0, atest_usb10, ddr_pxi3, _), + [13] = PINGROUP(13, SOUTH, cam_mclk, pll_bypassnl, qdss, _, _, _, _, _, _), + [14] = PINGROUP(14, SOUTH, cam_mclk, pll_reset, qdss, _, _, _, _, _, _), + [15] = PINGROUP(15, SOUTH, cam_mclk, qup02, qup02, qdss, _, _, _, _, _), + [16] = PINGROUP(16, SOUTH, cam_mclk, qup02, qup02, qdss, _, _, _, _, _), + [17] = PINGROUP(17, SOUTH, cci_i2c, _, phase_flag, qdss, _, wlan1_adc0, atest_usb12, ddr_pxi1, atest_char), + [18] = PINGROUP(18, SOUTH, cci_i2c, agera_pll, _, phase_flag, qdss, vsense_trigger, ddr_pxi0, atest_char3, _), + [19] = PINGROUP(19, SOUTH, cci_i2c, _, phase_flag, qdss, atest_char2, _, _, _, _), + [20] = PINGROUP(20, SOUTH, cci_i2c, _, phase_flag, qdss, atest_char1, _, _, _, _), + [21] = PINGROUP(21, NORTH, cci_timer0, gcc_gp2, _, qdss, atest_char0, _, _, _, _), + [22] = PINGROUP(22, NORTH, cci_timer1, gcc_gp3, _, qdss, _, _, _, _, _), + [23] = PINGROUP(23, SOUTH, cci_timer2, cam_mclk, qdss, _, _, _, _, _, _), + [24] = PINGROUP(24, SOUTH, cci_timer3, cci_async, qdss, _, _, _, _, _, _), + [25] = PINGROUP(25, SOUTH, cci_timer4, cci_async, qup05, _, phase_flag, qdss, _, _, _), + [26] = PINGROUP(26, SOUTH, cci_async, qup05, _, phase_flag, qdss, atest_tsens, atest_usb11, ddr_pxi2, _), + [27] = PINGROUP(27, SOUTH, cci_i2c, qup05, PLL_BIST, _, phase_flag, qdss, ddr_pxi0, _, _), + [28] = PINGROUP(28, SOUTH, cci_i2c, qup05, _, phase_flag, qdss, _, _, _, _), + [29] = PINGROUP(29, NORTH, _, qdss, _, _, _, _, _, _, _), + [30] = PINGROUP(30, SOUTH, qdss, _, _, _, _, _, _, _, _), + [31] = PINGROUP(31, NORTH, _, qdss, _, _, _, _, _, _, _), + [32] = PINGROUP(32, NORTH, _, phase_flag, _, _, _, _, _, _, _), + [33] = PINGROUP(33, NORTH, sd_write, _, phase_flag, qdss_cti, _, _, _, _, _), + [34] = PINGROUP(34, SOUTH, qup00, _, phase_flag, qdss, _, _, _, _, _), + [35] = PINGROUP(35, SOUTH, qup00, _, phase_flag, qdss, _, _, _, _, _), + [36] = PINGROUP(36, SOUTH, qup00, _, phase_flag, qdss, _, _, _, _, _), + [37] = PINGROUP(37, SOUTH, qup00, gp_pdm0, _, phase_flag, qdss, _, _, _, _), + [38] = PINGROUP(38, SOUTH, qup03, _, phase_flag, _, _, _, _, _, _), + [39] = PINGROUP(39, SOUTH, qup03, _, phase_flag, atest_tsens2, wlan2_adc1, atest_usb1, _, _, _), + [40] = PINGROUP(40, SOUTH, qup03, _, _, _, _, _, _, _, _), + [41] = PINGROUP(41, SOUTH, qup03, _, _, _, _, _, _, _, _), + [42] = PINGROUP(42, NORTH, qup12, _, phase_flag, _, _, _, _, _, _), + [43] = PINGROUP(43, NORTH, qup12, _, _, _, _, _, _, _, _), + [44] = PINGROUP(44, NORTH, qup12, _, phase_flag, qdss_cti, wlan1_adc1, atest_usb13, ddr_pxi1, _, _), + [45] = PINGROUP(45, NORTH, qup12, qdss_cti, _, _, _, _, _, _, _), + [46] = PINGROUP(46, NORTH, qup13, qup13, _, _, _, _, _, _, _), + [47] = PINGROUP(47, NORTH, qup13, qup13, _, _, _, _, _, _, _), + [48] = PINGROUP(48, NORTH, gcc_gp1, _, _, _, _, _, _, _, _), + [49] = PINGROUP(49, WEST, mi2s_1, btfm_slimbus, _, _, _, _, _, _, _), + [50] = PINGROUP(50, WEST, mi2s_1, btfm_slimbus, gp_pdm1, _, _, _, _, _, _), + [51] = PINGROUP(51, WEST, mi2s_1, btfm_slimbus, atest_usb2, _, _, _, _, _, _), + [52] = PINGROUP(52, WEST, mi2s_1, btfm_slimbus, atest_usb23, _, _, _, _, _, _), + [53] = PINGROUP(53, WEST, mi2s_0, qup15, qdss, atest_usb22, _, _, _, _, _), + [54] = PINGROUP(54, WEST, mi2s_0, qup15, qdss, atest_usb21, _, _, _, _, _), + [55] = PINGROUP(55, WEST, mi2s_0, qup15, qdss, atest_usb20, _, _, _, _, _), + [56] = PINGROUP(56, WEST, mi2s_0, qup15, gcc_gp1, _, phase_flag, qdss, _, _, _), + [57] = PINGROUP(57, WEST, lpass_ext, audio_ref, jitter_bist, gp_pdm2, _, phase_flag, qdss, _, _), + [58] = PINGROUP(58, WEST, lpass_ext, _, phase_flag, _, _, _, _, _, _), + [59] = PINGROUP(59, NORTH, qup10, _, _, _, _, _, _, _, _), + [60] = PINGROUP(60, NORTH, qup10, _, _, _, _, _, _, _, _), + [61] = PINGROUP(61, NORTH, qup10, _, _, _, _, _, _, _, _), + [62] = PINGROUP(62, NORTH, qup10, tgu_ch3, _, _, _, _, _, _, _), + [63] = PINGROUP(63, NORTH, qspi_clk, mdp_vsync0, mi2s_2, mdp_vsync1, mdp_vsync2, mdp_vsync3, tgu_ch0, _, phase_flag), + [64] = PINGROUP(64, NORTH, qspi_data, mi2s_2, tgu_ch1, _, phase_flag, _, _, _, _), + [65] = PINGROUP(65, NORTH, qspi_data, mi2s_2, vfr_1, tgu_ch2, _, _, _, _, _), + [66] = PINGROUP(66, NORTH, qspi_data, mi2s_2, _, _, _, _, _, _, _), + [67] = PINGROUP(67, NORTH, qspi_data, _, _, _, _, _, _, _, _), + [68] = PINGROUP(68, NORTH, qspi_cs, qup10, gp_pdm0, _, _, _, _, _, _), + [69] = PINGROUP(69, WEST, _, _, _, _, _, _, _, _, _), + [70] = PINGROUP(70, NORTH, _, _, mdp_vsync, ldo_en, _, _, _, _, _), + [71] = PINGROUP(71, NORTH, _, mdp_vsync, ldo_update, _, _, _, _, _, _), + [72] = PINGROUP(72, NORTH, qspi_cs, qup10, prng_rosc, _, qdss_cti, _, _, _, _), + [73] = PINGROUP(73, WEST, _, _, _, _, _, _, _, _, _), + [74] = PINGROUP(74, WEST, _, _, _, _, _, _, _, _, _), + [75] = PINGROUP(75, WEST, uim2, _, _, _, _, _, _, _, _), + [76] = PINGROUP(76, WEST, uim2, _, _, _, _, _, _, _, _), + [77] = PINGROUP(77, WEST, uim2, _, _, _, _, _, _, _, _), + [78] = PINGROUP(78, WEST, uim2, _, _, _, _, _, _, _, _), + [79] = PINGROUP(79, WEST, uim1, _, _, _, _, _, _, _, _), + [80] = PINGROUP(80, WEST, uim1, _, _, _, _, _, _, _, _), + [81] = PINGROUP(81, WEST, uim1, _, _, _, _, _, _, _, _), + [82] = PINGROUP(82, WEST, uim1, _, _, _, _, _, _, _, _), + [83] = PINGROUP(83, WEST, _, _V_GPIO, _V_PPS_IN, _V_PPS_OUT, gps_tx, _, _, _, _), + [84] = PINGROUP(84, WEST, _, _V_GPIO, _V_PPS_IN, _V_PPS_OUT, gps_tx, _, _, _, _), + [85] = PINGROUP(85, WEST, uim_batt, dp_hot, aoss_cti, _, _, _, _, _, _), + [86] = PINGROUP(86, NORTH, qup14, qdss, _, _, _, _, _, _, _), + [87] = PINGROUP(87, NORTH, qup14, adsp_ext, qdss, _, _, _, _, _, _), + [88] = PINGROUP(88, NORTH, qup14, qdss, tsense_pwm1, tsense_pwm2, _, _, _, _, _), + [89] = PINGROUP(89, NORTH, qup14, qdss, _, _, _, _, _, _, _), + [90] = PINGROUP(90, NORTH, qup14, qdss, _, _, _, _, _, _, _), + [91] = PINGROUP(91, NORTH, qup14, qdss, _, _, _, _, _, _, _), + [92] = PINGROUP(92, NORTH, _, _, _, _, _, _, _, _, _), + [93] = PINGROUP(93, NORTH, qdss, _, _, _, _, _, _, _, _), + [94] = PINGROUP(94, SOUTH, qup01, _, _, _, _, _, _, _, _), + [95] = PINGROUP(95, WEST, _, _, _, _, _, _, _, _, _), + [96] = PINGROUP(96, WEST, qlink_request, _, _, _, _, _, _, _, _), + [97] = PINGROUP(97, WEST, qlink_enable, _, _, _, _, _, _, _, _), + [98] = PINGROUP(98, WEST, _, _, _, _, _, _, _, _, _), + [99] = PINGROUP(99, WEST, _, pa_indicator, _, _, _, _, _, _, _), + [100] = PINGROUP(100, WEST, _, _, _, _, _, _, _, _, _), + [101] = PINGROUP(101, NORTH, _, _, _, _, _, _, _, _, _), + [102] = PINGROUP(102, NORTH, _, _, _, _, _, _, _, _, _), + [103] = PINGROUP(103, NORTH, _, _, _, _, _, _, _, _, _), + [104] = PINGROUP(104, WEST, usb_phy, _, qdss, _, _, _, _, _, _), + [105] = PINGROUP(105, NORTH, _, _, _, _, _, _, _, _, _), + [106] = PINGROUP(106, NORTH, _, _, _, _, _, _, _, _, _), + [107] = PINGROUP(107, WEST, _, _V_GPIO, _V_PPS_IN, _V_PPS_OUT, gps_tx, _, _, _, _), + [108] = PINGROUP(108, SOUTH, mss_lte, _, phase_flag, ddr_pxi3, _, _, _, _, _), + [109] = PINGROUP(109, SOUTH, mss_lte, gps_tx, _, phase_flag, _, _, _, _, _), + [110] = PINGROUP(110, NORTH, _, _, _, _, _, _, _, _, _), + [111] = PINGROUP(111, NORTH, _, _, _, _, _, _, _, _, _), + [112] = PINGROUP(112, NORTH, _, _, _, _, _, _, _, _, _), + [113] = PINGROUP(113, NORTH, _, _, _, _, _, _, _, _, _), + [114] = PINGROUP(114, NORTH, _, _, _, _, _, _, _, _, _), + [115] = PINGROUP(115, WEST, qup04, qup04, _, _, _, _, _, _, _), + [116] = PINGROUP(116, WEST, qup04, qup04, _, _, _, _, _, _, _), + [117] = PINGROUP(117, WEST, dp_hot, _, _, _, _, _, _, _, _), + [118] = PINGROUP(118, WEST, _, _, _, _, _, _, _, _, _), + [119] = UFS_RESET(ufs_reset, 0x97f000), + [120] = SDC_QDSD_PINGROUP(sdc1_rclk, 0x97a000, 15, 0), + [121] = SDC_QDSD_PINGROUP(sdc1_clk, 0x97a000, 13, 6), + [122] = SDC_QDSD_PINGROUP(sdc1_cmd, 0x97a000, 11, 3), + [123] = SDC_QDSD_PINGROUP(sdc1_data, 0x97a000, 9, 0), + [124] = SDC_QDSD_PINGROUP(sdc2_clk, 0x97b000, 14, 6), + [125] = SDC_QDSD_PINGROUP(sdc2_cmd, 0x97b000, 11, 3), + [126] = SDC_QDSD_PINGROUP(sdc2_data, 0x97b000, 9, 0), +}; + +static const struct msm_pinctrl_soc_data sc7180_pinctrl = { + .pins = sc7180_pins, + .npins = ARRAY_SIZE(sc7180_pins), + .functions = sc7180_functions, + .nfunctions = ARRAY_SIZE(sc7180_functions), + .groups = sc7180_groups, + .ngroups = ARRAY_SIZE(sc7180_groups), + .ngpios = 120, + .tiles = sc7180_tiles, + .ntiles = ARRAY_SIZE(sc7180_tiles), +}; + +static int sc7180_pinctrl_probe(struct platform_device *pdev) +{ + return msm_pinctrl_probe(pdev, &sc7180_pinctrl); +} + +static const struct of_device_id sc7180_pinctrl_of_match[] = { + { .compatible = "qcom,sc7180-pinctrl", }, + { }, +}; + +static struct platform_driver sc7180_pinctrl_driver = { + .driver = { + .name = "sc7180-pinctrl", + .pm = &msm_pinctrl_dev_pm_ops, + .of_match_table = sc7180_pinctrl_of_match, + }, + .probe = sc7180_pinctrl_probe, + .remove = msm_pinctrl_remove, +}; + +static int __init sc7180_pinctrl_init(void) +{ + return platform_driver_register(&sc7180_pinctrl_driver); +} +arch_initcall(sc7180_pinctrl_init); + +static void __exit sc7180_pinctrl_exit(void) +{ + platform_driver_unregister(&sc7180_pinctrl_driver); +} +module_exit(sc7180_pinctrl_exit); + +MODULE_DESCRIPTION("QTI sc7180 pinctrl driver"); +MODULE_LICENSE("GPL v2"); +MODULE_DEVICE_TABLE(of, sc7180_pinctrl_of_match); diff --git a/drivers/pinctrl/qcom/pinctrl-sdm845.c b/drivers/pinctrl/qcom/pinctrl-sdm845.c index 39f498c09906..ce495970459d 100644 --- a/drivers/pinctrl/qcom/pinctrl-sdm845.c +++ b/drivers/pinctrl/qcom/pinctrl-sdm845.c @@ -262,10 +262,10 @@ static const struct pinctrl_pin_desc sdm845_pins[] = { PINCTRL_PIN(147, "GPIO_147"), PINCTRL_PIN(148, "GPIO_148"), PINCTRL_PIN(149, "GPIO_149"), - PINCTRL_PIN(150, "SDC2_CLK"), - PINCTRL_PIN(151, "SDC2_CMD"), - PINCTRL_PIN(152, "SDC2_DATA"), - PINCTRL_PIN(153, "UFS_RESET"), + PINCTRL_PIN(150, "UFS_RESET"), + PINCTRL_PIN(151, "SDC2_CLK"), + PINCTRL_PIN(152, "SDC2_CMD"), + PINCTRL_PIN(153, "SDC2_DATA"), }; #define DECLARE_MSM_GPIO_PINS(pin) \ diff --git a/drivers/pinctrl/qcom/pinctrl-spmi-gpio.c b/drivers/pinctrl/qcom/pinctrl-spmi-gpio.c index 442db15e0729..f1fece5b9c06 100644 --- a/drivers/pinctrl/qcom/pinctrl-spmi-gpio.c +++ b/drivers/pinctrl/qcom/pinctrl-spmi-gpio.c @@ -793,11 +793,13 @@ static int pmic_gpio_populate(struct pmic_gpio_state *state, switch (subtype) { case PMIC_GPIO_SUBTYPE_GPIO_4CH: pad->have_buffer = true; + /* Fall through */ case PMIC_GPIO_SUBTYPE_GPIOC_4CH: pad->num_sources = 4; break; case PMIC_GPIO_SUBTYPE_GPIO_8CH: pad->have_buffer = true; + /* Fall through */ case PMIC_GPIO_SUBTYPE_GPIOC_8CH: pad->num_sources = 8; break; @@ -1113,6 +1115,12 @@ static const struct of_device_id pmic_gpio_of_match[] = { { .compatible = "qcom,pma8084-gpio", .data = (void *) 22 }, /* pms405 has 12 GPIOs with holes on 1, 9, and 10 */ { .compatible = "qcom,pms405-gpio", .data = (void *) 12 }, + /* pm8150 has 10 GPIOs with holes on 2, 5, 7 and 8 */ + { .compatible = "qcom,pm8150-gpio", .data = (void *) 10 }, + /* pm8150b has 12 GPIOs with holes on 3, r and 7 */ + { .compatible = "qcom,pm8150b-gpio", .data = (void *) 12 }, + /* pm8150l has 12 GPIOs with holes on 7 */ + { .compatible = "qcom,pm8150l-gpio", .data = (void *) 12 }, { }, }; diff --git a/drivers/pinctrl/qcom/pinctrl-ssbi-mpp.c b/drivers/pinctrl/qcom/pinctrl-ssbi-mpp.c index 076ba085a6a1..3d8b1d74fa2f 100644 --- a/drivers/pinctrl/qcom/pinctrl-ssbi-mpp.c +++ b/drivers/pinctrl/qcom/pinctrl-ssbi-mpp.c @@ -791,11 +791,8 @@ static int pm8xxx_mpp_probe(struct platform_device *pdev) for (i = 0; i < pctrl->desc.npins; i++) { pin_data[i].reg = SSBI_REG_ADDR_MPP(i); pin_data[i].irq = platform_get_irq(pdev, i); - if (pin_data[i].irq < 0) { - dev_err(&pdev->dev, - "missing interrupts for pin %d\n", i); + if (pin_data[i].irq < 0) return pin_data[i].irq; - } ret = pm8xxx_pin_populate(pctrl, &pin_data[i]); if (ret) diff --git a/drivers/pinctrl/sh-pfc/gpio.c b/drivers/pinctrl/sh-pfc/gpio.c index 97c1332c1045..5a55b8da7919 100644 --- a/drivers/pinctrl/sh-pfc/gpio.c +++ b/drivers/pinctrl/sh-pfc/gpio.c @@ -7,7 +7,7 @@ */ #include <linux/device.h> -#include <linux/gpio.h> +#include <linux/gpio/driver.h> #include <linux/init.h> #include <linux/module.h> #include <linux/pinctrl/consumer.h> @@ -255,18 +255,13 @@ static int gpio_pin_setup(struct sh_pfc_chip *chip) #ifdef CONFIG_PINCTRL_SH_FUNC_GPIO static int gpio_function_request(struct gpio_chip *gc, unsigned offset) { - static bool __print_once; struct sh_pfc *pfc = gpio_to_pfc(gc); unsigned int mark = pfc->info->func_gpios[offset].enum_id; unsigned long flags; int ret; - if (!__print_once) { - dev_notice(pfc->dev, - "Use of GPIO API for function requests is deprecated." - " Convert to pinctrl\n"); - __print_once = true; - } + dev_notice_once(pfc->dev, + "Use of GPIO API for function requests is deprecated, convert to pinctrl\n"); if (mark == 0) return -EINVAL; diff --git a/drivers/pinctrl/sh-pfc/pinctrl.c b/drivers/pinctrl/sh-pfc/pinctrl.c index 2824be4eb887..212a4a9c3a8f 100644 --- a/drivers/pinctrl/sh-pfc/pinctrl.c +++ b/drivers/pinctrl/sh-pfc/pinctrl.c @@ -26,7 +26,9 @@ #include "../pinconf.h" struct sh_pfc_pin_config { - u32 type; + unsigned int mux_mark; + bool mux_set; + bool gpio_enabled; }; struct sh_pfc_pinctrl { @@ -355,16 +357,27 @@ static int sh_pfc_func_set_mux(struct pinctrl_dev *pctldev, unsigned selector, int idx = sh_pfc_get_pin_index(pfc, grp->pins[i]); struct sh_pfc_pin_config *cfg = &pmx->configs[idx]; - if (cfg->type != PINMUX_TYPE_NONE) { + /* + * This driver cannot manage both gpio and mux when the gpio + * pin is already enabled. So, this function fails. + */ + if (cfg->gpio_enabled) { ret = -EBUSY; goto done; } - } - for (i = 0; i < grp->nr_pins; ++i) { ret = sh_pfc_config_mux(pfc, grp->mux[i], PINMUX_TYPE_FUNCTION); if (ret < 0) - break; + goto done; + } + + /* All group pins are configured, mark the pins as mux_set */ + for (i = 0; i < grp->nr_pins; ++i) { + int idx = sh_pfc_get_pin_index(pfc, grp->pins[i]); + struct sh_pfc_pin_config *cfg = &pmx->configs[idx]; + + cfg->mux_set = true; + cfg->mux_mark = grp->mux[i]; } done: @@ -385,14 +398,6 @@ static int sh_pfc_gpio_request_enable(struct pinctrl_dev *pctldev, spin_lock_irqsave(&pfc->lock, flags); - if (cfg->type != PINMUX_TYPE_NONE) { - dev_err(pfc->dev, - "Pin %u is busy, can't configure it as GPIO.\n", - offset); - ret = -EBUSY; - goto done; - } - if (!pfc->gpio) { /* If GPIOs are handled externally the pin mux type need to be * set to GPIO here. @@ -404,7 +409,7 @@ static int sh_pfc_gpio_request_enable(struct pinctrl_dev *pctldev, goto done; } - cfg->type = PINMUX_TYPE_GPIO; + cfg->gpio_enabled = true; ret = 0; @@ -425,7 +430,10 @@ static void sh_pfc_gpio_disable_free(struct pinctrl_dev *pctldev, unsigned long flags; spin_lock_irqsave(&pfc->lock, flags); - cfg->type = PINMUX_TYPE_NONE; + cfg->gpio_enabled = false; + /* If mux is already set, this configures it here */ + if (cfg->mux_set) + sh_pfc_config_mux(pfc, cfg->mux_mark, PINMUX_TYPE_FUNCTION); spin_unlock_irqrestore(&pfc->lock, flags); } @@ -438,7 +446,6 @@ static int sh_pfc_gpio_set_direction(struct pinctrl_dev *pctldev, int new_type = input ? PINMUX_TYPE_INPUT : PINMUX_TYPE_OUTPUT; int idx = sh_pfc_get_pin_index(pfc, offset); const struct sh_pfc_pin *pin = &pfc->info->pins[idx]; - struct sh_pfc_pin_config *cfg = &pmx->configs[idx]; unsigned long flags; unsigned int dir; int ret; @@ -458,8 +465,6 @@ static int sh_pfc_gpio_set_direction(struct pinctrl_dev *pctldev, if (ret < 0) goto done; - cfg->type = new_type; - done: spin_unlock_irqrestore(&pfc->lock, flags); return ret; @@ -782,13 +787,11 @@ static int sh_pfc_map_pins(struct sh_pfc *pfc, struct sh_pfc_pinctrl *pmx) for (i = 0; i < pfc->info->nr_pins; ++i) { const struct sh_pfc_pin *info = &pfc->info->pins[i]; - struct sh_pfc_pin_config *cfg = &pmx->configs[i]; struct pinctrl_pin_desc *pin = &pmx->pins[i]; /* If the pin number is equal to -1 all pins are considered */ pin->number = info->pin != (u16)-1 ? info->pin : i; pin->name = info->name; - cfg->type = PINMUX_TYPE_NONE; } return 0; diff --git a/drivers/pinctrl/spear/pinctrl-spear.c b/drivers/pinctrl/spear/pinctrl-spear.c index c4f850345dc4..7ec19c73f870 100644 --- a/drivers/pinctrl/spear/pinctrl-spear.c +++ b/drivers/pinctrl/spear/pinctrl-spear.c @@ -157,12 +157,16 @@ static int spear_pinctrl_dt_node_to_map(struct pinctrl_dev *pctldev, /* calculate number of maps required */ for_each_child_of_node(np_config, np) { ret = of_property_read_string(np, "st,function", &function); - if (ret < 0) + if (ret < 0) { + of_node_put(np); return ret; + } ret = of_property_count_strings(np, "st,pins"); - if (ret < 0) + if (ret < 0) { + of_node_put(np); return ret; + } count += ret; } diff --git a/drivers/pinctrl/sprd/pinctrl-sprd-sc9860.c b/drivers/pinctrl/sprd/pinctrl-sprd-sc9860.c index 3b65aeab7244..06c8671b40e7 100644 --- a/drivers/pinctrl/sprd/pinctrl-sprd-sc9860.c +++ b/drivers/pinctrl/sprd/pinctrl-sprd-sc9860.c @@ -940,7 +940,6 @@ MODULE_DEVICE_TABLE(of, sprd_pinctrl_of_match); static struct platform_driver sprd_pinctrl_driver = { .driver = { .name = "sprd-pinctrl", - .owner = THIS_MODULE, .of_match_table = sprd_pinctrl_of_match, }, .probe = sprd_pinctrl_probe, diff --git a/drivers/pinctrl/sprd/pinctrl-sprd.c b/drivers/pinctrl/sprd/pinctrl-sprd.c index c31b58168772..7b95bf5a82a9 100644 --- a/drivers/pinctrl/sprd/pinctrl-sprd.c +++ b/drivers/pinctrl/sprd/pinctrl-sprd.c @@ -454,7 +454,7 @@ static int sprd_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin_id, if (pin->type == GLOBAL_CTRL_PIN && param == SPRD_PIN_CONFIG_CONTROL) { arg = reg; - } else if (pin->type == COMMON_PIN) { + } else if (pin->type == COMMON_PIN || pin->type == MISC_PIN) { switch (param) { case SPRD_PIN_CONFIG_SLEEP_MODE: arg = (reg >> SLEEP_MODE_SHIFT) & SLEEP_MODE_MASK; @@ -465,14 +465,6 @@ static int sprd_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin_id, case PIN_CONFIG_OUTPUT: arg = reg & SLEEP_OUTPUT_MASK; break; - case PIN_CONFIG_SLEEP_HARDWARE_STATE: - arg = 0; - break; - default: - return -ENOTSUPP; - } - } else if (pin->type == MISC_PIN) { - switch (param) { case PIN_CONFIG_DRIVE_STRENGTH: arg = (reg >> DRIVE_STRENGTH_SHIFT) & DRIVE_STRENGTH_MASK; @@ -606,7 +598,7 @@ static int sprd_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin_id, if (pin->type == GLOBAL_CTRL_PIN && param == SPRD_PIN_CONFIG_CONTROL) { val = arg; - } else if (pin->type == COMMON_PIN) { + } else if (pin->type == COMMON_PIN || pin->type == MISC_PIN) { switch (param) { case SPRD_PIN_CONFIG_SLEEP_MODE: if (arg & AP_SLEEP) @@ -639,13 +631,6 @@ static int sprd_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin_id, shift = SLEEP_OUTPUT_SHIFT; } break; - case PIN_CONFIG_SLEEP_HARDWARE_STATE: - continue; - default: - return -ENOTSUPP; - } - } else if (pin->type == MISC_PIN) { - switch (param) { case PIN_CONFIG_DRIVE_STRENGTH: if (arg < 2 || arg > 60) return -EINVAL; @@ -940,8 +925,10 @@ static int sprd_pinctrl_parse_dt(struct sprd_pinctrl *sprd_pctl) for_each_child_of_node(np, child) { ret = sprd_pinctrl_parse_groups(child, sprd_pctl, grp); - if (ret) + if (ret) { + of_node_put(child); return ret; + } *temp++ = grp->name; grp++; @@ -950,8 +937,11 @@ static int sprd_pinctrl_parse_dt(struct sprd_pinctrl *sprd_pctl) for_each_child_of_node(child, sub_child) { ret = sprd_pinctrl_parse_groups(sub_child, sprd_pctl, grp); - if (ret) + if (ret) { + of_node_put(sub_child); + of_node_put(child); return ret; + } *temp++ = grp->name; grp++; @@ -1020,7 +1010,6 @@ int sprd_pinctrl_core_probe(struct platform_device *pdev, struct sprd_pinctrl *sprd_pctl; struct sprd_pinctrl_soc_info *pinctrl_info; struct pinctrl_pin_desc *pin_desc; - struct resource *res; int ret, i; sprd_pctl = devm_kzalloc(&pdev->dev, sizeof(struct sprd_pinctrl), @@ -1028,8 +1017,7 @@ int sprd_pinctrl_core_probe(struct platform_device *pdev, if (!sprd_pctl) return -ENOMEM; - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - sprd_pctl->base = devm_ioremap_resource(&pdev->dev, res); + sprd_pctl->base = devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(sprd_pctl->base)) return PTR_ERR(sprd_pctl->base); diff --git a/drivers/pinctrl/stm32/pinctrl-stm32.c b/drivers/pinctrl/stm32/pinctrl-stm32.c index b453aed1bbeb..2d5e0435af0a 100644 --- a/drivers/pinctrl/stm32/pinctrl-stm32.c +++ b/drivers/pinctrl/stm32/pinctrl-stm32.c @@ -615,6 +615,7 @@ static int stm32_pctrl_dt_node_to_map(struct pinctrl_dev *pctldev, &reserved_maps, num_maps); if (ret < 0) { pinctrl_utils_free_map(pctldev, *map, *num_maps); + of_node_put(np); return ret; } } @@ -1468,8 +1469,10 @@ int stm32_pctl_probe(struct platform_device *pdev) for_each_available_child_of_node(np, child) { if (of_property_read_bool(child, "gpio-controller")) { ret = stm32_gpiolib_register_bank(pctl, child); - if (ret) + if (ret) { + of_node_put(child); return ret; + } pctl->nbanks++; } diff --git a/drivers/pinctrl/sunxi/pinctrl-sun8i-v3s.c b/drivers/pinctrl/sunxi/pinctrl-sun8i-v3s.c index 6704ce8e5e3d..ca85438e379a 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sun8i-v3s.c +++ b/drivers/pinctrl/sunxi/pinctrl-sun8i-v3s.c @@ -1,5 +1,5 @@ /* - * Allwinner V3s SoCs pinctrl driver. + * Allwinner V3/V3s SoCs pinctrl driver. * * Copyright (C) 2016 Icenowy Zheng <icenowy@aosc.xyz> * @@ -77,6 +77,30 @@ static const struct sunxi_desc_pin sun8i_v3s_pins[] = { SUNXI_FUNCTION(0x2, "i2c1"), /* SCK */ SUNXI_FUNCTION(0x3, "uart0"), /* RX */ SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 9)), /* PB_EINT9 */ + SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(B, 10), + PINCTRL_SUN8I_V3, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "jtag"), /* MS */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 10)), /* PB_EINT10 */ + SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(B, 11), + PINCTRL_SUN8I_V3, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "jtag"), /* CK */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 11)), /* PB_EINT11 */ + SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(B, 12), + PINCTRL_SUN8I_V3, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "jtag"), /* DO */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 12)), /* PB_EINT12 */ + SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(B, 13), + PINCTRL_SUN8I_V3, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "jtag"), /* DI */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 13)), /* PB_EINT13 */ /* Hole */ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 0), SUNXI_FUNCTION(0x0, "gpio_in"), @@ -98,6 +122,180 @@ static const struct sunxi_desc_pin sun8i_v3s_pins[] = { SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "mmc2"), /* D0 */ SUNXI_FUNCTION(0x3, "spi0")), /* MOSI */ + SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(C, 4), + PINCTRL_SUN8I_V3, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc2")), /* D1 */ + SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(C, 5), + PINCTRL_SUN8I_V3, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc2")), /* D2 */ + SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(C, 6), + PINCTRL_SUN8I_V3, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc2")), /* D3 */ + SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(C, 7), + PINCTRL_SUN8I_V3, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc2")), /* D4 */ + SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(C, 8), + PINCTRL_SUN8I_V3, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc2")), /* D5 */ + SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(C, 9), + PINCTRL_SUN8I_V3, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc2")), /* D6 */ + SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(C, 10), + PINCTRL_SUN8I_V3, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc2")), /* D7 */ + /* Hole */ + SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(D, 0), + PINCTRL_SUN8I_V3, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd"), /* D2 */ + SUNXI_FUNCTION(0x4, "emac")), /* RXD3 */ + SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(D, 1), + PINCTRL_SUN8I_V3, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd"), /* D3 */ + SUNXI_FUNCTION(0x4, "emac")), /* RXD2 */ + SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(D, 2), + PINCTRL_SUN8I_V3, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd"), /* D4 */ + SUNXI_FUNCTION(0x4, "emac")), /* RXD1 */ + SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(D, 3), + PINCTRL_SUN8I_V3, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd"), /* D5 */ + SUNXI_FUNCTION(0x4, "emac")), /* RXD0 */ + SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(D, 4), + PINCTRL_SUN8I_V3, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd"), /* D6 */ + SUNXI_FUNCTION(0x4, "emac")), /* RXCK */ + SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(D, 5), + PINCTRL_SUN8I_V3, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd"), /* D7 */ + SUNXI_FUNCTION(0x4, "emac")), /* RXCTL/RXDV */ + SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(D, 6), + PINCTRL_SUN8I_V3, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd"), /* D10 */ + SUNXI_FUNCTION(0x4, "emac")), /* RXERR */ + SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(D, 7), + PINCTRL_SUN8I_V3, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd"), /* D11 */ + SUNXI_FUNCTION(0x4, "emac")), /* TXD3 */ + SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(D, 8), + PINCTRL_SUN8I_V3, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd"), /* D12 */ + SUNXI_FUNCTION(0x4, "emac")), /* TXD2 */ + SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(D, 9), + PINCTRL_SUN8I_V3, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd"), /* D13 */ + SUNXI_FUNCTION(0x4, "emac")), /* TXD1 */ + SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(D, 10), + PINCTRL_SUN8I_V3, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd"), /* D14 */ + SUNXI_FUNCTION(0x4, "emac")), /* TXD0 */ + SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(D, 11), + PINCTRL_SUN8I_V3, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd"), /* D15 */ + SUNXI_FUNCTION(0x4, "emac")), /* CRS */ + SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(D, 12), + PINCTRL_SUN8I_V3, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd"), /* D18 */ + SUNXI_FUNCTION(0x3, "lvds"), /* VP0 */ + SUNXI_FUNCTION(0x4, "emac")), /* TXCK */ + SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(D, 13), + PINCTRL_SUN8I_V3, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd"), /* D19 */ + SUNXI_FUNCTION(0x3, "lvds"), /* VN0 */ + SUNXI_FUNCTION(0x4, "emac")), /* TXCTL/TXEN */ + SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(D, 14), + PINCTRL_SUN8I_V3, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd"), /* D20 */ + SUNXI_FUNCTION(0x3, "lvds"), /* VP1 */ + SUNXI_FUNCTION(0x4, "emac")), /* TXERR */ + SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(D, 15), + PINCTRL_SUN8I_V3, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd"), /* D21 */ + SUNXI_FUNCTION(0x3, "lvds"), /* VN1 */ + SUNXI_FUNCTION(0x4, "emac")), /* CLKIN/COL */ + SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(D, 16), + PINCTRL_SUN8I_V3, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd"), /* D22 */ + SUNXI_FUNCTION(0x3, "lvds"), /* VP2 */ + SUNXI_FUNCTION(0x4, "emac")), /* MDC */ + SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(D, 17), + PINCTRL_SUN8I_V3, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd"), /* D23 */ + SUNXI_FUNCTION(0x3, "lvds"), /* VN2 */ + SUNXI_FUNCTION(0x4, "emac")), /* MDIO */ + SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(D, 18), + PINCTRL_SUN8I_V3, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd"), /* CLK */ + SUNXI_FUNCTION(0x3, "lvds")), /* VPC */ + SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(D, 19), + PINCTRL_SUN8I_V3, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd"), /* DE */ + SUNXI_FUNCTION(0x3, "lvds")), /* VNC */ + SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(D, 20), + PINCTRL_SUN8I_V3, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd"), /* HSYNC */ + SUNXI_FUNCTION(0x3, "lvds")), /* VP3 */ + SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(D, 21), + PINCTRL_SUN8I_V3, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd"), /* VSYNC */ + SUNXI_FUNCTION(0x3, "lvds")), /* VN3 */ /* Hole */ SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 0), SUNXI_FUNCTION(0x0, "gpio_in"), @@ -291,6 +489,54 @@ static const struct sunxi_desc_pin sun8i_v3s_pins[] = { SUNXI_FUNCTION(0x1, "gpio_out"), SUNXI_FUNCTION(0x2, "mmc1"), /* D3 */ SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 5)), /* PG_EINT5 */ + SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(G, 6), + PINCTRL_SUN8I_V3, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "uart1"), /* TX */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 6)), /* PG_EINT6 */ + SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(G, 7), + PINCTRL_SUN8I_V3, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "uart1"), /* RX */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 7)), /* PG_EINT7 */ + SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(G, 8), + PINCTRL_SUN8I_V3, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "uart1"), /* RTS */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 8)), /* PG_EINT8 */ + SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(G, 9), + PINCTRL_SUN8I_V3, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "uart1"), /* CTS */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 9)), /* PG_EINT9 */ + SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(G, 10), + PINCTRL_SUN8I_V3, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2s"), /* SYNC */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 10)), /* PG_EINT10 */ + SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(G, 11), + PINCTRL_SUN8I_V3, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2s"), /* BCLK */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 11)), /* PG_EINT11 */ + SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(G, 12), + PINCTRL_SUN8I_V3, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2s"), /* DOUT */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 12)), /* PG_EINT12 */ + SUNXI_PIN_VARIANT(SUNXI_PINCTRL_PIN(G, 13), + PINCTRL_SUN8I_V3, + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2s"), /* DIN */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 13)), /* PG_EINT13 */ }; static const unsigned int sun8i_v3s_pinctrl_irq_bank_map[] = { 1, 2 }; @@ -305,13 +551,22 @@ static const struct sunxi_pinctrl_desc sun8i_v3s_pinctrl_data = { static int sun8i_v3s_pinctrl_probe(struct platform_device *pdev) { - return sunxi_pinctrl_init(pdev, - &sun8i_v3s_pinctrl_data); + unsigned long variant = (unsigned long)of_device_get_match_data(&pdev->dev); + + return sunxi_pinctrl_init_with_variant(pdev, &sun8i_v3s_pinctrl_data, + variant); } static const struct of_device_id sun8i_v3s_pinctrl_match[] = { - { .compatible = "allwinner,sun8i-v3s-pinctrl", }, - {} + { + .compatible = "allwinner,sun8i-v3-pinctrl", + .data = (void *)PINCTRL_SUN8I_V3 + }, + { + .compatible = "allwinner,sun8i-v3s-pinctrl", + .data = (void *)PINCTRL_SUN8I_V3S + }, + { }, }; static struct platform_driver sun8i_v3s_pinctrl_driver = { diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.h b/drivers/pinctrl/sunxi/pinctrl-sunxi.h index 44e30deeee38..a32bb5bcb754 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sunxi.h +++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.h @@ -94,6 +94,8 @@ #define PINCTRL_SUN4I_A10 BIT(6) #define PINCTRL_SUN7I_A20 BIT(7) #define PINCTRL_SUN8I_R40 BIT(8) +#define PINCTRL_SUN8I_V3 BIT(9) +#define PINCTRL_SUN8I_V3S BIT(10) #define PIO_POW_MOD_SEL_REG 0x340 diff --git a/drivers/pinctrl/tegra/pinctrl-tegra.c b/drivers/pinctrl/tegra/pinctrl-tegra.c index 186ef98e7b2b..e9a7cbb9aa33 100644 --- a/drivers/pinctrl/tegra/pinctrl-tegra.c +++ b/drivers/pinctrl/tegra/pinctrl-tegra.c @@ -32,7 +32,9 @@ static inline u32 pmx_readl(struct tegra_pmx *pmx, u32 bank, u32 reg) static inline void pmx_writel(struct tegra_pmx *pmx, u32 val, u32 bank, u32 reg) { - writel(val, pmx->regs[bank] + reg); + writel_relaxed(val, pmx->regs[bank] + reg); + /* make sure pinmux register write completed */ + pmx_readl(pmx, bank, reg); } static int tegra_pinctrl_get_groups_count(struct pinctrl_dev *pctldev) @@ -631,6 +633,62 @@ static void tegra_pinctrl_clear_parked_bits(struct tegra_pmx *pmx) } } +static size_t tegra_pinctrl_get_bank_size(struct device *dev, + unsigned int bank_id) +{ + struct platform_device *pdev = to_platform_device(dev); + struct resource *res; + + res = platform_get_resource(pdev, IORESOURCE_MEM, bank_id); + + return resource_size(res) / 4; +} + +static int tegra_pinctrl_suspend(struct device *dev) +{ + struct tegra_pmx *pmx = dev_get_drvdata(dev); + u32 *backup_regs = pmx->backup_regs; + u32 *regs; + size_t bank_size; + unsigned int i, k; + + for (i = 0; i < pmx->nbanks; i++) { + bank_size = tegra_pinctrl_get_bank_size(dev, i); + regs = pmx->regs[i]; + for (k = 0; k < bank_size; k++) + *backup_regs++ = readl_relaxed(regs++); + } + + return pinctrl_force_sleep(pmx->pctl); +} + +static int tegra_pinctrl_resume(struct device *dev) +{ + struct tegra_pmx *pmx = dev_get_drvdata(dev); + u32 *backup_regs = pmx->backup_regs; + u32 *regs; + size_t bank_size; + unsigned int i, k; + + for (i = 0; i < pmx->nbanks; i++) { + bank_size = tegra_pinctrl_get_bank_size(dev, i); + regs = pmx->regs[i]; + for (k = 0; k < bank_size; k++) + writel_relaxed(*backup_regs++, regs++); + } + + /* flush all the prior writes */ + readl_relaxed(pmx->regs[0]); + /* wait for pinctrl register read to complete */ + rmb(); + return 0; +} + +const struct dev_pm_ops tegra_pinctrl_pm = { + .suspend = &tegra_pinctrl_suspend, + .resume = &tegra_pinctrl_resume +}; + static bool gpio_node_has_range(const char *compatible) { struct device_node *np; @@ -655,6 +713,7 @@ int tegra_pinctrl_probe(struct platform_device *pdev, int i; const char **group_pins; int fn, gn, gfn; + unsigned long backup_regs_size = 0; pmx = devm_kzalloc(&pdev->dev, sizeof(*pmx), GFP_KERNEL); if (!pmx) @@ -707,6 +766,7 @@ int tegra_pinctrl_probe(struct platform_device *pdev, res = platform_get_resource(pdev, IORESOURCE_MEM, i); if (!res) break; + backup_regs_size += resource_size(res); } pmx->nbanks = i; @@ -715,6 +775,11 @@ int tegra_pinctrl_probe(struct platform_device *pdev, if (!pmx->regs) return -ENOMEM; + pmx->backup_regs = devm_kzalloc(&pdev->dev, backup_regs_size, + GFP_KERNEL); + if (!pmx->backup_regs) + return -ENOMEM; + for (i = 0; i < pmx->nbanks; i++) { res = platform_get_resource(pdev, IORESOURCE_MEM, i); pmx->regs[i] = devm_ioremap_resource(&pdev->dev, res); diff --git a/drivers/pinctrl/tegra/pinctrl-tegra.h b/drivers/pinctrl/tegra/pinctrl-tegra.h index 105309774079..0fc82eea9cf1 100644 --- a/drivers/pinctrl/tegra/pinctrl-tegra.h +++ b/drivers/pinctrl/tegra/pinctrl-tegra.h @@ -17,6 +17,7 @@ struct tegra_pmx { int nbanks; void __iomem **regs; + u32 *backup_regs; }; enum tegra_pinconf_param { @@ -193,6 +194,8 @@ struct tegra_pinctrl_soc_data { bool drvtype_in_mux; }; +extern const struct dev_pm_ops tegra_pinctrl_pm; + int tegra_pinctrl_probe(struct platform_device *pdev, const struct tegra_pinctrl_soc_data *soc_data); #endif diff --git a/drivers/pinctrl/tegra/pinctrl-tegra210.c b/drivers/pinctrl/tegra/pinctrl-tegra210.c index 39ab6480a941..fc072a36deb3 100644 --- a/drivers/pinctrl/tegra/pinctrl-tegra210.c +++ b/drivers/pinctrl/tegra/pinctrl-tegra210.c @@ -1571,6 +1571,7 @@ static struct platform_driver tegra210_pinctrl_driver = { .driver = { .name = "tegra210-pinctrl", .of_match_table = tegra210_pinctrl_of_match, + .pm = &tegra_pinctrl_pm, }, .probe = tegra210_pinctrl_probe, }; diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-ld11.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-ld11.c index 92fef3ae1177..c390a551d6dd 100644 --- a/drivers/pinctrl/uniphier/pinctrl-uniphier-ld11.c +++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-ld11.c @@ -526,8 +526,10 @@ static const unsigned uart2_pins[] = {90, 91}; static const int uart2_muxvals[] = {1, 1}; static const unsigned uart3_pins[] = {94, 95}; static const int uart3_muxvals[] = {1, 1}; -static const unsigned uart3_ctsrts_pins[] = {96, 97, 98, 99, 100, 101}; -static const int uart3_ctsrts_muxvals[] = {1, 1, 1, 1, 1, 1}; +static const unsigned uart3_ctsrts_pins[] = {96, 98}; +static const int uart3_ctsrts_muxvals[] = {1, 1}; +static const unsigned uart3_modem_pins[] = {97, 99, 100, 101}; +static const int uart3_modem_muxvals[] = {1, 1, 1, 1}; static const unsigned usb0_pins[] = {46, 47}; static const int usb0_muxvals[] = {0, 0}; static const unsigned usb1_pins[] = {48, 49}; @@ -600,6 +602,7 @@ static const struct uniphier_pinctrl_group uniphier_ld11_groups[] = { UNIPHIER_PINCTRL_GROUP(uart2), UNIPHIER_PINCTRL_GROUP(uart3), UNIPHIER_PINCTRL_GROUP(uart3_ctsrts), + UNIPHIER_PINCTRL_GROUP(uart3_modem), UNIPHIER_PINCTRL_GROUP(usb0), UNIPHIER_PINCTRL_GROUP(usb1), UNIPHIER_PINCTRL_GROUP(usb2), @@ -636,7 +639,8 @@ static const char * const system_bus_groups[] = {"system_bus", static const char * const uart0_groups[] = {"uart0"}; static const char * const uart1_groups[] = {"uart1"}; static const char * const uart2_groups[] = {"uart2"}; -static const char * const uart3_groups[] = {"uart3", "uart3_ctsrts"}; +static const char * const uart3_groups[] = {"uart3", "uart3_ctsrts", + "uart3_modem"}; static const char * const usb0_groups[] = {"usb0"}; static const char * const usb1_groups[] = {"usb1"}; static const char * const usb2_groups[] = {"usb2"}; diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-ld20.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-ld20.c index 7fbc9652b134..0a8b1867057b 100644 --- a/drivers/pinctrl/uniphier/pinctrl-uniphier-ld20.c +++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-ld20.c @@ -544,6 +544,8 @@ static const struct pinctrl_pin_desc uniphier_ld20_pins[] = { static const unsigned aout1_pins[] = {137, 138, 139, 140, 141, 142}; static const int aout1_muxvals[] = {0, 0, 0, 0, 0, 0}; +static const unsigned aout1b_pins[] = {150, 151, 152, 153, 154, 155, 156}; +static const int aout1b_muxvals[] = {1, 1, 1, 1, 1, 1, 1}; static const unsigned aoutiec1_pins[] = {135, 136}; static const int aoutiec1_muxvals[] = {0, 0}; static const unsigned int emmc_pins[] = {19, 20, 21, 22, 23, 24, 25}; @@ -574,6 +576,8 @@ static const unsigned hscin2_s_pins[] = {124, 125, 126, 127}; static const int hscin2_s_muxvals[] = {3, 3, 3, 3}; static const unsigned hscin3_s_pins[] = {129, 130, 131, 132}; static const int hscin3_s_muxvals[] = {3, 3, 3, 3}; +static const unsigned hscin4_s_pins[] = {80, 81, 82, 83}; +static const int hscin4_s_muxvals[] = {3, 3, 3, 3}; static const unsigned hscout0_ci_pins[] = {113, 114, 115, 116, 117, 118, 119, 120, 121, 122, 123}; static const int hscout0_ci_muxvals[] = {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1}; @@ -619,8 +623,10 @@ static const unsigned uart2_pins[] = {90, 91}; static const int uart2_muxvals[] = {1, 1}; static const unsigned uart3_pins[] = {94, 95}; static const int uart3_muxvals[] = {1, 1}; -static const unsigned uart3_ctsrts_pins[] = {96, 97, 98, 99, 100, 101}; -static const int uart3_ctsrts_muxvals[] = {1, 1, 1, 1, 1, 1}; +static const unsigned uart3_ctsrts_pins[] = {96, 98}; +static const int uart3_ctsrts_muxvals[] = {1, 1}; +static const unsigned uart3_modem_pins[] = {97, 99, 100, 101}; +static const int uart3_modem_muxvals[] = {1, 1, 1, 1}; static const unsigned usb0_pins[] = {46, 47}; static const int usb0_muxvals[] = {0, 0}; static const unsigned usb1_pins[] = {48, 49}; @@ -662,6 +668,7 @@ static const unsigned int gpio_range2_pins[] = { static const struct uniphier_pinctrl_group uniphier_ld20_groups[] = { UNIPHIER_PINCTRL_GROUP(aout1), + UNIPHIER_PINCTRL_GROUP(aout1b), UNIPHIER_PINCTRL_GROUP(aoutiec1), UNIPHIER_PINCTRL_GROUP(emmc), UNIPHIER_PINCTRL_GROUP(emmc_dat8), @@ -674,6 +681,7 @@ static const struct uniphier_pinctrl_group uniphier_ld20_groups[] = { UNIPHIER_PINCTRL_GROUP(hscin1_s), UNIPHIER_PINCTRL_GROUP(hscin2_s), UNIPHIER_PINCTRL_GROUP(hscin3_s), + UNIPHIER_PINCTRL_GROUP(hscin4_s), UNIPHIER_PINCTRL_GROUP(hscout0_ci), UNIPHIER_PINCTRL_GROUP(hscout0_p), UNIPHIER_PINCTRL_GROUP(hscout0_s), @@ -695,6 +703,7 @@ static const struct uniphier_pinctrl_group uniphier_ld20_groups[] = { UNIPHIER_PINCTRL_GROUP(uart2), UNIPHIER_PINCTRL_GROUP(uart3), UNIPHIER_PINCTRL_GROUP(uart3_ctsrts), + UNIPHIER_PINCTRL_GROUP(uart3_modem), UNIPHIER_PINCTRL_GROUP(usb0), UNIPHIER_PINCTRL_GROUP(usb1), UNIPHIER_PINCTRL_GROUP(usb2), @@ -704,7 +713,7 @@ static const struct uniphier_pinctrl_group uniphier_ld20_groups[] = { UNIPHIER_PINCTRL_GROUP_GPIO(gpio_range2), }; -static const char * const aout1_groups[] = {"aout1"}; +static const char * const aout1_groups[] = {"aout1", "aout1b"}; static const char * const aoutiec1_groups[] = {"aoutiec1"}; static const char * const emmc_groups[] = {"emmc", "emmc_dat8"}; static const char * const ether_rgmii_groups[] = {"ether_rgmii"}; @@ -715,6 +724,7 @@ static const char * const hscin0_groups[] = {"hscin0_ci", static const char * const hscin1_groups[] = {"hscin1_p", "hscin1_s"}; static const char * const hscin2_groups[] = {"hscin2_s"}; static const char * const hscin3_groups[] = {"hscin3_s"}; +static const char * const hscin4_groups[] = {"hscin4_s"}; static const char * const hscout0_groups[] = {"hscout0_ci", "hscout0_p", "hscout0_s"}; @@ -734,7 +744,8 @@ static const char * const system_bus_groups[] = {"system_bus", static const char * const uart0_groups[] = {"uart0"}; static const char * const uart1_groups[] = {"uart1"}; static const char * const uart2_groups[] = {"uart2"}; -static const char * const uart3_groups[] = {"uart3", "uart3_ctsrts"}; +static const char * const uart3_groups[] = {"uart3", "uart3_ctsrts", + "uart3_modem"}; static const char * const usb0_groups[] = {"usb0"}; static const char * const usb1_groups[] = {"usb1"}; static const char * const usb2_groups[] = {"usb2"}; @@ -750,6 +761,7 @@ static const struct uniphier_pinmux_function uniphier_ld20_functions[] = { UNIPHIER_PINMUX_FUNCTION(hscin1), UNIPHIER_PINMUX_FUNCTION(hscin2), UNIPHIER_PINMUX_FUNCTION(hscin3), + UNIPHIER_PINMUX_FUNCTION(hscin4), UNIPHIER_PINMUX_FUNCTION(hscout0), UNIPHIER_PINMUX_FUNCTION(hscout1), UNIPHIER_PINMUX_FUNCTION(i2c0), diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-ld4.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-ld4.c index d09019bfbb1a..88fd68f86a85 100644 --- a/drivers/pinctrl/uniphier/pinctrl-uniphier-ld4.c +++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-ld4.c @@ -583,8 +583,10 @@ static const unsigned system_bus_cs3_pins[] = {156}; static const int system_bus_cs3_muxvals[] = {1}; static const unsigned uart0_pins[] = {85, 88}; static const int uart0_muxvals[] = {1, 1}; -static const unsigned uart0_ctsrts_pins[] = {86, 87, 89}; -static const int uart0_ctsrts_muxvals[] = {1, 1, 1}; +static const unsigned uart0_ctsrts_pins[] = {86, 89}; +static const int uart0_ctsrts_muxvals[] = {1, 1}; +static const unsigned uart0_modem_pins[] = {87}; +static const int uart0_modem_muxvals[] = {1}; static const unsigned uart1_pins[] = {155, 156}; static const int uart1_muxvals[] = {13, 13}; static const unsigned uart1b_pins[] = {69, 70}; @@ -641,6 +643,7 @@ static const struct uniphier_pinctrl_group uniphier_ld4_groups[] = { UNIPHIER_PINCTRL_GROUP(system_bus_cs3), UNIPHIER_PINCTRL_GROUP(uart0), UNIPHIER_PINCTRL_GROUP(uart0_ctsrts), + UNIPHIER_PINCTRL_GROUP(uart0_modem), UNIPHIER_PINCTRL_GROUP(uart1), UNIPHIER_PINCTRL_GROUP(uart1b), UNIPHIER_PINCTRL_GROUP(uart2), @@ -667,7 +670,8 @@ static const char * const system_bus_groups[] = {"system_bus", "system_bus_cs1", "system_bus_cs2", "system_bus_cs3"}; -static const char * const uart0_groups[] = {"uart0", "uart0_ctsrts"}; +static const char * const uart0_groups[] = {"uart0", "uart0_ctsrts", + "uart0_modem"}; static const char * const uart1_groups[] = {"uart1", "uart1b"}; static const char * const uart2_groups[] = {"uart2"}; static const char * const uart3_groups[] = {"uart3"}; diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-ld6b.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-ld6b.c index 414ff3aee67b..374c029ebc02 100644 --- a/drivers/pinctrl/uniphier/pinctrl-uniphier-ld6b.c +++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-ld6b.c @@ -780,8 +780,10 @@ static const unsigned system_bus_cs5_pins[] = {55}; static const int system_bus_cs5_muxvals[] = {6}; static const unsigned uart0_pins[] = {135, 136}; static const int uart0_muxvals[] = {3, 3}; -static const unsigned uart0_ctsrts_pins[] = {137, 138, 139, 140, 141, 124}; -static const int uart0_ctsrts_muxvals[] = {3, 3, 3, 3, 3, 3}; +static const unsigned uart0_ctsrts_pins[] = {137, 139}; +static const int uart0_ctsrts_muxvals[] = {3, 3}; +static const unsigned uart0_modem_pins[] = {124, 138, 140, 141}; +static const int uart0_modem_muxvals[] = {3, 3, 3, 3}; static const unsigned uart0b_pins[] = {11, 12}; static const int uart0b_muxvals[] = {2, 2}; static const unsigned uart1_pins[] = {115, 116}; @@ -856,6 +858,7 @@ static const struct uniphier_pinctrl_group uniphier_ld6b_groups[] = { UNIPHIER_PINCTRL_GROUP(system_bus_cs5), UNIPHIER_PINCTRL_GROUP(uart0), UNIPHIER_PINCTRL_GROUP(uart0_ctsrts), + UNIPHIER_PINCTRL_GROUP(uart0_modem), UNIPHIER_PINCTRL_GROUP(uart0b), UNIPHIER_PINCTRL_GROUP(uart1), UNIPHIER_PINCTRL_GROUP(uart1b), @@ -887,7 +890,8 @@ static const char * const system_bus_groups[] = {"system_bus", "system_bus_cs3", "system_bus_cs4", "system_bus_cs5"}; -static const char * const uart0_groups[] = {"uart0", "uart0_ctsrts", "uart0b"}; +static const char * const uart0_groups[] = {"uart0", "uart0_ctsrts", + "uart0_modem", "uart0b"}; static const char * const uart1_groups[] = {"uart1", "uart1b"}; static const char * const uart2_groups[] = {"uart2", "uart2b"}; static const char * const usb0_groups[] = {"usb0"}; diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-pro4.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-pro4.c index 919b9bec2027..4f63d7b1a252 100644 --- a/drivers/pinctrl/uniphier/pinctrl-uniphier-pro4.c +++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-pro4.c @@ -1072,8 +1072,10 @@ static const unsigned uart2_pins[] = {131, 132}; static const int uart2_muxvals[] = {0, 0}; static const unsigned uart3_pins[] = {88, 89}; static const int uart3_muxvals[] = {2, 2}; -static const unsigned uart3_ctsrts_pins[] = {80, 81, 82, 83, 90, 91}; -static const int uart3_ctsrts_muxvals[] = {2, 2, 2, 2, 2, 2}; +static const unsigned uart3_ctsrts_pins[] = {90, 91}; +static const int uart3_ctsrts_muxvals[] = {2, 2}; +static const unsigned uart3_modem_pins[] = {80, 81, 82, 83}; +static const int uart3_modem_muxvals[] = {2, 2, 2, 2}; static const unsigned usb0_pins[] = {180, 181}; static const int usb0_muxvals[] = {0, 0}; static const unsigned usb1_pins[] = {182, 183}; @@ -1148,6 +1150,7 @@ static const struct uniphier_pinctrl_group uniphier_pro4_groups[] = { UNIPHIER_PINCTRL_GROUP(uart2), UNIPHIER_PINCTRL_GROUP(uart3), UNIPHIER_PINCTRL_GROUP(uart3_ctsrts), + UNIPHIER_PINCTRL_GROUP(uart3_modem), UNIPHIER_PINCTRL_GROUP(usb0), UNIPHIER_PINCTRL_GROUP(usb1), UNIPHIER_PINCTRL_GROUP(usb2), @@ -1181,7 +1184,8 @@ static const char * const system_bus_groups[] = {"system_bus", static const char * const uart0_groups[] = {"uart0"}; static const char * const uart1_groups[] = {"uart1"}; static const char * const uart2_groups[] = {"uart2"}; -static const char * const uart3_groups[] = {"uart3", "uart3_ctsrts"}; +static const char * const uart3_groups[] = {"uart3", "uart3_ctsrts", + "uart3_modem"}; static const char * const usb0_groups[] = {"usb0"}; static const char * const usb1_groups[] = {"usb1"}; static const char * const usb2_groups[] = {"usb2"}; diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-pro5.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-pro5.c index 4a6580da4edb..4277d494a348 100644 --- a/drivers/pinctrl/uniphier/pinctrl-uniphier-pro5.c +++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-pro5.c @@ -807,7 +807,9 @@ static const unsigned nand_pins[] = {19, 20, 21, 22, 23, 24, 25, 28, 29, 30, static const int nand_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; static const unsigned nand_cs1_pins[] = {26, 27}; static const int nand_cs1_muxvals[] = {0, 0}; -static const unsigned sd_pins[] = {250, 251, 252, 253, 254, 255, 256, 257, 258}; +static const unsigned pcie_pins[] = {109, 110, 111}; +static const int pcie_muxvals[] = {0, 0, 0}; +static const unsigned sd_pins[] = {247, 248, 249, 250, 251, 252, 253, 254, 255}; static const int sd_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0, 0}; static const unsigned spi0_pins[] = {120, 121, 122, 123}; static const int spi0_muxvals[] = {0, 0, 0, 0}; @@ -839,8 +841,10 @@ static const unsigned uart0_pins[] = {47, 48}; static const int uart0_muxvals[] = {0, 0}; static const unsigned uart0b_pins[] = {227, 228}; static const int uart0b_muxvals[] = {3, 3}; -static const unsigned uart0b_ctsrts_pins[] = {229, 230, 231, 232, 233, 234}; -static const int uart0b_ctsrts_muxvals[] = {3, 3, 3, 3, 3, 3}; +static const unsigned uart0b_ctsrts_pins[] = {232, 233}; +static const int uart0b_ctsrts_muxvals[] = {3, 3}; +static const unsigned uart0b_modem_pins[] = {229, 230, 231, 234}; +static const int uart0b_modem_muxvals[] = {3, 3, 3, 3}; static const unsigned uart1_pins[] = {49, 50}; static const int uart1_muxvals[] = {0, 0}; static const unsigned uart2_pins[] = {51, 52}; @@ -900,6 +904,7 @@ static const struct uniphier_pinctrl_group uniphier_pro5_groups[] = { UNIPHIER_PINCTRL_GROUP(i2c5b), UNIPHIER_PINCTRL_GROUP(i2c5c), UNIPHIER_PINCTRL_GROUP(i2c6), + UNIPHIER_PINCTRL_GROUP(pcie), UNIPHIER_PINCTRL_GROUP(sd), UNIPHIER_PINCTRL_GROUP(spi0), UNIPHIER_PINCTRL_GROUP(spi1), @@ -916,6 +921,7 @@ static const struct uniphier_pinctrl_group uniphier_pro5_groups[] = { UNIPHIER_PINCTRL_GROUP(uart0), UNIPHIER_PINCTRL_GROUP(uart0b), UNIPHIER_PINCTRL_GROUP(uart0b_ctsrts), + UNIPHIER_PINCTRL_GROUP(uart0b_modem), UNIPHIER_PINCTRL_GROUP(uart1), UNIPHIER_PINCTRL_GROUP(uart2), UNIPHIER_PINCTRL_GROUP(uart3), @@ -933,6 +939,7 @@ static const char * const i2c3_groups[] = {"i2c3"}; static const char * const i2c5_groups[] = {"i2c5", "i2c5b", "i2c5c"}; static const char * const i2c6_groups[] = {"i2c6"}; static const char * const nand_groups[] = {"nand", "nand_cs1"}; +static const char * const pcie_groups[] = {"pcie"}; static const char * const sd_groups[] = {"sd"}; static const char * const spi0_groups[] = {"spi0"}; static const char * const spi1_groups[] = {"spi1"}; @@ -946,7 +953,8 @@ static const char * const system_bus_groups[] = {"system_bus", "system_bus_cs5", "system_bus_cs6", "system_bus_cs7"}; -static const char * const uart0_groups[] = {"uart0", "uart0b", "uart0b_ctsrts"}; +static const char * const uart0_groups[] = {"uart0", "uart0b", + "uart0b_ctsrts", "uart0b_modem"}; static const char * const uart1_groups[] = {"uart1"}; static const char * const uart2_groups[] = {"uart2"}; static const char * const uart3_groups[] = {"uart3"}; @@ -963,6 +971,7 @@ static const struct uniphier_pinmux_function uniphier_pro5_functions[] = { UNIPHIER_PINMUX_FUNCTION(i2c5), UNIPHIER_PINMUX_FUNCTION(i2c6), UNIPHIER_PINMUX_FUNCTION(nand), + UNIPHIER_PINMUX_FUNCTION(pcie), UNIPHIER_PINMUX_FUNCTION(sd), UNIPHIER_PINMUX_FUNCTION(spi0), UNIPHIER_PINMUX_FUNCTION(spi1), diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-pxs2.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-pxs2.c index 169bb4489bc7..e52e65a24048 100644 --- a/drivers/pinctrl/uniphier/pinctrl-uniphier-pxs2.c +++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-pxs2.c @@ -783,8 +783,10 @@ static const unsigned uart0_pins[] = {217, 218}; static const int uart0_muxvals[] = {8, 8}; static const unsigned uart0b_pins[] = {179, 180}; static const int uart0b_muxvals[] = {10, 10}; -static const unsigned uart0b_ctsrts_pins[] = {176, 177, 178, 183, 184, 185}; -static const int uart0b_ctsrts_muxvals[] = {10, 10, 10, 10, 10, 10}; +static const unsigned uart0b_ctsrts_pins[] = {183, 185}; +static const int uart0b_ctsrts_muxvals[] = {10, 10}; +static const unsigned uart0b_modem_pins[] = {176, 177, 178, 184}; +static const int uart0b_modem_muxvals[] = {10, 10, 10, 10}; static const unsigned uart1_pins[] = {115, 116}; static const int uart1_muxvals[] = {8, 8}; static const unsigned uart2_pins[] = {113, 114}; @@ -863,6 +865,7 @@ static const struct uniphier_pinctrl_group uniphier_pxs2_groups[] = { UNIPHIER_PINCTRL_GROUP(uart0), UNIPHIER_PINCTRL_GROUP(uart0b), UNIPHIER_PINCTRL_GROUP(uart0b_ctsrts), + UNIPHIER_PINCTRL_GROUP(uart0b_modem), UNIPHIER_PINCTRL_GROUP(uart1), UNIPHIER_PINCTRL_GROUP(uart2), UNIPHIER_PINCTRL_GROUP(uart3), @@ -898,7 +901,8 @@ static const char * const spi0_groups[] = {"spi0"}; static const char * const spi1_groups[] = {"spi1"}; static const char * const system_bus_groups[] = {"system_bus", "system_bus_cs1"}; -static const char * const uart0_groups[] = {"uart0", "uart0b", "uart0b_ctsrts"}; +static const char * const uart0_groups[] = {"uart0", "uart0b", + "uart0b_ctsrts", "uart0b_modem"}; static const char * const uart1_groups[] = {"uart1"}; static const char * const uart2_groups[] = {"uart2"}; static const char * const uart3_groups[] = {"uart3", "uart3b"}; diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-pxs3.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-pxs3.c index 3dc3e5b1e80c..2b388fdcca3a 100644 --- a/drivers/pinctrl/uniphier/pinctrl-uniphier-pxs3.c +++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-pxs3.c @@ -811,8 +811,10 @@ static const unsigned int system_bus_cs1_pins[] = {15}; static const int system_bus_cs1_muxvals[] = {0}; static const unsigned int uart0_pins[] = {92, 93}; static const int uart0_muxvals[] = {0, 0}; -static const unsigned int uart0_ctsrts_pins[] = {243, 244, 245, 246, 247, 248}; -static const int uart0_ctsrts_muxvals[] = {3, 3, 3, 3, 3, 3}; +static const unsigned int uart0_ctsrts_pins[] = {243, 247}; +static const int uart0_ctsrts_muxvals[] = {3, 3}; +static const unsigned int uart0_modem_pins[] = {244, 245, 246, 248}; +static const int uart0_modem_muxvals[] = {3, 3, 3, 3}; static const unsigned int uart1_pins[] = {94, 95}; static const int uart1_muxvals[] = {0, 0}; static const unsigned int uart2_pins[] = {96, 97}; @@ -887,6 +889,7 @@ static const struct uniphier_pinctrl_group uniphier_pxs3_groups[] = { UNIPHIER_PINCTRL_GROUP(system_bus_cs1), UNIPHIER_PINCTRL_GROUP(uart0), UNIPHIER_PINCTRL_GROUP(uart0_ctsrts), + UNIPHIER_PINCTRL_GROUP(uart0_modem), UNIPHIER_PINCTRL_GROUP(uart1), UNIPHIER_PINCTRL_GROUP(uart2), UNIPHIER_PINCTRL_GROUP(uart3), @@ -914,7 +917,8 @@ static const char * const spi0_groups[] = {"spi0"}; static const char * const spi1_groups[] = {"spi1"}; static const char * const system_bus_groups[] = {"system_bus", "system_bus_cs1"}; -static const char * const uart0_groups[] = {"uart0", "uart0_ctsrts"}; +static const char * const uart0_groups[] = {"uart0", "uart0_ctsrts", + "uart0_modem"}; static const char * const uart1_groups[] = {"uart1"}; static const char * const uart2_groups[] = {"uart2"}; static const char * const uart3_groups[] = {"uart3"}; diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-sld8.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-sld8.c index 463e9324ab54..087e8db8f11d 100644 --- a/drivers/pinctrl/uniphier/pinctrl-uniphier-sld8.c +++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-sld8.c @@ -513,8 +513,10 @@ static const unsigned system_bus_cs5_pins[] = {13}; static const int system_bus_cs5_muxvals[] = {1}; static const unsigned uart0_pins[] = {70, 71}; static const int uart0_muxvals[] = {3, 3}; -static const unsigned uart0_ctsrts_pins[] = {72, 73, 74}; -static const int uart0_ctsrts_muxvals[] = {3, 3, 3}; +static const unsigned uart0_ctsrts_pins[] = {72, 74}; +static const int uart0_ctsrts_muxvals[] = {3, 3}; +static const unsigned uart0_modem_pins[] = {73}; +static const int uart0_modem_muxvals[] = {3}; static const unsigned uart1_pins[] = {114, 115}; static const int uart1_muxvals[] = {0, 0}; static const unsigned uart2_pins[] = {112, 113}; @@ -572,6 +574,7 @@ static const struct uniphier_pinctrl_group uniphier_sld8_groups[] = { UNIPHIER_PINCTRL_GROUP(system_bus_cs5), UNIPHIER_PINCTRL_GROUP(uart0), UNIPHIER_PINCTRL_GROUP(uart0_ctsrts), + UNIPHIER_PINCTRL_GROUP(uart0_modem), UNIPHIER_PINCTRL_GROUP(uart1), UNIPHIER_PINCTRL_GROUP(uart2), UNIPHIER_PINCTRL_GROUP(uart3), @@ -599,7 +602,8 @@ static const char * const system_bus_groups[] = {"system_bus", "system_bus_cs3", "system_bus_cs4", "system_bus_cs5"}; -static const char * const uart0_groups[] = {"uart0", "uart0_ctsrts"}; +static const char * const uart0_groups[] = {"uart0", "uart0_ctsrts", + "uart0_modem"}; static const char * const uart1_groups[] = {"uart1"}; static const char * const uart2_groups[] = {"uart2"}; static const char * const uart3_groups[] = {"uart3"}; diff --git a/include/linux/pinctrl/consumer.h b/include/linux/pinctrl/consumer.h index 86720a5a384f..7f8c7d9583d3 100644 --- a/include/linux/pinctrl/consumer.h +++ b/include/linux/pinctrl/consumer.h @@ -24,6 +24,7 @@ struct device; #ifdef CONFIG_PINCTRL /* External interface to pin control */ +extern bool pinctrl_gpio_can_use_line(unsigned gpio); extern int pinctrl_gpio_request(unsigned gpio); extern void pinctrl_gpio_free(unsigned gpio); extern int pinctrl_gpio_direction_input(unsigned gpio); @@ -61,6 +62,11 @@ static inline int pinctrl_pm_select_idle_state(struct device *dev) #else /* !CONFIG_PINCTRL */ +static inline bool pinctrl_gpio_can_use_line(unsigned gpio) +{ + return true; +} + static inline int pinctrl_gpio_request(unsigned gpio) { return 0; diff --git a/include/linux/platform_data/pinctrl-single.h b/include/linux/platform_data/pinctrl-single.h index 1cf36fdf9510..7473d3c4cabf 100644 --- a/include/linux/platform_data/pinctrl-single.h +++ b/include/linux/platform_data/pinctrl-single.h @@ -1,4 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0 */ + +#ifndef _PINCTRL_SINGLE_H +#define _PINCTRL_SINGLE_H + /** * irq: optional wake-up interrupt * rearm: optional soc specific rearm function @@ -11,3 +15,5 @@ struct pcs_pdata { int irq; void (*rearm)(void); }; + +#endif /* _PINCTRL_SINGLE_H */ |