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| author |   Leo Yan <leo.yan@linaro.org> | 2020-11-19 23:24:39 +0800 |
|---|---|---|
| committer |   Arnaldo Carvalho de Melo <acme@redhat.com> | 2020-11-26 09:31:46 -0300 |
| commit | 3d829724b16c5d2de42e6c9601c696c93a10bc61 (patch) | |
| tree | ffae409c729814a45fbde71ea23eb829d27170e2 | |
| parent | perf arm-spe: Refactor operation packet handling (diff) | |
| download | linux-dev-3d829724b16c5d2de42e6c9601c696c93a10bc61.tar.xz linux-dev-3d829724b16c5d2de42e6c9601c696c93a10bc61.zip | |
perf arm-spe: Add more sub classes for operation packet
For the operation type packet payload with load/store class, it misses
to support these sub classes:
- A load/store targeting the general-purpose registers;
- A load/store targeting unspecified registers;
- The ARMv8.4 nested virtualisation extension can redirect system
register accesses to a memory page controlled by the hypervisor.
The SPE profiling feature in newer implementations can tag those
memory accesses accordingly.
Add the bit pattern describing load/store sub classes, so that the perf
tool can decode it properly.
Inspired by Andre Przywara, refined the commit log and code for more
clear description.
Co-developed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Leo Yan <leo.yan@linaro.org>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Will Deacon <will@kernel.org>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Al Grant <Al.Grant@arm.com>
Cc: Arnaldo Carvalho de Melo <acme@kernel.org>
Cc: Dave Martin <Dave.Martin@arm.com>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: James Clark <james.clark@arm.com>
Cc: Jiri Olsa <jolsa@redhat.com>
Cc: John Garry <john.garry@huawei.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Wei Li <liwei391@huawei.com>
Link: https://lore.kernel.org/r/20201119152441.6972-15-leo.yan@linaro.org
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
| -rw-r--r-- | tools/perf/util/arm-spe-decoder/arm-spe-pkt-decoder.c | 18 |
1 files changed, 16 insertions, 2 deletions
diff --git a/tools/perf/util/arm-spe-decoder/arm-spe-pkt-decoder.c b/tools/perf/util/arm-spe-decoder/arm-spe-pkt-decoder.c index 1d1354a0eef4..84d661aab54f 100644 --- a/tools/perf/util/arm-spe-decoder/arm-spe-pkt-decoder.c +++ b/tools/perf/util/arm-spe-decoder/arm-spe-pkt-decoder.c @@ -343,9 +343,23 @@ static int arm_spe_pkt_desc_op_type(const struct arm_spe_pkt *packet, arm_spe_pkt_out_string(&err, &buf, &buf_len, " EXCL"); if (payload & SPE_OP_PKT_AR) arm_spe_pkt_out_string(&err, &buf, &buf_len, " AR"); - } else if (SPE_OP_PKT_LDST_SUBCLASS_GET(payload) == - SPE_OP_PKT_LDST_SUBCLASS_SIMD_FP) { + } + + switch (SPE_OP_PKT_LDST_SUBCLASS_GET(payload)) { + case SPE_OP_PKT_LDST_SUBCLASS_SIMD_FP: arm_spe_pkt_out_string(&err, &buf, &buf_len, " SIMD-FP"); + break; + case SPE_OP_PKT_LDST_SUBCLASS_GP_REG: + arm_spe_pkt_out_string(&err, &buf, &buf_len, " GP-REG"); + break; + case SPE_OP_PKT_LDST_SUBCLASS_UNSPEC_REG: + arm_spe_pkt_out_string(&err, &buf, &buf_len, " UNSPEC-REG"); + break; + case SPE_OP_PKT_LDST_SUBCLASS_NV_SYSREG: + arm_spe_pkt_out_string(&err, &buf, &buf_len, " NV-SYSREG"); + break; + default: + break; } break; case SPE_OP_PKT_HDR_CLASS_BR_ERET: |