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| author |   Joseph Lo <josephl@nvidia.com> | 2019-01-04 11:06:57 +0800 |
|---|---|---|
| committer |   Thierry Reding <treding@nvidia.com> | 2019-02-07 19:03:09 +0100 |
| commit | 43b9b402f491cb488eb1d1b2608718585cecfd72 (patch) | |
| tree | af1ceb188281a0992fd7c560561eb0da70ecab11 | |
| parent | arm64: tegra: Add DFLL clock on Tegra210 (diff) | |
| download | linux-dev-43b9b402f491cb488eb1d1b2608718585cecfd72.tar.xz linux-dev-43b9b402f491cb488eb1d1b2608718585cecfd72.zip | |
arm64: tegra: Add CPU clocks on Tegra210
Add CPU clocks for Tegra210.
Signed-off-by: Joseph Lo <josephl@nvidia.com>
Acked-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
| -rw-r--r-- | arch/arm64/boot/dts/nvidia/tegra210.dtsi | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts/nvidia/tegra210.dtsi index 09f4d48fac9c..b5858b5ea052 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi @@ -1304,6 +1304,12 @@ device_type = "cpu"; compatible = "arm,cortex-a57"; reg = <0>; + clocks = <&tegra_car TEGRA210_CLK_CCLK_G>, + <&tegra_car TEGRA210_CLK_PLL_X>, + <&tegra_car TEGRA210_CLK_PLL_P_OUT4>, + <&dfll>; + clock-names = "cpu_g", "pll_x", "pll_p", "dfll"; + clock-latency = <300000>; }; cpu@1 { |