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| author |   Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> | 2017-04-15 23:18:28 +0300 |
|---|---|---|
| committer |   Simon Horman <horms+renesas@verge.net.au> | 2017-08-15 18:00:17 +0200 |
| commit | 485a40469cf05d7948e1d8c9dbd9058044ded91c (patch) | |
| tree | d0149f91334d66fdb1199807ec9206019babcb09 | |
| parent | ARM: dts: sk-rzg1e: add SCIF2 pins (diff) | |
| download | linux-dev-485a40469cf05d7948e1d8c9dbd9058044ded91c.tar.xz linux-dev-485a40469cf05d7948e1d8c9dbd9058044ded91c.zip | |
ARM: dts: sk-rzg1e: add Ether pins
Add the (previously omitted) Ether/PHY pin data to the SK-RZG1E board's
device tree.
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
| -rw-r--r-- | arch/arm/boot/dts/r8a7745-sk-rzg1e.dts | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/r8a7745-sk-rzg1e.dts b/arch/arm/boot/dts/r8a7745-sk-rzg1e.dts index 0cd908796055..b4d679b04ad6 100644 --- a/arch/arm/boot/dts/r8a7745-sk-rzg1e.dts +++ b/arch/arm/boot/dts/r8a7745-sk-rzg1e.dts @@ -39,6 +39,16 @@ groups = "scif2_data"; function = "scif2"; }; + + ether_pins: ether { + groups = "eth_link", "eth_mdio", "eth_rmii"; + function = "eth"; + }; + + phy1_pins: phy1 { + groups = "intc_irq8"; + function = "intc"; + }; }; &scif2 { @@ -49,6 +59,9 @@ }; ðer { + pinctrl-0 = <ðer_pins &phy1_pins>; + pinctrl-names = "default"; + phy-handle = <&phy1>; renesas,ether-link-active-low; status = "okay"; |