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| author |   Jerome Brunet <jbrunet@baylibre.com> | 2018-01-19 16:55:24 +0100 |
|---|---|---|
| committer | Jerome Brunet <jbrunet@baylibre.com> | 2018-02-12 09:49:23 +0100 |
| commit | 4c5f67b7ea329ed8b3cf708fde4656b2d3b27dbf (patch) | |
| tree | f989beea1abae68e375ccfe0a141290cdb5f55b3 | |
| parent | clk: meson: remove unnecessary rounding in the pll clock (diff) | |
| download | linux-dev-4c5f67b7ea329ed8b3cf708fde4656b2d3b27dbf.tar.xz linux-dev-4c5f67b7ea329ed8b3cf708fde4656b2d3b27dbf.zip | |
clk: meson: use the frac parameter width instead of a constant
Use the fractional part width in the calculation instead of 12, which
happens to be the witdh right now. This is safer in case the field width
ever change in the future
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
| -rw-r--r-- | drivers/clk/meson/clk-pll.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/clk/meson/clk-pll.c b/drivers/clk/meson/clk-pll.c index 087dfc532ba8..50923d004d96 100644 --- a/drivers/clk/meson/clk-pll.c +++ b/drivers/clk/meson/clk-pll.c @@ -81,7 +81,7 @@ static unsigned long meson_clk_pll_recalc_rate(struct clk_hw *hw, reg = readl(pll->base + p->reg_off); frac = PARM_GET(p->width, p->shift, reg); - rate += mul_u64_u32_shr(parent_rate, frac, 12); + rate += mul_u64_u32_shr(parent_rate, frac, p->width); rate *= 2; } |