diff options
| author |   Nandhini Srikandan <nandhini.srikandan@intel.com> | 2022-07-13 12:22:22 +0800 |
|---|---|---|
| committer |   Mark Brown <broonie@kernel.org> | 2022-07-13 13:32:31 +0100 |
| commit | 51e41dc2f2bc7e7c8d5b8202a23eae3ee6056131 (patch) | |
| tree | 7b3f34c59d6e27e314577a31a8c13b2a098d9528 | |
| parent | spi: Add bindings for Intel Thunder Bay SOC (diff) | |
| download | linux-dev-51e41dc2f2bc7e7c8d5b8202a23eae3ee6056131.tar.xz linux-dev-51e41dc2f2bc7e7c8d5b8202a23eae3ee6056131.zip | |
spi: dw: Add support for master mode selection for DWC SSI controller
Add support to select the controller mode as master mode by setting Bit 31
of CTRLR0 register. This feature is supported for controller versions above
v1.02.
Signed-off-by: Nandhini Srikandan <nandhini.srikandan@intel.com>
Acked-by: Serge Semin <fancer.lancer@gmail.com>
Link: https://lore.kernel.org/r/20220713042223.1458-4-nandhini.srikandan@intel.com
Signed-off-by: Mark Brown <broonie@kernel.org>
| -rw-r--r-- | drivers/spi/spi-dw-core.c | 5 | ||||
| -rw-r--r-- | drivers/spi/spi-dw.h | 8 |
2 files changed, 4 insertions, 9 deletions
diff --git a/drivers/spi/spi-dw-core.c b/drivers/spi/spi-dw-core.c index 911ea9bddbee..f87d97ccd2d6 100644 --- a/drivers/spi/spi-dw-core.c +++ b/drivers/spi/spi-dw-core.c @@ -307,8 +307,9 @@ static u32 dw_spi_prepare_cr0(struct dw_spi *dws, struct spi_device *spi) if (spi->mode & SPI_LOOP) cr0 |= DW_HSSI_CTRLR0_SRL; - if (dws->caps & DW_SPI_CAP_KEEMBAY_MST) - cr0 |= DW_HSSI_CTRLR0_KEEMBAY_MST; + /* CTRLR0[31] MST */ + if (dw_spi_ver_is_ge(dws, HSSI, 102A)) + cr0 |= DW_HSSI_CTRLR0_MST; } return cr0; diff --git a/drivers/spi/spi-dw.h b/drivers/spi/spi-dw.h index 79d853f6d192..8b8f924ac410 100644 --- a/drivers/spi/spi-dw.h +++ b/drivers/spi/spi-dw.h @@ -94,13 +94,7 @@ #define DW_HSSI_CTRLR0_SCPOL BIT(9) #define DW_HSSI_CTRLR0_TMOD_MASK GENMASK(11, 10) #define DW_HSSI_CTRLR0_SRL BIT(13) - -/* - * For Keem Bay, CTRLR0[31] is used to select controller mode. - * 0: SSI is slave - * 1: SSI is master - */ -#define DW_HSSI_CTRLR0_KEEMBAY_MST BIT(31) +#define DW_HSSI_CTRLR0_MST BIT(31) /* Bit fields in CTRLR1 */ #define DW_SPI_NDF_MASK GENMASK(15, 0) |