diff options
| author |   William Zhang <william.zhang@broadcom.com> | 2022-08-01 12:46:45 -0700 |
|---|---|---|
| committer |   Florian Fainelli <f.fainelli@gmail.com> | 2022-08-15 09:35:54 -0700 |
| commit | 57d81a9797079065ddfcfcd42b3f94831a9668df (patch) | |
| tree | 139bf93d5bc48b39bc31bb89f523dcad0b004808 | |
| parent | ARM: dts: bcmbca: bcm63178: cosmetic change (diff) | |
| download | linux-dev-57d81a9797079065ddfcfcd42b3f94831a9668df.tar.xz linux-dev-57d81a9797079065ddfcfcd42b3f94831a9668df.zip | |
ARM: dts: bcmbca: bcm6846: fix timer node cpu mask flag
The cpu mask flag value should match the number of cpu cores in the
chip. Correct the value to two cpus for BCM6846 dual core SoC.
Fixes: de1a99ac0b64 ("ARM: dts: Add DTS files for bcmbca SoC BCM6846")
Signed-off-by: William Zhang <william.zhang@broadcom.com>
Link: https://lore.kernel.org/r/20220801194647.29437-1-william.zhang@broadcom.com
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
| -rw-r--r-- | arch/arm/boot/dts/bcm6846.dtsi | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/arch/arm/boot/dts/bcm6846.dtsi b/arch/arm/boot/dts/bcm6846.dtsi index e610c102498f..b74491a3f111 100644 --- a/arch/arm/boot/dts/bcm6846.dtsi +++ b/arch/arm/boot/dts/bcm6846.dtsi @@ -40,10 +40,10 @@ timer { compatible = "arm,armv7-timer"; - interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, - <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, - <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, - <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; arm,cpu-registers-not-fw-configured; }; |