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authorBen Skeggs <bskeggs@redhat.com>2013-05-14 13:09:28 +1000
committerBen Skeggs <bskeggs@redhat.com>2013-07-01 13:50:41 +1000
commit57f0ec159b77df764a6948f8a612b0b825cd8350 (patch)
tree63fadeaf38daafb1559d2471c3f9f2102cdb7e5d
parentdrm/nvc8/gr: update initial register/context values (diff)
downloadlinux-dev-57f0ec159b77df764a6948f8a612b0b825cd8350.tar.xz
linux-dev-57f0ec159b77df764a6948f8a612b0b825cd8350.zip
drm/nvc0/gr: cleanup register lists, and add nvce/nvcf to switches
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Diffstat
-rw-r--r--drivers/gpu/drm/nouveau/core/engine/graph/ctxnvc0.c205
-rw-r--r--drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnvc0.fuc197
-rw-r--r--drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnvc0.fuc.h180
-rw-r--r--drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvc0.fuc111
-rw-r--r--drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvc0.fuc.h111
-rw-r--r--drivers/gpu/drm/nouveau/core/engine/graph/nvc0.c140
6 files changed, 344 insertions, 600 deletions
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/ctxnvc0.c b/drivers/gpu/drm/nouveau/core/engine/graph/ctxnvc0.c
index e0305bd8eedb..3be7b950eece 100644
--- a/drivers/gpu/drm/nouveau/core/engine/graph/ctxnvc0.c
+++ b/drivers/gpu/drm/nouveau/core/engine/graph/ctxnvc0.c
@@ -1323,21 +1323,6 @@ nvc0_grctx_generate_9097(struct nvc0_graph_priv *priv)
nv_mthd(priv, 0x9097, 0x1450, 0x00300008);
nv_mthd(priv, 0x9097, 0x1454, 0x04000080);
nv_mthd(priv, 0x9097, 0x0214, 0x00000000);
-
- switch (nv_device(priv)->chipset) {
- case 0xc0:
- case 0xc3:
- case 0xc4:
- case 0xc1:
- case 0xc8:
- case 0xd9:
- case 0xd7:
- break;
- default:
- /* in trace, right after 0x90c0, not here */
- nv_mthd(priv, 0x9097, 0x3410, 0x80002006);
- break;
- }
}
static void
@@ -1481,7 +1466,11 @@ nvc0_grctx_generate_dispatch(struct nvc0_graph_priv *priv)
case 0xc4:
case 0xc1:
case 0xc8:
+ case 0xce:
+ case 0xcf:
+ break;
default:
+ BUG_ON(1);
break;
}
nv_wr32(priv, 0x404044, 0x00000000);
@@ -1499,19 +1488,7 @@ nvc0_grctx_generate_dispatch(struct nvc0_graph_priv *priv)
nv_wr32(priv, 0x4040c0, 0x00000000);
nv_wr32(priv, 0x4040c4, 0x00000000);
nv_wr32(priv, 0x4040c8, 0xf0000087);
- switch (nv_device(priv)->chipset) {
- case 0xc0:
- case 0xc3:
- case 0xc4:
- case 0xc1:
- case 0xc8:
- case 0xd9:
- case 0xd7:
- nv_wr32(priv, 0x4040d0, 0x00000000);
- break;
- default:
- break;
- }
+ nv_wr32(priv, 0x4040d0, 0x00000000);
nv_wr32(priv, 0x4040d4, 0x00000000);
nv_wr32(priv, 0x4040d8, 0x00000000);
nv_wr32(priv, 0x4040dc, 0x00000000);
@@ -1536,9 +1513,13 @@ nvc0_grctx_generate_dispatch(struct nvc0_graph_priv *priv)
case 0xc4:
case 0xc1:
case 0xc8:
- default:
+ case 0xce:
+ case 0xcf:
nv_wr32(priv, 0x404174, 0x00000000);
break;
+ default:
+ BUG_ON(1);
+ break;
}
nv_wr32(priv, 0x404178, 0x00000000);
nv_wr32(priv, 0x40417c, 0x00000000);
@@ -1681,11 +1662,15 @@ nvc0_grctx_generate_shaders(struct nvc0_graph_priv *priv)
case 0xc3:
case 0xc4:
case 0xc8:
- default:
+ case 0xce:
+ case 0xcf:
nv_wr32(priv, 0x405800, 0x078000bf);
nv_wr32(priv, 0x405830, 0x02180000);
nv_wr32(priv, 0x405834, 0x00000000);
break;
+ default:
+ BUG_ON(1);
+ break;
}
nv_wr32(priv, 0x405838, 0x00000000);
nv_wr32(priv, 0x405854, 0x00000000);
@@ -1720,27 +1705,19 @@ nvc0_grctx_generate_unk64xx(struct nvc0_graph_priv *priv)
case 0xd9:
case 0xd7:
nv_wr32(priv, 0x4064bc, 0x00000000);
- break;
- case 0xc0:
- case 0xc3:
- case 0xc4:
- case 0xc1:
- case 0xc8:
- default:
- break;
- }
- switch (nv_device(priv)->chipset) {
- case 0xc1:
- case 0xd9:
- case 0xd7:
nv_wr32(priv, 0x4064c0, 0x80140078);
nv_wr32(priv, 0x4064c4, 0x0086ffff);
break;
case 0xc0:
case 0xc3:
case 0xc4:
+ case 0xc1:
case 0xc8:
+ case 0xce:
+ case 0xcf:
+ break;
default:
+ BUG_ON(1);
break;
}
}
@@ -1782,6 +1759,8 @@ nvc0_grctx_generate_rop(struct nvc0_graph_priv *priv)
case 0xc3:
case 0xc4:
case 0xc8:
+ case 0xce:
+ case 0xcf:
nv_wr32(priv, 0x408808, 0x0003e00d);
nv_wr32(priv, 0x408900, 0x3080b801);
nv_wr32(priv, 0x408904, 0x02000001);
@@ -1801,11 +1780,7 @@ nvc0_grctx_generate_rop(struct nvc0_graph_priv *priv)
nv_wr32(priv, 0x408908, 0x00c8102f);
break;
default:
- nv_wr32(priv, 0x408808, 0x0003e00d);
- nv_wr32(priv, 0x408900, 0x3080b801);
- nv_wr32(priv, 0x408904, 0x02000001);
- nv_wr32(priv, 0x408908, 0x00c80929);
- nv_wr32(priv, 0x40890c, 0x00000000);
+ BUG_ON(1);
break;
}
nv_wr32(priv, 0x408980, 0x0000011d);
@@ -1829,9 +1804,13 @@ nvc0_grctx_generate_gpc(struct nvc0_graph_priv *priv)
case 0xc4:
case 0xc1:
case 0xc8:
- default:
+ case 0xce:
+ case 0xcf:
nv_wr32(priv, 0x418408, 0x00000000);
break;
+ default:
+ BUG_ON(1);
+ break;
}
nv_wr32(priv, 0x41840c, 0x00001008);
nv_wr32(priv, 0x418410, 0x0fff0fff);
@@ -1845,9 +1824,13 @@ nvc0_grctx_generate_gpc(struct nvc0_graph_priv *priv)
case 0xc4:
case 0xc1:
case 0xc8:
- default:
+ case 0xce:
+ case 0xcf:
nv_wr32(priv, 0x418414, 0x00200fff);
break;
+ default:
+ BUG_ON(1);
+ break;
}
nv_wr32(priv, 0x418450, 0x00000000);
nv_wr32(priv, 0x418454, 0x00000000);
@@ -1873,9 +1856,13 @@ nvc0_grctx_generate_gpc(struct nvc0_graph_priv *priv)
case 0xc4:
case 0xc1:
case 0xc8:
- default:
+ case 0xce:
+ case 0xcf:
nv_wr32(priv, 0x41870c, 0x07c80000);
break;
+ default:
+ BUG_ON(1);
+ break;
}
nv_wr32(priv, 0x418710, 0x00000000);
switch (nv_device(priv)->chipset) {
@@ -1888,9 +1875,13 @@ nvc0_grctx_generate_gpc(struct nvc0_graph_priv *priv)
case 0xc4:
case 0xc1:
case 0xc8:
- default:
+ case 0xce:
+ case 0xcf:
nv_wr32(priv, 0x418800, 0x0006860a);
break;
+ default:
+ BUG_ON(1);
+ break;
}
nv_wr32(priv, 0x418808, 0x00000000);
nv_wr32(priv, 0x41880c, 0x00000000);
@@ -1906,9 +1897,13 @@ nvc0_grctx_generate_gpc(struct nvc0_graph_priv *priv)
case 0xc3:
case 0xc4:
case 0xc8:
- default:
+ case 0xce:
+ case 0xcf:
nv_wr32(priv, 0x418830, 0x00000001);
break;
+ default:
+ BUG_ON(1);
+ break;
}
nv_wr32(priv, 0x4188d8, 0x00000008);
nv_wr32(priv, 0x4188e0, 0x01000000);
@@ -1929,9 +1924,13 @@ nvc0_grctx_generate_gpc(struct nvc0_graph_priv *priv)
case 0xc3:
case 0xc4:
case 0xc8:
- default:
+ case 0xce:
+ case 0xcf:
nv_wr32(priv, 0x4188fc, 0x00100000);
break;
+ default:
+ BUG_ON(1);
+ break;
}
nv_wr32(priv, 0x41891c, 0x00ff00ff);
nv_wr32(priv, 0x418924, 0x00000000);
@@ -1956,9 +1955,13 @@ nvc0_grctx_generate_gpc(struct nvc0_graph_priv *priv)
case 0xc4:
case 0xc1:
case 0xc8:
- default:
+ case 0xce:
+ case 0xcf:
nv_wr32(priv, 0x418b00, 0x00000000);
break;
+ default:
+ BUG_ON(1);
+ break;
}
nv_wr32(priv, 0x418b08, 0x0a418820);
nv_wr32(priv, 0x418b0c, 0x062080e6);
@@ -1986,7 +1989,11 @@ nvc0_grctx_generate_gpc(struct nvc0_graph_priv *priv)
case 0xc3:
case 0xc4:
case 0xc8:
+ case 0xce:
+ case 0xcf:
+ break;
default:
+ BUG_ON(1);
break;
}
nv_wr32(priv, 0x418c80, 0x20200004);
@@ -2014,9 +2021,13 @@ nvc0_grctx_generate_tp(struct nvc0_graph_priv *priv)
case 0xc3:
case 0xc4:
case 0xc8:
- default:
+ case 0xce:
+ case 0xcf:
nv_wr32(priv, 0x419864, 0x0000012a);
break;
+ default:
+ BUG_ON(1);
+ break;
}
nv_wr32(priv, 0x419888, 0x00000000);
nv_wr32(priv, 0x419a00, 0x000001f0);
@@ -2032,10 +2043,16 @@ nvc0_grctx_generate_tp(struct nvc0_graph_priv *priv)
case 0xc4:
case 0xc1:
case 0xc8:
- default:
+ case 0xce:
+ case 0xcf:
+ case 0xd9:
+ case 0xd7:
nv_wr32(priv, 0x419a1c, 0x00000000);
nv_wr32(priv, 0x419a20, 0x00000800);
break;
+ default:
+ BUG_ON(1);
+ break;
}
switch (nv_device(priv)->chipset) {
case 0xc0:
@@ -2048,9 +2065,13 @@ nvc0_grctx_generate_tp(struct nvc0_graph_priv *priv)
case 0xc3:
case 0xc4:
case 0xc1:
- default:
+ case 0xce:
+ case 0xcf:
nv_wr32(priv, 0x00419ac4, 0x0007f440);
break;
+ default:
+ BUG_ON(1);
+ break;
}
nv_wr32(priv, 0x419b00, 0x0a418820);
nv_wr32(priv, 0x419b04, 0x062080e6);
@@ -2069,9 +2090,13 @@ nvc0_grctx_generate_tp(struct nvc0_graph_priv *priv)
case 0xc3:
case 0xc4:
case 0xc8:
- default:
+ case 0xce:
+ case 0xcf:
nv_wr32(priv, 0x419be0, 0x00000001);
break;
+ default:
+ BUG_ON(1);
+ break;
}
nv_wr32(priv, 0x419be4, 0x00000000);
switch (nv_device(priv)->chipset) {
@@ -2084,9 +2109,13 @@ nvc0_grctx_generate_tp(struct nvc0_graph_priv *priv)
case 0xc4:
case 0xc1:
case 0xc8:
- default:
+ case 0xce:
+ case 0xcf:
nv_wr32(priv, 0x419c00, 0x00000002);
break;
+ default:
+ BUG_ON(1);
+ break;
}
nv_wr32(priv, 0x419c04, 0x00000006);
nv_wr32(priv, 0x419c08, 0x00000002);
@@ -2107,9 +2136,11 @@ nvc0_grctx_generate_tp(struct nvc0_graph_priv *priv)
break;
case 0xc0:
case 0xc8:
- default:
nv_wr32(priv, 0x419cb0, 0x00060048);
break;
+ default:
+ BUG_ON(1);
+ break;
}
nv_wr32(priv, 0x419ce8, 0x00000000);
nv_wr32(priv, 0x419cf4, 0x00000183);
@@ -2123,9 +2154,13 @@ nvc0_grctx_generate_tp(struct nvc0_graph_priv *priv)
case 0xc3:
case 0xc4:
case 0xc8:
- default:
+ case 0xce:
+ case 0xcf:
nv_wr32(priv, 0x419d20, 0x02180000);
break;
+ default:
+ BUG_ON(1);
+ break;
}
nv_wr32(priv, 0x419d24, 0x00001fff);
switch (nv_device(priv)->chipset) {
@@ -2138,7 +2173,11 @@ nvc0_grctx_generate_tp(struct nvc0_graph_priv *priv)
case 0xc3:
case 0xc4:
case 0xc8:
+ case 0xce:
+ case 0xcf:
+ break;
default:
+ BUG_ON(1);
break;
}
nv_wr32(priv, 0x419e04, 0x00000000);
@@ -2177,9 +2216,13 @@ nvc0_grctx_generate_tp(struct nvc0_graph_priv *priv)
case 0xc3:
case 0xc4:
case 0xc1:
- default:
+ case 0xce:
+ case 0xcf:
nv_wr32(priv, 0x419ee0, 0x00011110);
break;
+ default:
+ BUG_ON(1);
+ break;
}
switch (nv_device(priv)->chipset) {
case 0xc0:
@@ -2190,6 +2233,8 @@ nvc0_grctx_generate_tp(struct nvc0_graph_priv *priv)
case 0xc3:
case 0xc4:
case 0xc1:
+ case 0xce:
+ case 0xcf:
case 0xd9:
case 0xd7:
nv_wr32(priv, 0x419f30, 0x00000000);
@@ -2204,10 +2249,9 @@ nvc0_grctx_generate_tp(struct nvc0_graph_priv *priv)
nv_wr32(priv, 0x419f54, 0x00000000);
nv_wr32(priv, 0x419f58, 0x00000000);
break;
+ break;
default:
- nv_wr32(priv, 0x419f50, 0x00000000);
- nv_wr32(priv, 0x419f54, 0x00000000);
- nv_wr32(priv, 0x419f58, 0x00000000);
+ BUG_ON(1);
break;
}
}
@@ -2277,7 +2321,13 @@ nvc0_grctx_generate(struct nvc0_graph_priv *priv)
}
}
break;
- default:
+ break;
+ case 0xc0:
+ case 0xc3:
+ case 0xc4:
+ case 0xc8:
+ case 0xce:
+ case 0xcf:
tmp = 0x02180000;
mmio_list(0x405830, tmp, 0, 0);
for (gpc = 0; gpc < priv->gpc_nr; gpc++) {
@@ -2288,6 +2338,9 @@ nvc0_grctx_generate(struct nvc0_graph_priv *priv)
}
}
break;
+ default:
+ BUG_ON(1);
+ break;
}
for (tpc = 0, id = 0; tpc < 4; tpc++) {
@@ -2530,7 +2583,11 @@ nvc0_grctx_generate(struct nvc0_graph_priv *priv)
case 0xc4:
case 0xc1:
case 0xc8:
+ case 0xce:
+ case 0xcf:
+ break;
default:
+ BUG_ON(1);
break;
}
nv_icmd(priv, 0x00000218, 0x0000c080);
@@ -2552,8 +2609,11 @@ nvc0_grctx_generate(struct nvc0_graph_priv *priv)
case 0xc4:
case 0xc1:
case 0xc8:
+ case 0xce:
+ case 0xcf:
break;
default:
+ BUG_ON(1);
break;
}
nv_icmd(priv, 0x000000ad, 0x0000013e);
@@ -3128,7 +3188,11 @@ nvc0_grctx_generate(struct nvc0_graph_priv *priv)
case 0xc0:
case 0xc3:
case 0xc4:
+ case 0xce:
+ case 0xcf:
+ break;
default:
+ BUG_ON(1);
break;
}
nv_icmd(priv, 0x00000586, 0x00000040);
@@ -3241,7 +3305,11 @@ nvc0_grctx_generate(struct nvc0_graph_priv *priv)
case 0xc3:
case 0xc4:
case 0xc1:
+ case 0xce:
+ case 0xcf:
+ break;
default:
+ BUG_ON(1);
break;
}
nv_icmd(priv, 0x00000683, 0x00000006);
@@ -3392,6 +3460,8 @@ nvc0_grctx_generate(struct nvc0_graph_priv *priv)
case 0xc4:
case 0xc1:
case 0xc8:
+ case 0xce:
+ case 0xcf:
nv_mthd(priv, 0x902d, 0x3410, 0x00000000);
break;
case 0xd9:
@@ -3399,6 +3469,7 @@ nvc0_grctx_generate(struct nvc0_graph_priv *priv)
nv_mthd(priv, 0x902d, 0x3410, 0x80002006);
break;
default:
+ BUG_ON(1);
break;
}
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnvc0.fuc b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnvc0.fuc
index 4539e33174b7..61a6b43ece19 100644
--- a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnvc0.fuc
+++ b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnvc0.fuc
@@ -48,30 +48,30 @@ cmd_queue: queue_init
// chipset descriptions
chipsets:
.b8 0xc0 0 0 0
-.b16 #nnvc0_gpc_mmio_head
-.b16 #nnvc0_gpc_mmio_tail
-.b16 #nnvc0_tpc_mmio_head
-.b16 #nnvc0_tpc_mmio_tail
+.b16 #nvc0_gpc_mmio_head
+.b16 #nvc0_gpc_mmio_tail
+.b16 #nvc0_tpc_mmio_head
+.b16 #nvc0_tpc_mmio_tail
.b8 0xc1 0 0 0
-.b16 #nnvc0_gpc_mmio_head
-.b16 #nnvc1_gpc_mmio_tail
-.b16 #nnvc3_tpc_mmio_head
-.b16 #nnvc1_tpc_mmio_tail
+.b16 #nvc0_gpc_mmio_head
+.b16 #nvc1_gpc_mmio_tail
+.b16 #nvc0_tpc_mmio_head
+.b16 #nvc1_tpc_mmio_tail
.b8 0xc3 0 0 0
-.b16 #nnvc0_gpc_mmio_head
-.b16 #nnvc0_gpc_mmio_tail
-.b16 #nnvc3_tpc_mmio_head
-.b16 #nnvc3_tpc_mmio_tail
+.b16 #nvc0_gpc_mmio_head
+.b16 #nvc0_gpc_mmio_tail
+.b16 #nvc0_tpc_mmio_head
+.b16 #nvc3_tpc_mmio_tail
.b8 0xc4 0 0 0
-.b16 #nnvc0_gpc_mmio_head
-.b16 #nnvc0_gpc_mmio_tail
-.b16 #nnvc3_tpc_mmio_head
-.b16 #nnvc3_tpc_mmio_tail
+.b16 #nvc0_gpc_mmio_head
+.b16 #nvc0_gpc_mmio_tail
+.b16 #nvc0_tpc_mmio_head
+.b16 #nvc3_tpc_mmio_tail
.b8 0xc8 0 0 0
-.b16 #nnvc0_gpc_mmio_head
-.b16 #nnvc0_gpc_mmio_tail
-.b16 #nnvc0_tpc_mmio_head
-.b16 #nnvc0_tpc_mmio_tail
+.b16 #nvc0_gpc_mmio_head
+.b16 #nvc0_gpc_mmio_tail
+.b16 #nvc0_tpc_mmio_head
+.b16 #nvc0_tpc_mmio_tail
.b8 0xce 0 0 0
.b16 #nvc0_gpc_mmio_head
.b16 #nvc0_gpc_mmio_tail
@@ -81,23 +81,26 @@ chipsets:
.b16 #nvc0_gpc_mmio_head
.b16 #nvc0_gpc_mmio_tail
.b16 #nvc0_tpc_mmio_head
-.b16 #nvcf_tpc_mmio_tail
+.b16 #nvc3_tpc_mmio_tail
.b8 0xd9 0 0 0
.b16 #nvd9_gpc_mmio_head
-.b16 #nvd9_gpc_mmio_tail
-.b16 #nvd9_tpc_mmio_head
+.b16 #nvc1_gpc_mmio_tail
+.b16 #nvc0_tpc_mmio_head
.b16 #nvd9_tpc_mmio_tail
.b8 0xd7 0 0 0
.b16 #nvd9_gpc_mmio_head
-.b16 #nvd9_gpc_mmio_tail
-.b16 #nvd9_tpc_mmio_head
+.b16 #nvc1_gpc_mmio_tail
+.b16 #nvc0_tpc_mmio_head
.b16 #nvd9_tpc_mmio_tail
.b8 0 0 0 0
// GPC mmio lists
nvc0_gpc_mmio_head:
+mmctx_data(0x000408, 1)
+nvd9_gpc_mmio_head:
mmctx_data(0x000380, 1)
-mmctx_data(0x000400, 6)
+mmctx_data(0x000400, 2);
+mmctx_data(0x00040c, 3);
mmctx_data(0x000450, 9)
mmctx_data(0x000600, 1)
mmctx_data(0x000684, 1)
@@ -121,64 +124,8 @@ mmctx_data(0x000c8c, 1)
mmctx_data(0x001000, 3)
mmctx_data(0x001014, 1)
nvc0_gpc_mmio_tail:
-
-nnvc0_gpc_mmio_head:
-mmctx_data(0x000380, 1)
-mmctx_data(0x000400, 6)
-mmctx_data(0x000450, 9)
-mmctx_data(0x000600, 1)
-mmctx_data(0x000684, 1)
-mmctx_data(0x000700, 5)
-mmctx_data(0x000800, 1)
-mmctx_data(0x000808, 3)
-mmctx_data(0x000828, 1)
-mmctx_data(0x000830, 1)
-mmctx_data(0x0008d8, 1)
-mmctx_data(0x0008e0, 1)
-mmctx_data(0x0008e8, 6)
-mmctx_data(0x00091c, 1)
-mmctx_data(0x000924, 3)
-mmctx_data(0x000b00, 1)
-mmctx_data(0x000b08, 6)
-mmctx_data(0x000bb8, 1)
-mmctx_data(0x000c08, 1)
-mmctx_data(0x000c10, 8)
-mmctx_data(0x000c80, 1)
-mmctx_data(0x000c8c, 1)
-mmctx_data(0x001000, 3)
-mmctx_data(0x001014, 1)
-nnvc0_gpc_mmio_tail:
mmctx_data(0x000c6c, 1);
-nnvc1_gpc_mmio_tail:
-
-nvd9_gpc_mmio_head:
-mmctx_data(0x000380, 1)
-mmctx_data(0x000400, 2)
-mmctx_data(0x00040c, 3)
-mmctx_data(0x000450, 9)
-mmctx_data(0x000600, 1)
-mmctx_data(0x000684, 1)
-mmctx_data(0x000700, 5)
-mmctx_data(0x000800, 1)
-mmctx_data(0x000808, 3)
-mmctx_data(0x000828, 1)
-mmctx_data(0x000830, 1)
-mmctx_data(0x0008d8, 1)
-mmctx_data(0x0008e0, 1)
-mmctx_data(0x0008e8, 6)
-mmctx_data(0x00091c, 1)
-mmctx_data(0x000924, 3)
-mmctx_data(0x000b00, 1)
-mmctx_data(0x000b08, 6)
-mmctx_data(0x000bb8, 1)
-mmctx_data(0x000c08, 1)
-mmctx_data(0x000c10, 8)
-mmctx_data(0x000c6c, 1)
-mmctx_data(0x000c80, 1)
-mmctx_data(0x000c8c, 1)
-mmctx_data(0x001000, 3)
-mmctx_data(0x001014, 1)
-nvd9_gpc_mmio_tail:
+nvc1_gpc_mmio_tail:
// TPC mmio lists
nvc0_tpc_mmio_head:
@@ -188,7 +135,6 @@ mmctx_data(0x000048, 1)
mmctx_data(0x000064, 1)
mmctx_data(0x000088, 1)
mmctx_data(0x000200, 6)
-mmctx_data(0x00021c, 2)
mmctx_data(0x000300, 6)
mmctx_data(0x0003d0, 1)
mmctx_data(0x0003e0, 2)
@@ -203,86 +149,15 @@ mmctx_data(0x000644, 20)
mmctx_data(0x000698, 1)
mmctx_data(0x000750, 2)
nvc0_tpc_mmio_tail:
-mmctx_data(0x000758, 1)
-mmctx_data(0x0002c4, 1)
-mmctx_data(0x0006e0, 1)
-nvcf_tpc_mmio_tail:
-mmctx_data(0x0004bc, 1)
-nvc3_tpc_mmio_tail:
-
-nnvc0_tpc_mmio_head:
-mmctx_data(0x000018, 1)
-mmctx_data(0x00003c, 1)
-mmctx_data(0x000048, 1)
-mmctx_data(0x000064, 1)
-mmctx_data(0x000088, 1)
-mmctx_data(0x000200, 6)
-mmctx_data(0x000300, 6)
-mmctx_data(0x0003d0, 1)
-mmctx_data(0x0003e0, 2)
-mmctx_data(0x000400, 3)
-mmctx_data(0x000420, 1)
-mmctx_data(0x0004b0, 1)
-mmctx_data(0x0004e8, 1)
-mmctx_data(0x0004f4, 1)
-mmctx_data(0x000520, 2)
-mmctx_data(0x000604, 4)
-mmctx_data(0x000644, 20)
-mmctx_data(0x000698, 1)
-mmctx_data(0x000750, 2)
-nnvc0_tpc_mmio_tail:
-
-nnvc3_tpc_mmio_head:
-mmctx_data(0x000018, 1)
-mmctx_data(0x00003c, 1)
-mmctx_data(0x000048, 1)
-mmctx_data(0x000064, 1)
-mmctx_data(0x000088, 1)
-mmctx_data(0x000200, 6)
mmctx_data(0x00021c, 2)
mmctx_data(0x0002c4, 1)
-mmctx_data(0x000300, 6)
-mmctx_data(0x0003d0, 1)
-mmctx_data(0x0003e0, 2)
-mmctx_data(0x000400, 3)
-mmctx_data(0x000420, 1)
-mmctx_data(0x0004b0, 1)
-mmctx_data(0x0004e8, 1)
-mmctx_data(0x0004f4, 1)
-mmctx_data(0x000520, 2)
-mmctx_data(0x000604, 4)
-mmctx_data(0x000644, 20)
-mmctx_data(0x000698, 1)
-mmctx_data(0x0006e0, 1)
-mmctx_data(0x000730, 11)
-nnvc3_tpc_mmio_tail:
-mmctx_data(0x000544, 1)
-nnvc1_tpc_mmio_tail:
-
-nvd9_tpc_mmio_head:
-mmctx_data(0x000018, 1)
-mmctx_data(0x00003c, 1)
-mmctx_data(0x000048, 1)
-mmctx_data(0x000064, 1)
-mmctx_data(0x000088, 1)
-mmctx_data(0x000200, 6)
-mmctx_data(0x00021c, 2)
-mmctx_data(0x0002c4, 1)
-mmctx_data(0x000300, 6)
-mmctx_data(0x0003d0, 1)
-mmctx_data(0x0003e0, 2)
-mmctx_data(0x000400, 3)
-mmctx_data(0x000420, 3)
-mmctx_data(0x0004b0, 1)
-mmctx_data(0x0004e8, 1)
-mmctx_data(0x0004f4, 1)
-mmctx_data(0x000520, 2)
+mmctx_data(0x000730, 8)
+mmctx_data(0x000758, 1)
+nvc3_tpc_mmio_tail:
mmctx_data(0x000544, 1)
-mmctx_data(0x000604, 4)
-mmctx_data(0x000644, 20)
-mmctx_data(0x000698, 1)
-mmctx_data(0x0006e0, 1)
-mmctx_data(0x000730, 11)
+nvc1_tpc_mmio_tail:
+mmctx_data(0x000424, 2);
+mmctx_data(0x0006e0, 1);
nvd9_tpc_mmio_tail:
.section #nvc0_grgpc_code
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnvc0.fuc.h b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnvc0.fuc.h
index bad9a16a9463..cafcc638042a 100644
--- a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnvc0.fuc.h
+++ b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/gpcnvc0.fuc.h
@@ -34,88 +34,36 @@ uint32_t nvc0_grgpc_data[] = {
0x00000000,
/* 0x0064: chipsets */
0x000000c0,
- 0x01940134,
- 0x02ac0260,
+ 0x013c00d4,
+ 0x018c0140,
0x000000c1,
- 0x01980134,
- 0x030802ac,
+ 0x014000d4,
+ 0x01a00140,
0x000000c3,
- 0x01940134,
- 0x030402ac,
+ 0x013c00d4,
+ 0x019c0140,
0x000000c4,
- 0x01940134,
- 0x030402ac,
+ 0x013c00d4,
+ 0x019c0140,
0x000000c8,
- 0x01940134,
- 0x02ac0260,
+ 0x013c00d4,
+ 0x018c0140,
0x000000ce,
- 0x013400d4,
- 0x02600200,
+ 0x013c00d4,
+ 0x019c0140,
0x000000cf,
- 0x013400d4,
- 0x025c0200,
+ 0x013c00d4,
+ 0x019c0140,
0x000000d9,
- 0x02000198,
- 0x03640308,
+ 0x014000d8,
+ 0x01a80140,
0x000000d7,
- 0x02000198,
- 0x03640308,
+ 0x014000d8,
+ 0x01a80140,
0x00000000,
/* 0x00d4: nvc0_gpc_mmio_head */
- 0x00000380,
- 0x14000400,
- 0x20000450,
- 0x00000600,
- 0x00000684,
- 0x10000700,
- 0x00000800,
- 0x08000808,
- 0x00000828,
- 0x00000830,
- 0x000008d8,
- 0x000008e0,
- 0x140008e8,
- 0x0000091c,
- 0x08000924,
- 0x00000b00,
- 0x14000b08,
- 0x00000bb8,
- 0x00000c08,
- 0x1c000c10,
- 0x00000c80,
- 0x00000c8c,
- 0x08001000,
- 0x00001014,
-/* 0x0134: nvc0_gpc_mmio_tail */
-/* 0x0134: nnvc0_gpc_mmio_head */
- 0x00000380,
- 0x14000400,
- 0x20000450,
- 0x00000600,
- 0x00000684,
- 0x10000700,
- 0x00000800,
- 0x08000808,
- 0x00000828,
- 0x00000830,
- 0x000008d8,
- 0x000008e0,
- 0x140008e8,
- 0x0000091c,
- 0x08000924,
- 0x00000b00,
- 0x14000b08,
- 0x00000bb8,
- 0x00000c08,
- 0x1c000c10,
- 0x00000c80,
- 0x00000c8c,
- 0x08001000,
- 0x00001014,
-/* 0x0194: nnvc0_gpc_mmio_tail */
- 0x00000c6c,
-/* 0x0198: nnvc1_gpc_mmio_tail */
-/* 0x0198: nvd9_gpc_mmio_head */
+ 0x00000408,
+/* 0x00d8: nvd9_gpc_mmio_head */
0x00000380,
0x04000400,
0x0800040c,
@@ -137,41 +85,14 @@ uint32_t nvc0_grgpc_data[] = {
0x00000bb8,
0x00000c08,
0x1c000c10,
- 0x00000c6c,
0x00000c80,
0x00000c8c,
0x08001000,
0x00001014,
-/* 0x0200: nvd9_gpc_mmio_tail */
-/* 0x0200: nvc0_tpc_mmio_head */
- 0x00000018,
- 0x0000003c,
- 0x00000048,
- 0x00000064,
- 0x00000088,
- 0x14000200,
- 0x0400021c,
- 0x14000300,
- 0x000003d0,
- 0x040003e0,
- 0x08000400,
- 0x00000420,
- 0x000004b0,
- 0x000004e8,
- 0x000004f4,
- 0x04000520,
- 0x0c000604,
- 0x4c000644,
- 0x00000698,
- 0x04000750,
-/* 0x0250: nvc0_tpc_mmio_tail */
- 0x00000758,
- 0x000002c4,
- 0x000006e0,
-/* 0x025c: nvcf_tpc_mmio_tail */
- 0x000004bc,
-/* 0x0260: nvc3_tpc_mmio_tail */
-/* 0x0260: nnvc0_tpc_mmio_head */
+/* 0x013c: nvc0_gpc_mmio_tail */
+ 0x00000c6c,
+/* 0x0140: nvc1_gpc_mmio_tail */
+/* 0x0140: nvc0_tpc_mmio_head */
0x00000018,
0x0000003c,
0x00000048,
@@ -191,57 +112,16 @@ uint32_t nvc0_grgpc_data[] = {
0x4c000644,
0x00000698,
0x04000750,
-/* 0x02ac: nnvc0_tpc_mmio_tail */
-/* 0x02ac: nnvc3_tpc_mmio_head */
- 0x00000018,
- 0x0000003c,
- 0x00000048,
- 0x00000064,
- 0x00000088,
- 0x14000200,
- 0x0400021c,
- 0x000002c4,
- 0x14000300,
- 0x000003d0,
- 0x040003e0,
- 0x08000400,
- 0x00000420,
- 0x000004b0,
- 0x000004e8,
- 0x000004f4,
- 0x04000520,
- 0x0c000604,
- 0x4c000644,
- 0x00000698,
- 0x000006e0,
- 0x28000730,
-/* 0x0304: nnvc3_tpc_mmio_tail */
- 0x00000544,
-/* 0x0308: nnvc1_tpc_mmio_tail */
-/* 0x0308: nvd9_tpc_mmio_head */
- 0x00000018,
- 0x0000003c,
- 0x00000048,
- 0x00000064,
- 0x00000088,
- 0x14000200,
+/* 0x018c: nvc0_tpc_mmio_tail */
0x0400021c,
0x000002c4,
- 0x14000300,
- 0x000003d0,
- 0x040003e0,
- 0x08000400,
- 0x08000420,
- 0x000004b0,
- 0x000004e8,
- 0x000004f4,
- 0x04000520,
+ 0x1c000730,
+ 0x00000758,
+/* 0x019c: nvc3_tpc_mmio_tail */
0x00000544,
- 0x0c000604,
- 0x4c000644,
- 0x00000698,
+/* 0x01a0: nvc1_tpc_mmio_tail */
+ 0x04000424,
0x000006e0,
- 0x28000730,
};
uint32_t nvc0_grgpc_code[] = {
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvc0.fuc b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvc0.fuc
index 6eb5168a3811..9f174be6bc82 100644
--- a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvc0.fuc
+++ b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvc0.fuc
@@ -48,20 +48,20 @@ xfer_data: .b32 0
.align 256
chipsets:
.b8 0xc0 0 0 0
-.b16 #nnvc0_hub_mmio_head
-.b16 #nnvc0_hub_mmio_tail
+.b16 #nvc0_hub_mmio_head
+.b16 #nvc0_hub_mmio_tail
.b8 0xc1 0 0 0
-.b16 #nnvc0_hub_mmio_head
+.b16 #nvc0_hub_mmio_head
.b16 #nvc1_hub_mmio_tail
.b8 0xc3 0 0 0
-.b16 #nnvc0_hub_mmio_head
-.b16 #nnvc0_hub_mmio_tail
+.b16 #nvc0_hub_mmio_head
+.b16 #nvc0_hub_mmio_tail
.b8 0xc4 0 0 0
-.b16 #nnvc0_hub_mmio_head
-.b16 #nnvc0_hub_mmio_tail
+.b16 #nvc0_hub_mmio_head
+.b16 #nvc0_hub_mmio_tail
.b8 0xc8 0 0 0
-.b16 #nnvc0_hub_mmio_head
-.b16 #nnvc0_hub_mmio_tail
+.b16 #nvc0_hub_mmio_head
+.b16 #nvc0_hub_mmio_tail
.b8 0xce 0 0 0
.b16 #nvc0_hub_mmio_head
.b16 #nvc0_hub_mmio_tail
@@ -77,91 +77,8 @@ chipsets:
.b8 0 0 0 0
nvc0_hub_mmio_head:
-mmctx_data(0x17e91c, 2)
-mmctx_data(0x400204, 2)
-mmctx_data(0x404004, 11)
-mmctx_data(0x404044, 1)
-mmctx_data(0x404094, 14)
-mmctx_data(0x4040d0, 7)
-mmctx_data(0x4040f8, 1)
-mmctx_data(0x404130, 3)
-mmctx_data(0x404150, 3)
-mmctx_data(0x404164, 2)
-mmctx_data(0x404174, 3)
-mmctx_data(0x404200, 8)
-mmctx_data(0x404404, 14)
-mmctx_data(0x404460, 4)
-mmctx_data(0x404480, 1)
-mmctx_data(0x404498, 1)
-mmctx_data(0x404604, 4)
-mmctx_data(0x404618, 32)
-mmctx_data(0x404698, 21)
-mmctx_data(0x4046f0, 2)
-mmctx_data(0x404700, 22)
-mmctx_data(0x405800, 1)
-mmctx_data(0x405830, 3)
-mmctx_data(0x405854, 1)
-mmctx_data(0x405870, 4)
-mmctx_data(0x405a00, 2)
-mmctx_data(0x405a18, 1)
-mmctx_data(0x406020, 1)
-mmctx_data(0x406028, 4)
-mmctx_data(0x4064a8, 2)
-mmctx_data(0x4064b4, 2)
-mmctx_data(0x407804, 1)
-mmctx_data(0x40780c, 6)
-mmctx_data(0x4078bc, 1)
-mmctx_data(0x408000, 7)
-mmctx_data(0x408064, 1)
-mmctx_data(0x408800, 3)
-mmctx_data(0x408900, 4)
-mmctx_data(0x408980, 1)
-nvc0_hub_mmio_tail:
-
-nnvc0_hub_mmio_head:
-mmctx_data(0x17e91c, 2)
-mmctx_data(0x400204, 2)
-mmctx_data(0x404004, 11)
-mmctx_data(0x404044, 1)
-mmctx_data(0x404094, 14)
-mmctx_data(0x4040d0, 7)
-mmctx_data(0x4040f8, 1)
-mmctx_data(0x404130, 3)
-mmctx_data(0x404150, 3)
-mmctx_data(0x404164, 2)
-mmctx_data(0x404174, 3)
-mmctx_data(0x404200, 8)
-mmctx_data(0x404404, 14)
-mmctx_data(0x404460, 4)
-mmctx_data(0x404480, 1)
-mmctx_data(0x404498, 1)
-mmctx_data(0x404604, 4)
-mmctx_data(0x404618, 32)
-mmctx_data(0x404698, 21)
-mmctx_data(0x4046f0, 2)
-mmctx_data(0x404700, 22)
-mmctx_data(0x405800, 1)
-mmctx_data(0x405830, 3)
-mmctx_data(0x405854, 1)
-mmctx_data(0x405870, 4)
-mmctx_data(0x405a00, 2)
-mmctx_data(0x405a18, 1)
-mmctx_data(0x406020, 1)
-mmctx_data(0x406028, 4)
-mmctx_data(0x4064a8, 2)
-mmctx_data(0x4064b4, 2)
-mmctx_data(0x407804, 1)
-mmctx_data(0x40780c, 6)
-mmctx_data(0x4078bc, 1)
-mmctx_data(0x408000, 7)
-mmctx_data(0x408064, 1)
-mmctx_data(0x408800, 3)
-mmctx_data(0x408900, 3)
-mmctx_data(0x408980, 1)
-nnvc0_hub_mmio_tail:
-mmctx_data(0x4064c0, 2)
-nvc1_hub_mmio_tail:
-
+mmctx_data(0x40402c, 1)
+mmctx_data(0x404174, 1)
nvd9_hub_mmio_head:
mmctx_data(0x17e91c, 2)
mmctx_data(0x400204, 2)
@@ -193,7 +110,7 @@ mmctx_data(0x405a18, 1)
mmctx_data(0x406020, 1)
mmctx_data(0x406028, 4)
mmctx_data(0x4064a8, 2)
-mmctx_data(0x4064b4, 5)
+mmctx_data(0x4064b4, 2)
mmctx_data(0x407804, 1)
mmctx_data(0x40780c, 6)
mmctx_data(0x4078bc, 1)
@@ -202,6 +119,10 @@ mmctx_data(0x408064, 1)
mmctx_data(0x408800, 3)
mmctx_data(0x408900, 3)
mmctx_data(0x408980, 1)
+nvc0_hub_mmio_tail:
+mmctx_data(0x4064c0, 2)
+nvc1_hub_mmio_tail:
+mmctx_data(0x4064bc, 3)
nvd9_hub_mmio_tail:
.section #nvc0_grhub_code
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvc0.fuc.h b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvc0.fuc.h
index 9d5517407dfb..0953c2db2d13 100644
--- a/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvc0.fuc.h
+++ b/drivers/gpu/drm/nouveau/core/engine/graph/fuc/hubnvc0.fuc.h
@@ -203,109 +203,28 @@ uint32_t nvc0_grhub_data[] = {
0x00000000,
/* 0x0300: chipsets */
0x000000c0,
- 0x048403e8,
+ 0x03f0034c,
0x000000c1,
- 0x048803e8,
+ 0x03f4034c,
0x000000c3,
- 0x048403e8,
+ 0x03f0034c,
0x000000c4,
- 0x048403e8,
+ 0x03f0034c,
0x000000c8,
- 0x048403e8,
+ 0x03f0034c,
0x000000ce,
- 0x03e8034c,
+ 0x03f0034c,
0x000000cf,
- 0x03e8034c,
+ 0x03f0034c,
0x000000d9,
- 0x05240488,
+ 0x03f80354,
0x000000d7,
- 0x05240488,
+ 0x03f80354,
0x00000000,
/* 0x034c: nvc0_hub_mmio_head */
- 0x0417e91c,
- 0x04400204,
- 0x28404004,
- 0x00404044,
- 0x34404094,
- 0x184040d0,
- 0x004040f8,
- 0x08404130,
- 0x08404150,
- 0x04404164,
- 0x08404174,
- 0x1c404200,
- 0x34404404,
- 0x0c404460,
- 0x00404480,
- 0x00404498,
- 0x0c404604,
- 0x7c404618,
- 0x50404698,
- 0x044046f0,
- 0x54404700,
- 0x00405800,
- 0x08405830,
- 0x00405854,
- 0x0c405870,
- 0x04405a00,
- 0x00405a18,
- 0x00406020,
- 0x0c406028,
- 0x044064a8,
- 0x044064b4,
- 0x00407804,
- 0x1440780c,
- 0x004078bc,
- 0x18408000,
- 0x00408064,
- 0x08408800,
- 0x0c408900,
- 0x00408980,
-/* 0x03e8: nvc0_hub_mmio_tail */
-/* 0x03e8: nnvc0_hub_mmio_head */
- 0x0417e91c,
- 0x04400204,
- 0x28404004,
- 0x00404044,
- 0x34404094,
- 0x184040d0,
- 0x004040f8,
- 0x08404130,
- 0x08404150,
- 0x04404164,
- 0x08404174,
- 0x1c404200,
- 0x34404404,
- 0x0c404460,
- 0x00404480,
- 0x00404498,
- 0x0c404604,
- 0x7c404618,
- 0x50404698,
- 0x044046f0,
- 0x54404700,
- 0x00405800,
- 0x08405830,
- 0x00405854,
- 0x0c405870,
- 0x04405a00,
- 0x00405a18,
- 0x00406020,
- 0x0c406028,
- 0x044064a8,
- 0x044064b4,
- 0x00407804,
- 0x1440780c,
- 0x004078bc,
- 0x18408000,
- 0x00408064,
- 0x08408800,
- 0x08408900,
- 0x00408980,
-/* 0x0484: nnvc0_hub_mmio_tail */
- 0x044064c0,
-/* 0x0488: nvc1_hub_mmio_tail */
-/* 0x0488: nvd9_hub_mmio_head */
+ 0x0040402c,
+ 0x00404174,
+/* 0x0354: nvd9_hub_mmio_head */
0x0417e91c,
0x04400204,
0x24404004,
@@ -336,7 +255,7 @@ uint32_t nvc0_grhub_data[] = {
0x00406020,
0x0c406028,
0x044064a8,
- 0x104064b4,
+ 0x044064b4,
0x00407804,
0x1440780c,
0x004078bc,
@@ -345,6 +264,10 @@ uint32_t nvc0_grhub_data[] = {
0x08408800,
0x08408900,
0x00408980,
+/* 0x03f0: nvc0_hub_mmio_tail */
+ 0x044064c0,
+/* 0x03f4: nvc1_hub_mmio_tail */
+ 0x084064bc,
};
uint32_t nvc0_grhub_code[] = {
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/nvc0.c b/drivers/gpu/drm/nouveau/core/engine/graph/nvc0.c
index f146ebc9c08d..d61c833be09f 100644
--- a/drivers/gpu/drm/nouveau/core/engine/graph/nvc0.c
+++ b/drivers/gpu/drm/nouveau/core/engine/graph/nvc0.c
@@ -757,7 +757,11 @@ nvc0_graph_init_unk64xx(struct nvc0_graph_priv *priv)
case 0xc4:
case 0xc1:
case 0xc8:
+ case 0xce:
+ case 0xcf:
+ break;
default:
+ BUG_ON(1);
break;
}
}
@@ -771,13 +775,17 @@ nvc0_graph_init_unk58xx(struct nvc0_graph_priv *priv)
case 0xc3:
case 0xc4:
case 0xc1:
+ case 0xce:
+ case 0xcf:
case 0xd9:
case 0xd7:
nv_wr32(priv, 0x405900, 0x00002834);
break;
case 0xc0:
case 0xc8:
+ break;
default:
+ BUG_ON(1);
break;
}
nv_wr32(priv, 0x405908, 0x00000000);
@@ -792,7 +800,11 @@ nvc0_graph_init_unk58xx(struct nvc0_graph_priv *priv)
case 0xc4:
case 0xc1:
case 0xc8:
+ case 0xce:
+ case 0xcf:
+ break;
default:
+ BUG_ON(1);
break;
}
}
@@ -816,7 +828,11 @@ nvc0_graph_init_gpc(struct nvc0_graph_priv *priv)
case 0xc4:
case 0xc1:
case 0xc8:
+ case 0xce:
+ case 0xcf:
+ break;
default:
+ BUG_ON(1);
break;
}
nv_wr32(priv, 0x4184a0, 0x00000000);
@@ -831,7 +847,11 @@ nvc0_graph_init_gpc(struct nvc0_graph_priv *priv)
case 0xc4:
case 0xc1:
case 0xc8:
+ case 0xce:
+ case 0xcf:
+ break;
default:
+ BUG_ON(1);
break;
}
nv_wr32(priv, 0x418604, 0x00000000);
@@ -846,9 +866,13 @@ nvc0_graph_init_gpc(struct nvc0_graph_priv *priv)
case 0xc3:
case 0xc4:
case 0xc8:
- default:
+ case 0xce:
+ case 0xcf:
nv_wr32(priv, 0x418714, 0x80000000);
break;
+ default:
+ BUG_ON(1);
+ break;
}
nv_wr32(priv, 0x418384, 0x00000000);
nv_wr32(priv, 0x418814, 0x00000000);
@@ -865,9 +889,13 @@ nvc0_graph_init_gpc(struct nvc0_graph_priv *priv)
case 0xc0:
case 0xc3:
case 0xc4:
- default:
+ case 0xce:
+ case 0xcf:
nv_wr32(priv, 0x4188c8, 0x80000000);
break;
+ default:
+ BUG_ON(1);
+ break;
}
nv_wr32(priv, 0x4188cc, 0x00000000);
nv_wr32(priv, 0x4188d0, 0x00010000);
@@ -891,7 +919,11 @@ nvc0_graph_init_gpc(struct nvc0_graph_priv *priv)
case 0xc4:
case 0xc1:
case 0xc8:
+ case 0xce:
+ case 0xcf:
+ break;
default:
+ BUG_ON(1);
break;
}
nv_wr32(priv, 0x418c88, 0x00000000);
@@ -906,7 +938,11 @@ nvc0_graph_init_gpc(struct nvc0_graph_priv *priv)
case 0xc4:
case 0xc1:
case 0xc8:
+ case 0xce:
+ case 0xcf:
+ break;
default:
+ BUG_ON(1);
break;
}
nv_wr32(priv, 0x418d00, 0x00000000);
@@ -922,7 +958,11 @@ nvc0_graph_init_gpc(struct nvc0_graph_priv *priv)
case 0xc4:
case 0xc1:
case 0xc8:
+ case 0xce:
+ case 0xcf:
+ break;
default:
+ BUG_ON(1);
break;
}
nv_wr32(priv, 0x418f08, 0x00000000);
@@ -939,9 +979,13 @@ nvc0_graph_init_gpc(struct nvc0_graph_priv *priv)
case 0xc3:
case 0xc4:
case 0xc8:
- default:
+ case 0xce:
+ case 0xcf:
nv_wr32(priv, 0x418e00, 0x00000050);
break;
+ default:
+ BUG_ON(1);
+ break;
}
nv_wr32(priv, 0x418e08, 0x00000000);
switch (nv_device(priv)->chipset) {
@@ -955,7 +999,11 @@ nvc0_graph_init_gpc(struct nvc0_graph_priv *priv)
case 0xc4:
case 0xc1:
case 0xc8:
+ case 0xce:
+ case 0xcf:
+ break;
default:
+ BUG_ON(1);
break;
}
nv_wr32(priv, 0x41900c, 0x00000000);
@@ -973,13 +1021,17 @@ nvc0_graph_init_tpc(struct nvc0_graph_priv *priv)
case 0xc3:
case 0xc4:
case 0xc1:
+ case 0xce:
+ case 0xcf:
case 0xd9:
case 0xd7:
nv_wr32(priv, 0x419ac8, 0x00000000);
break;
case 0xc0:
case 0xc8:
+ break;
default:
+ BUG_ON(1);
break;
}
nv_wr32(priv, 0x419ab8, 0x000000e7);
@@ -996,9 +1048,13 @@ nvc0_graph_init_tpc(struct nvc0_graph_priv *priv)
case 0xc4:
case 0xc1:
case 0xc8:
- default:
+ case 0xce:
+ case 0xcf:
nv_wr32(priv, 0x41980c, 0x00000000);
break;
+ default:
+ BUG_ON(1);
+ break;
}
nv_wr32(priv, 0x419810, 0x00000000);
switch (nv_device(priv)->chipset) {
@@ -1011,9 +1067,13 @@ nvc0_graph_init_tpc(struct nvc0_graph_priv *priv)
case 0xc3:
case 0xc4:
case 0xc8:
- default:
+ case 0xce:
+ case 0xcf:
nv_wr32(priv, 0x419814, 0x00000000);
break;
+ default:
+ BUG_ON(1);
+ break;
}
nv_wr32(priv, 0x419844, 0x00000000);
switch (nv_device(priv)->chipset) {
@@ -1026,9 +1086,13 @@ nvc0_graph_init_tpc(struct nvc0_graph_priv *priv)
case 0xc4:
case 0xc1:
case 0xc8:
- default:
+ case 0xce:
+ case 0xcf:
nv_wr32(priv, 0x41984c, 0x00005bc5);
break;
+ default:
+ BUG_ON(1);
+ break;
}
nv_wr32(priv, 0x419850, 0x00000000);
nv_wr32(priv, 0x419854, 0x00000000);
@@ -1038,13 +1102,17 @@ nvc0_graph_init_tpc(struct nvc0_graph_priv *priv)
case 0xc3:
case 0xc4:
case 0xc1:
+ case 0xce:
+ case 0xcf:
case 0xd9:
case 0xd7:
nv_wr32(priv, 0x419880, 0x00000002);
break;
case 0xc0:
case 0xc8:
+ break;
default:
+ BUG_ON(1);
break;
}
nv_wr32(priv, 0x419c98, 0x00000000);
@@ -1067,7 +1135,11 @@ nvc0_graph_init_tpc(struct nvc0_graph_priv *priv)
case 0xc4:
case 0xc1:
case 0xc8:
+ case 0xce:
+ case 0xcf:
+ break;
default:
+ BUG_ON(1);
break;
}
nv_wr32(priv, 0x419d2c, 0x00000000);
@@ -1082,7 +1154,11 @@ nvc0_graph_init_tpc(struct nvc0_graph_priv *priv)
case 0xc4:
case 0xc1:
case 0xc8:
+ case 0xce:
+ case 0xcf:
+ break;
default:
+ BUG_ON(1);
break;
}
nv_wr32(priv, 0x419c0c, 0x00000000);
@@ -1099,9 +1175,13 @@ nvc0_graph_init_tpc(struct nvc0_graph_priv *priv)
case 0xc4:
case 0xc1:
case 0xc8:
- default:
+ case 0xce:
+ case 0xcf:
nv_wr32(priv, 0x419ea8, 0x00001100);
break;
+ default:
+ BUG_ON(1);
+ break;
}
switch (nv_device(priv)->chipset) {
@@ -1112,11 +1192,15 @@ nvc0_graph_init_tpc(struct nvc0_graph_priv *priv)
case 0xc3:
case 0xc4:
case 0xc1:
+ case 0xce:
+ case 0xcf:
case 0xd9:
case 0xd7:
- default:
nv_wr32(priv, 0x419eac, 0x11100702);
break;
+ default:
+ BUG_ON(1);
+ break;
}
nv_wr32(priv, 0x419eb0, 0x00000003);
nv_wr32(priv, 0x419eb4, 0x00000000);
@@ -1127,6 +1211,8 @@ nvc0_graph_init_tpc(struct nvc0_graph_priv *priv)
case 0xc3:
case 0xc4:
case 0xc1:
+ case 0xce:
+ case 0xcf:
case 0xd9:
case 0xd7:
nv_wr32(priv, 0x419ec8, 0x0e063818);
@@ -1135,10 +1221,12 @@ nvc0_graph_init_tpc(struct nvc0_graph_priv *priv)
break;
case 0xc0:
case 0xc8:
- default:
nv_wr32(priv, 0x419ec8, 0x06060618);
nv_wr32(priv, 0x419ed0, 0x0eff0e38);
break;
+ default:
+ BUG_ON(1);
+ break;
}
nv_wr32(priv, 0x419ed4, 0x011104f1);
nv_wr32(priv, 0x419edc, 0x00000000);
@@ -1407,30 +1495,16 @@ nvc0_graph_init(struct nouveau_object *object)
nvc0_graph_init_obj418880(priv);
nvc0_graph_init_regs(priv);
-
- switch (nv_device(priv)->chipset) {
- case 0xc0:
- case 0xc3:
- case 0xc4:
- case 0xc1:
- case 0xc8:
- case 0xd9:
- case 0xd7:
- nvc0_graph_init_unk40xx(priv);
- nvc0_graph_init_unk44xx(priv);
- nvc0_graph_init_unk78xx(priv);
- nvc0_graph_init_unk60xx(priv);
- nvc0_graph_init_unk64xx(priv);
- nvc0_graph_init_unk58xx(priv);
- nvc0_graph_init_unk80xx(priv);
- nvc0_graph_init_gpc(priv);
- nvc0_graph_init_tpc(priv);
- nvc0_graph_init_unk88xx(priv);
- break;
- default:
- break;
- }
-
+ nvc0_graph_init_unk40xx(priv);
+ nvc0_graph_init_unk44xx(priv);
+ nvc0_graph_init_unk78xx(priv);
+ nvc0_graph_init_unk60xx(priv);
+ nvc0_graph_init_unk64xx(priv);
+ nvc0_graph_init_unk58xx(priv);
+ nvc0_graph_init_unk80xx(priv);
+ nvc0_graph_init_gpc(priv);
+ nvc0_graph_init_tpc(priv);
+ nvc0_graph_init_unk88xx(priv);
nvc0_graph_init_gpc_0(priv);
/*nvc0_graph_init_unitplemented_c242(priv);*/
Copyright © 1996 – 2023 Jason A. Donenfeld. All Rights Reverse Engineered.