diff options
| author |   Radhakrishna Sripada <radhakrishna.sripada@intel.com> | 2022-08-18 16:41:50 -0700 |
|---|---|---|
| committer | Radhakrishna Sripada <radhakrishna.sripada@intel.com> | 2022-08-25 12:52:00 -0700 |
| commit | 61c86578229d2f0a71296663027bd774002f1506 (patch) | |
| tree | 42a679ff46818463650bd1021bde3de617f1b165 | |
| parent | drm/i915/mtl: Add VBT port and AUX_CH mapping (diff) | |
| download | linux-dev-61c86578229d2f0a71296663027bd774002f1506.tar.xz linux-dev-61c86578229d2f0a71296663027bd774002f1506.zip | |
drm/i915/mtl: Add support for MTL in Display Init sequences
The initialization sequence for Meteorlake reuses the sequence for
icelake for most parts. Some changes viz. reset PICA handshake
are added.
Bspec: 49189
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220818234202.451742-10-radhakrishna.sripada@intel.com
| -rw-r--r-- | drivers/gpu/drm/i915/display/intel_display_power.c | 3 | ||||
| -rw-r--r-- | drivers/gpu/drm/i915/i915_reg.h | 3 |
2 files changed, 5 insertions, 1 deletions
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c index f7e8d1ff62cf..9c1fefb2da55 100644 --- a/drivers/gpu/drm/i915/display/intel_display_power.c +++ b/drivers/gpu/drm/i915/display/intel_display_power.c @@ -1382,6 +1382,9 @@ static void intel_pch_reset_handshake(struct drm_i915_private *dev_priv, reset_bits = RESET_PCH_HANDSHAKE_ENABLE; } + if (DISPLAY_VER(dev_priv) >= 14) + reset_bits |= MTL_RESET_PICA_HANDSHAKE_EN; + val = intel_de_read(dev_priv, reg); if (enable) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 2e3aa684cf1b..5f140c26d79f 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -5821,7 +5821,8 @@ _BW_BUDDY1_PAGE_MASK)) #define HSW_NDE_RSTWRN_OPT _MMIO(0x46408) -#define RESET_PCH_HANDSHAKE_ENABLE (1 << 4) +#define MTL_RESET_PICA_HANDSHAKE_EN REG_BIT(6) +#define RESET_PCH_HANDSHAKE_ENABLE REG_BIT(4) #define GEN8_CHICKEN_DCPR_1 _MMIO(0x46430) #define SKL_SELECT_ALTERNATE_DC_EXIT REG_BIT(30) |