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authorJun Lei <Jun.Lei@amd.com>2018-08-13 15:11:44 -0400
committerAlex Deucher <alexander.deucher@amd.com>2018-09-10 22:42:32 -0500
commit61ea4c6f70ffd18eed7fc0d3fb678245f499c756 (patch)
treea9cd18bf5c9f20944560a42cf0b1323b75f92d6b
parentdrm/amd/display: Fix DAL217 tests modify DTN logs for other tests (diff)
drm/amd/display: Add driver-side parsing for CM
Although 4 unique register values exist for gamma modes, two are actually the same (the two RAMs) It’s not possible for caller to understand this HW specific behavior, so some parsing is necessary in driver Signed-off-by: Jun Lei <Jun.Lei@amd.com> Reviewed-by: Wesley Chalmers <Wesley.Chalmers@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
-rw-r--r--drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c29
1 files changed, 25 insertions, 4 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c
index 9288b00e49b4..9c218252004f 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c
@@ -314,14 +314,35 @@ static unsigned int dcn10_get_cm_states(struct dc *dc, char *pBuf, unsigned int
struct dpp *dpp = pool->dpps[i];
struct dcn_dpp_state s = {0};
+
+
+
dpp->funcs->dpp_read_state(dpp, &s);
if (s.is_enabled) {
- chars_printed = snprintf_count(pBuf, remaining_buffer, "%x,%x,%x,%x,%x,%x,"
- "%08x,%08x,%08x,%08x,%08x,%08x"
+ chars_printed = snprintf_count(pBuf, remaining_buffer, "%x,%x,"
+ "%s,%s,%s,"
+ "%x,%08x,%08x,%08x,%08x,%08x,%08x"
"\n",
- dpp->inst, s.igam_input_format, s.igam_lut_mode, s.dgam_lut_mode,
- s.rgam_lut_mode, s.gamut_remap_mode, s.gamut_remap_c11_c12,
+ dpp->inst, s.igam_input_format,
+ (s.igam_lut_mode == 0) ? "BypassFixed" :
+ ((s.igam_lut_mode == 1) ? "BypassFloat" :
+ ((s.igam_lut_mode == 2) ? "RAM" :
+ ((s.igam_lut_mode == 3) ? "RAM" :
+ "Unknown"))),
+ (s.dgam_lut_mode == 0) ? "Bypass" :
+ ((s.dgam_lut_mode == 1) ? "sRGB" :
+ ((s.dgam_lut_mode == 2) ? "Ycc" :
+ ((s.dgam_lut_mode == 3) ? "RAM" :
+ ((s.dgam_lut_mode == 4) ? "RAM" :
+ "Unknown")))),
+ (s.rgam_lut_mode == 0) ? "Bypass" :
+ ((s.rgam_lut_mode == 1) ? "sRGB" :
+ ((s.rgam_lut_mode == 2) ? "Ycc" :
+ ((s.rgam_lut_mode == 3) ? "RAM" :
+ ((s.rgam_lut_mode == 4) ? "RAM" :
+ "Unknown")))),
+ s.gamut_remap_mode, s.gamut_remap_c11_c12,
s.gamut_remap_c13_c14, s.gamut_remap_c21_c22, s.gamut_remap_c23_c24,
s.gamut_remap_c31_c32, s.gamut_remap_c33_c34);