diff options
| author |   Mikko Perttunen <mperttunen@nvidia.com> | 2022-06-27 17:19:57 +0300 |
|---|---|---|
| committer |   Thierry Reding <treding@nvidia.com> | 2022-07-08 16:17:04 +0200 |
| commit | 63a6ef2360bdeffcdd41bcdd86937b6db17b573d (patch) | |
| tree | d4fc53797c191beaabec651add923fd9e11b09f4 | |
| parent | dt-bindings: timer: Add Tegra186 & Tegra234 Timer (diff) | |
| download | linux-dev-63a6ef2360bdeffcdd41bcdd86937b6db17b573d.tar.xz linux-dev-63a6ef2360bdeffcdd41bcdd86937b6db17b573d.zip | |
dt-bindings: Add headers for Host1x and VIC on Tegra234
Add clock, memory controller, powergate and reset dt-binding headers
for Host1x and VIC on Tegra234.
Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
| -rw-r--r-- | include/dt-bindings/clock/tegra234-clock.h | 4 | ||||
| -rw-r--r-- | include/dt-bindings/memory/tegra234-mc.h | 5 | ||||
| -rw-r--r-- | include/dt-bindings/power/tegra234-powergate.h | 1 | ||||
| -rw-r--r-- | include/dt-bindings/reset/tegra234-reset.h | 1 |
4 files changed, 11 insertions, 0 deletions
diff --git a/include/dt-bindings/clock/tegra234-clock.h b/include/dt-bindings/clock/tegra234-clock.h index bab85d9ba8cd..173364a93381 100644 --- a/include/dt-bindings/clock/tegra234-clock.h +++ b/include/dt-bindings/clock/tegra234-clock.h @@ -38,6 +38,8 @@ * throughput and memory controller power. */ #define TEGRA234_CLK_EMC 31U +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X */ +#define TEGRA234_CLK_HOST1X 46U /** @brief output of gate CLK_ENB_FUSE */ #define TEGRA234_CLK_FUSE 40U /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C1 */ @@ -132,6 +134,8 @@ #define TEGRA234_CLK_UARTA 155U /** @brief output of gate CLK_ENB_PEX1_CORE_6 */ #define TEGRA234_CLK_PEX1_C6_CORE 161U +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_VIC */ +#define TEGRA234_CLK_VIC 167U /** @brief output of gate CLK_ENB_PEX2_CORE_7 */ #define TEGRA234_CLK_PEX2_C7_CORE 171U /** @brief output of gate CLK_ENB_PEX2_CORE_8 */ diff --git a/include/dt-bindings/memory/tegra234-mc.h b/include/dt-bindings/memory/tegra234-mc.h index 8b0ddcb715ff..62987b47ce81 100644 --- a/include/dt-bindings/memory/tegra234-mc.h +++ b/include/dt-bindings/memory/tegra234-mc.h @@ -31,6 +31,8 @@ #define TEGRA234_SID_PCIE8 0x09 #define TEGRA234_SID_PCIE10 0x0b #define TEGRA234_SID_BPMP 0x10 +#define TEGRA234_SID_HOST1X 0x27 +#define TEGRA234_SID_VIC 0x34 /* * memory client IDs @@ -38,6 +40,7 @@ /* High-definition audio (HDA) read clients */ #define TEGRA234_MEMORY_CLIENT_HDAR 0x15 +#define TEGRA234_MEMORY_CLIENT_HOST1XDMAR 0x16 /* PCIE6 read clients */ #define TEGRA234_MEMORY_CLIENT_PCIE6AR 0x28 /* PCIE6 write clients */ @@ -86,6 +89,8 @@ #define TEGRA234_MEMORY_CLIENT_MGBEDWR 0x65 /* sdmmcd memory write client */ #define TEGRA234_MEMORY_CLIENT_SDMMCWAB 0x67 +#define TEGRA234_MEMORY_CLIENT_VICSRD 0x6c +#define TEGRA234_MEMORY_CLIENT_VICSWR 0x6d /* BPMP read client */ #define TEGRA234_MEMORY_CLIENT_BPMPR 0x93 /* BPMP write client */ diff --git a/include/dt-bindings/power/tegra234-powergate.h b/include/dt-bindings/power/tegra234-powergate.h index df1d4dd8dcf3..ae9286cef85c 100644 --- a/include/dt-bindings/power/tegra234-powergate.h +++ b/include/dt-bindings/power/tegra234-powergate.h @@ -19,5 +19,6 @@ #define TEGRA234_POWER_DOMAIN_MGBEB 18U #define TEGRA234_POWER_DOMAIN_MGBEC 19U #define TEGRA234_POWER_DOMAIN_MGBED 20U +#define TEGRA234_POWER_DOMAIN_VIC 29U #endif diff --git a/include/dt-bindings/reset/tegra234-reset.h b/include/dt-bindings/reset/tegra234-reset.h index bd58a05f1d94..d48d22b2bc7f 100644 --- a/include/dt-bindings/reset/tegra234-reset.h +++ b/include/dt-bindings/reset/tegra234-reset.h @@ -53,6 +53,7 @@ #define TEGRA234_RESET_MGBE3_PCS 87U #define TEGRA234_RESET_MGBE3_MAC 88U #define TEGRA234_RESET_UARTA 100U +#define TEGRA234_RESET_VIC 113U #define TEGRA234_RESET_PEX0_CORE_0 116U #define TEGRA234_RESET_PEX0_CORE_1 117U #define TEGRA234_RESET_PEX0_CORE_2 118U |