diff options
| author |   Ben Skeggs <bskeggs@redhat.com> | 2013-12-03 16:25:48 +1000 |
|---|---|---|
| committer | Ben Skeggs <bskeggs@redhat.com> | 2014-01-23 13:39:07 +1000 |
| commit | 73216231caf184439c5f6163d01145bdbdfcd00b (patch) | |
| tree | 0c497ccd66354c11629ef9bc56b7465ffc8422cb | |
| parent | drm/nve0/fb/gddr5: merge a fix from ddr3 for one of the timing settings (diff) | |
drm/nve0/fb: turn off some bits in 10f584 at init
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
| -rw-r--r-- | drivers/gpu/drm/nouveau/core/subdev/fb/ramnve0.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/ramnve0.c b/drivers/gpu/drm/nouveau/core/subdev/fb/ramnve0.c index 025c291514db..3257c522a021 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/fb/ramnve0.c +++ b/drivers/gpu/drm/nouveau/core/subdev/fb/ramnve0.c @@ -1178,6 +1178,7 @@ nve0_ram_init(struct nouveau_object *object) data += 4; } nv_wr32(pfb, 0x10f65c, save); + nv_mask(pfb, 0x10f584, 0x11000000, 0x00000000); switch (ram->base.type) { case NV_MEM_TYPE_GDDR5: |