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| author |   Martin Blumenstingl <martin.blumenstingl@googlemail.com> | 2020-06-20 18:36:53 +0200 |
|---|---|---|
| committer |   Kevin Hilman <khilman@baylibre.com> | 2020-07-13 11:58:15 -0700 |
| commit | 73501b890a6f15460613878b463319d0e0cd1632 (patch) | |
| tree | cd1258c7ad31c2f2904dd5761bec8035314772e9 | |
| parent | ARM: dts: meson: add the SDHC MMC controller (diff) | |
| download | linux-dev-73501b890a6f15460613878b463319d0e0cd1632.tar.xz linux-dev-73501b890a6f15460613878b463319d0e0cd1632.zip | |
ARM: dts: meson8b: ec100: enable the SDHC controller
EC-100 has built-in eMMC flash which is hard-wired to 3.3V VCC (which
means it's limited to high-speed MMC modes). Enable the SDHC controller
to access the contents of the eMMC flash.
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Link: https://lore.kernel.org/r/20200620163654.37207-3-martin.blumenstingl@googlemail.com
| -rw-r--r-- | arch/arm/boot/dts/meson8b-ec100.dts | 25 |
1 files changed, 25 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/meson8b-ec100.dts b/arch/arm/boot/dts/meson8b-ec100.dts index 163a200d5a7b..ed06102a4014 100644 --- a/arch/arm/boot/dts/meson8b-ec100.dts +++ b/arch/arm/boot/dts/meson8b-ec100.dts @@ -27,6 +27,11 @@ reg = <0x40000000 0x40000000>; }; + emmc_pwrseq: emmc-pwrseq { + compatible = "mmc-pwrseq-emmc"; + reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>; + }; + gpio-keys { compatible = "gpio-keys-polled"; #address-cells = <1>; @@ -299,6 +304,26 @@ vref-supply = <&vcc_1v8>; }; +&sdhc { + status = "okay"; + + pinctrl-0 = <&sdxc_c_pins>; + pinctrl-names = "default"; + + bus-width = <8>; + max-frequency = <50000000>; + + cap-mmc-highspeed; + disable-wp; + non-removable; + no-sdio; + + mmc-pwrseq = <&emmc_pwrseq>; + + vmmc-supply = <&vcc_3v3>; + vqmmc-supply = <&vcc_3v3>; +}; + &sdio { status = "okay"; |