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| author |   Masahiro Yamada <yamada.masahiro@socionext.com> | 2017-09-29 23:12:57 +0900 |
|---|---|---|
| committer |   Boris Brezillon <boris.brezillon@free-electrons.com> | 2017-10-07 11:28:06 +0200 |
| commit | 7963f58cbf3a722c93f946c80a12f185b86dc45c (patch) | |
| tree | 0ccc6ea49a657c82c9bc6dc91e412b5b5a46f1f6 | |
| parent | mtd: nand: pxa3xx_nand: Update Kconfig information (diff) | |
| download | linux-dev-7963f58cbf3a722c93f946c80a12f185b86dc45c.tar.xz linux-dev-7963f58cbf3a722c93f946c80a12f185b86dc45c.zip | |
mtd: nand: denali: fix setup_data_interface to meet tCCS delay
The WE_2_RE register specifies the number of clock cycles inserted
between the rising edge of #WE and the falling edge of #RE.
The current setup_data_interface implementation takes care of tWHR,
but tCCS is missing. Wait for max(tCSS, tWHR) to meet the spec.
With setup_data_interface() properly programmed, the Denali NAND
controller can observe the timing, so NAND_WAIT_TCCS flag is unneeded.
Clarify this in the comment block.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
| -rw-r--r-- | drivers/mtd/nand/denali.c | 10 |
1 files changed, 8 insertions, 2 deletions
diff --git a/drivers/mtd/nand/denali.c b/drivers/mtd/nand/denali.c index 0b268ec88435..5124f8ae8c04 100644 --- a/drivers/mtd/nand/denali.c +++ b/drivers/mtd/nand/denali.c @@ -1004,8 +1004,14 @@ static int denali_setup_data_interface(struct mtd_info *mtd, int chipnr, tmp |= FIELD_PREP(RE_2_RE__VALUE, re_2_re); iowrite32(tmp, denali->reg + RE_2_RE); - /* tWHR -> WE_2_RE */ - we_2_re = DIV_ROUND_UP(timings->tWHR_min, t_clk); + /* + * tCCS, tWHR -> WE_2_RE + * + * With WE_2_RE properly set, the Denali controller automatically takes + * care of the delay; the driver need not set NAND_WAIT_TCCS. + */ + we_2_re = DIV_ROUND_UP(max(timings->tCCS_min, timings->tWHR_min), + t_clk); we_2_re = min_t(int, we_2_re, TWHR2_AND_WE_2_RE__WE_2_RE); tmp = ioread32(denali->reg + TWHR2_AND_WE_2_RE); |