diff options
| author |   Andy Shevchenko <andriy.shevchenko@linux.intel.com> | 2019-10-25 21:25:43 +0300 |
|---|---|---|
| committer | Andy Shevchenko <andriy.shevchenko@linux.intel.com> | 2019-12-13 16:48:47 +0200 |
| commit | 7c0bc7bb39ac89a454317d55262c06ec0048628b (patch) | |
| tree | d0c3e97559211d9f419fb2d488439ee65b9d6e15 | |
| parent | pinctrl: lynxpoint: Use raw_spinlock for locking (diff) | |
| download | linux-dev-7c0bc7bb39ac89a454317d55262c06ec0048628b.tar.xz linux-dev-7c0bc7bb39ac89a454317d55262c06ec0048628b.zip | |
pinctrl: lynxpoint: Correct amount of pins
When we count from 0 it's possible to get into off-by-one error.
That's what had happened to this driver. So, correct amount of pins
and related typos in the code.
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
| -rw-r--r-- | drivers/pinctrl/intel/pinctrl-lynxpoint.c | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/drivers/pinctrl/intel/pinctrl-lynxpoint.c b/drivers/pinctrl/intel/pinctrl-lynxpoint.c index c30fd86846a7..162fc38c929d 100644 --- a/drivers/pinctrl/intel/pinctrl-lynxpoint.c +++ b/drivers/pinctrl/intel/pinctrl-lynxpoint.c @@ -18,9 +18,9 @@ #include <linux/slab.h> #include <linux/types.h> -/* LynxPoint chipset has support for 94 gpio pins */ +/* LynxPoint chipset has support for 95 GPIO pins */ -#define LP_NUM_GPIO 94 +#define LP_NUM_GPIO 95 /* Bitmapped register offsets */ #define LP_ACPI_OWNED 0x00 /* Bitmap, set by bios, 0: pin reserved for ACPI */ @@ -54,11 +54,11 @@ struct lp_gpio { /* * Lynxpoint gpios are controlled through both bitmapped registers and * per gpio specific registers. The bitmapped registers are in chunks of - * 3 x 32bit registers to cover all 94 gpios + * 3 x 32bit registers to cover all 95 GPIOs * * per gpio specific registers consist of two 32bit registers per gpio - * (LP_CONFIG1 and LP_CONFIG2), with 94 gpios there's a total of - * 188 config registers. + * (LP_CONFIG1 and LP_CONFIG2), with 95 GPIOs there's a total of + * 190 config registers. * * A simplified view of the register layout look like this: * @@ -67,7 +67,7 @@ struct lp_gpio { * LP_ACPI_OWNED[94:64] gpio ownerships for gpios 63-94 * ... * LP_INT_ENABLE[31:0] ... - * LP_INT_ENABLE[63:31] ... + * LP_INT_ENABLE[63:32] ... * LP_INT_ENABLE[94:64] ... * LP0_CONFIG1 (gpio 0) config1 reg for gpio 0 (per gpio registers) * LP0_CONFIG2 (gpio 0) config2 reg for gpio 0 |