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authorMarc Zyngier <maz@kernel.org>2019-10-02 10:06:13 +0100
committerCatalin Marinas <catalin.marinas@arm.com>2019-10-15 12:26:15 +0100
commit7e3a57fa6ca831fa232a7cd4659eaed674236810 (patch)
tree7fd7d5d9cbd63cc17d7901d92260b5470450f79e
parentarm64: Relax ICC_PMR_EL1 accesses when ICC_CTLR_EL1.PMHE is clear (diff)
downloadlinux-dev-7e3a57fa6ca831fa232a7cd4659eaed674236810.tar.xz
linux-dev-7e3a57fa6ca831fa232a7cd4659eaed674236810.zip
arm64: Document ICC_CTLR_EL3.PMHE setting requirements
It goes without saying, but better saying it: the kernel expects ICC_CTLR_EL3.PMHE to have the same value across all CPUs, and for that setting not to change during the lifetime of the kernel. Signed-off-by: Marc Zyngier <maz@kernel.org> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
-rw-r--r--Documentation/arm64/booting.rst3
1 files changed, 3 insertions, 0 deletions
diff --git a/Documentation/arm64/booting.rst b/Documentation/arm64/booting.rst
index d3f3a60fbf25..5d78a6f5b0ae 100644
--- a/Documentation/arm64/booting.rst
+++ b/Documentation/arm64/booting.rst
@@ -213,6 +213,9 @@ Before jumping into the kernel, the following conditions must be met:
- ICC_SRE_EL3.Enable (bit 3) must be initialiased to 0b1.
- ICC_SRE_EL3.SRE (bit 0) must be initialised to 0b1.
+ - ICC_CTLR_EL3.PMHE (bit 6) must be set to the same value across
+ all CPUs the kernel is executing on, and must stay constant
+ for the lifetime of the kernel.
- If the kernel is entered at EL1: