diff options
| author |   Hugues Fruchet <hugues.fruchet@foss.st.com> | 2022-05-16 10:19:32 +0100 |
|---|---|---|
| committer |   Mauro Carvalho Chehab <mchehab@kernel.org> | 2022-07-08 15:12:43 +0100 |
| commit | 81bf9e2e6e857cd8bed7062c22af09fb34881340 (patch) | |
| tree | 0d96aa6ee63a85f6763476fa2e8e7a0b14fd5c90 | |
| parent | media: ov7251: Fix multiple problems in s_stream callback (diff) | |
media: st-mipid02: add support of pixel clock polarity
Add support of pixel clock polarity.
Signed-off-by: Hugues Fruchet <hugues.fruchet@foss.st.com>
Reviewed-by: Benjamin Mugnier <benjamin.mugnier@foss.st.com>
Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab@kernel.org>
| -rw-r--r-- | drivers/media/i2c/st-mipid02.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/drivers/media/i2c/st-mipid02.c b/drivers/media/i2c/st-mipid02.c index ef976d085d72..59b48026c752 100644 --- a/drivers/media/i2c/st-mipid02.c +++ b/drivers/media/i2c/st-mipid02.c @@ -50,6 +50,7 @@ /* Bits definition for MIPID02_MODE_REG2 */ #define MODE_HSYNC_ACTIVE_HIGH BIT(1) #define MODE_VSYNC_ACTIVE_HIGH BIT(2) +#define MODE_PCLK_SAMPLE_RISING BIT(3) /* Bits definition for MIPID02_DATA_SELECTION_CTRL */ #define SELECTION_MANUAL_DATA BIT(2) #define SELECTION_MANUAL_WIDTH BIT(3) @@ -494,6 +495,8 @@ static int mipid02_configure_from_tx(struct mipid02_dev *bridge) bridge->r.mode_reg2 |= MODE_HSYNC_ACTIVE_HIGH; if (ep->bus.parallel.flags & V4L2_MBUS_VSYNC_ACTIVE_HIGH) bridge->r.mode_reg2 |= MODE_VSYNC_ACTIVE_HIGH; + if (ep->bus.parallel.flags & V4L2_MBUS_PCLK_SAMPLE_RISING) + bridge->r.mode_reg2 |= MODE_PCLK_SAMPLE_RISING; return 0; } |