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authorStafford Horne <shorne@gmail.com>2022-06-15 08:54:26 +0900
committerStafford Horne <shorne@gmail.com>2022-06-28 17:31:15 +0900
commit8520501346ed8d1c4a6dfa751cb57328a9c843f1 (patch)
tree4a9cb6949ee81cd8c0fe7a51faa5bf961eded371
parentLinux 5.19-rc4 (diff)
downloadlinux-dev-8520501346ed8d1c4a6dfa751cb57328a9c843f1.tar.xz
linux-dev-8520501346ed8d1c4a6dfa751cb57328a9c843f1.zip
irqchip: or1k-pic: Undefine mask_ack for level triggered hardware
The mask_ack operation clears the interrupt by writing to the PICSR register. This we don't want for level triggered interrupt because it does not actually clear the interrupt on the source hardware. This was causing issues in qemu with multi core setups where interrupts would continue to fire even though they had been cleared in PICSR. Just remove the mask_ack operation. Acked-by: Marc Zyngier <maz@kernel.org> Signed-off-by: Stafford Horne <shorne@gmail.com>
-rw-r--r--drivers/irqchip/irq-or1k-pic.c1
1 files changed, 0 insertions, 1 deletions
diff --git a/drivers/irqchip/irq-or1k-pic.c b/drivers/irqchip/irq-or1k-pic.c
index 49b47e787644..f289ccd95291 100644
--- a/drivers/irqchip/irq-or1k-pic.c
+++ b/drivers/irqchip/irq-or1k-pic.c
@@ -66,7 +66,6 @@ static struct or1k_pic_dev or1k_pic_level = {
.name = "or1k-PIC-level",
.irq_unmask = or1k_pic_unmask,
.irq_mask = or1k_pic_mask,
- .irq_mask_ack = or1k_pic_mask_ack,
},
.handle = handle_level_irq,
.flags = IRQ_LEVEL | IRQ_NOPROBE,