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| author |   Thierry Reding <treding@nvidia.com> | 2017-06-26 17:38:43 +0200 |
|---|---|---|
| committer | Thierry Reding <treding@nvidia.com> | 2017-12-13 13:15:43 +0100 |
| commit | 85593b75ee715490f0207d95de4978fc465fda89 (patch) | |
| tree | e8c520fa7ecb30699f37a7f5bbd66805de76cc78 | |
| parent | arm64: tegra: Add MISC registers on Tegra186 (diff) | |
| download | linux-dev-85593b75ee715490f0207d95de4978fc465fda89.tar.xz linux-dev-85593b75ee715490f0207d95de4978fc465fda89.zip | |
arm64: tegra: Add FUSE block on Tegra186
The FUSE register block found on Tegra186 SoCs encodes various settings,
such as calibration data for other blocks.
Signed-off-by: Thierry Reding <treding@nvidia.com>
| -rw-r--r-- | arch/arm64/boot/dts/nvidia/tegra186.dtsi | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia/tegra186.dtsi index 11795dbd30f0..c9f4a6dc162c 100644 --- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi @@ -265,6 +265,13 @@ status = "disabled"; }; + fuse@3820000 { + compatible = "nvidia,tegra186-efuse"; + reg = <0x0 0x03820000 0x0 0x10000>; + clocks = <&bpmp TEGRA186_CLK_FUSE>; + clock-names = "fuse"; + }; + gic: interrupt-controller@3881000 { compatible = "arm,gic-400"; #interrupt-cells = <3>; |