diff options
| author |   Ard Biesheuvel <ard.biesheuvel@linaro.org> | 2018-08-27 13:02:43 +0200 |
|---|---|---|
| committer |   Catalin Marinas <catalin.marinas@arm.com> | 2018-09-10 16:10:09 +0100 |
| commit | 86d0dd34eafffbc76a81aba6ae2d71927d3835a8 (patch) | |
| tree | b083d6e8636d919c268a8b6fef9d0311e77f50dd | |
| parent | lib/crc32: make core crc32() routines weak so they can be overridden (diff) | |
| download | linux-dev-86d0dd34eafffbc76a81aba6ae2d71927d3835a8.tar.xz linux-dev-86d0dd34eafffbc76a81aba6ae2d71927d3835a8.zip | |
arm64: cpufeature: add feature for CRC32 instructions
Add a CRC32 feature bit and wire it up to the CPU id register so we
will be able to use alternatives patching for CRC32 operations.
Acked-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
| -rw-r--r-- | arch/arm64/include/asm/cpucaps.h | 3 | ||||
| -rw-r--r-- | arch/arm64/kernel/cpufeature.c | 9 |
2 files changed, 11 insertions, 1 deletions
diff --git a/arch/arm64/include/asm/cpucaps.h b/arch/arm64/include/asm/cpucaps.h index ae1f70450fb2..9932aca9704b 100644 --- a/arch/arm64/include/asm/cpucaps.h +++ b/arch/arm64/include/asm/cpucaps.h @@ -51,7 +51,8 @@ #define ARM64_SSBD 30 #define ARM64_MISMATCHED_CACHE_TYPE 31 #define ARM64_HAS_STAGE2_FWB 32 +#define ARM64_HAS_CRC32 33 -#define ARM64_NCAPS 33 +#define ARM64_NCAPS 34 #endif /* __ASM_CPUCAPS_H */ diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c index e238b7932096..7626b80128f5 100644 --- a/arch/arm64/kernel/cpufeature.c +++ b/arch/arm64/kernel/cpufeature.c @@ -1222,6 +1222,15 @@ static const struct arm64_cpu_capabilities arm64_features[] = { .cpu_enable = cpu_enable_hw_dbm, }, #endif + { + .desc = "CRC32 instructions", + .capability = ARM64_HAS_CRC32, + .type = ARM64_CPUCAP_SYSTEM_FEATURE, + .matches = has_cpuid_feature, + .sys_reg = SYS_ID_AA64ISAR0_EL1, + .field_pos = ID_AA64ISAR0_CRC32_SHIFT, + .min_field_value = 1, + }, {}, }; |