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| author |   Sowjanya Komatineni <skomatineni@nvidia.com> | 2020-12-21 13:17:31 -0800 |
|---|---|---|
| committer |   Thierry Reding <treding@nvidia.com> | 2021-01-27 00:10:14 +0100 |
| commit | 88893986338beebcf5317bda80d43d4f6f7f7c7c (patch) | |
| tree | 6c5575ba3f087bd8e6f9e5afef8c837e3863b3bb | |
| parent | Linux 5.11-rc1 (diff) | |
| download | linux-dev-88893986338beebcf5317bda80d43d4f6f7f7c7c.tar.xz linux-dev-88893986338beebcf5317bda80d43d4f6f7f7c7c.zip | |
dt-bindings: clock: tegra: Add clock ID TEGRA210_CLK_QSPI_PM
Tegra210 QSPI clock output has divider DIV2_SEL which will be enabled
when using DDR interface mode.
This patch adds clock ID for this to dt-binding.
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
| -rw-r--r-- | include/dt-bindings/clock/tegra210-car.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/include/dt-bindings/clock/tegra210-car.h b/include/dt-bindings/clock/tegra210-car.h index ab8b8a737a0a..9cfcc3baa52c 100644 --- a/include/dt-bindings/clock/tegra210-car.h +++ b/include/dt-bindings/clock/tegra210-car.h @@ -307,7 +307,7 @@ #define TEGRA210_CLK_AUDIO4 275 #define TEGRA210_CLK_SPDIF 276 /* 277 */ -/* 278 */ +#define TEGRA210_CLK_QSPI_PM 278 /* 279 */ /* 280 */ #define TEGRA210_CLK_SOR0_LVDS 281 /* deprecated */ |