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authorArd Biesheuvel <ardb@kernel.org>2022-04-20 09:57:45 +0100
committerRussell King (Oracle) <rmk+kernel@armlinux.org.uk>2022-05-20 12:33:47 +0100
commit892c608a7d7380b9a7c8f0d6aab99b763fd6fd3f (patch)
tree2414479effffccb130956bc04d7505d42625d0e6
parentARM: 9198/1: spectre-bhb: simplify BPIALL vector macro (diff)
downloadlinux-dev-892c608a7d7380b9a7c8f0d6aab99b763fd6fd3f.tar.xz
linux-dev-892c608a7d7380b9a7c8f0d6aab99b763fd6fd3f.zip
ARM: 9199/1: spectre-bhb: use local DSB and elide ISB in loop8 sequence
The loop8 mitigation for Spectre-BHB only requires a CPU local DSB rather than a systemwide one, which is much more costly. And by the same reasoning as why it is justified to omit the ISB after BPIALL, we can also elide the ISB and rely on the exception return for the context synchronization. Signed-off-by: Ard Biesheuvel <ardb@kernel.org> Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
-rw-r--r--arch/arm/kernel/entry-armv.S5
-rw-r--r--arch/arm/kernel/entry-common.S2
2 files changed, 4 insertions, 3 deletions
diff --git a/arch/arm/kernel/entry-armv.S b/arch/arm/kernel/entry-armv.S
index 87cb06316aca..43ab77553e84 100644
--- a/arch/arm/kernel/entry-armv.S
+++ b/arch/arm/kernel/entry-armv.S
@@ -1131,8 +1131,9 @@ vector_bhb_loop8_\name:
3: W(b) . + 4
subs r0, r0, #1
bne 3b
- dsb
- isb
+ dsb nsh
+ @ isb not needed due to "movs pc, lr" in the vector stub
+ @ which gives a "context synchronisation".
b 2b
ENDPROC(vector_bhb_loop8_\name)
.previous
diff --git a/arch/arm/kernel/entry-common.S b/arch/arm/kernel/entry-common.S
index ad3210e5cb69..7aa3ded4af92 100644
--- a/arch/arm/kernel/entry-common.S
+++ b/arch/arm/kernel/entry-common.S
@@ -164,7 +164,7 @@ ENTRY(vector_bhb_loop8_swi)
1: b 2f
2: subs r8, r8, #1
bne 1b
- dsb
+ dsb nsh
isb
b 3f
ENDPROC(vector_bhb_loop8_swi)