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| author |   Suravee Suthikulpanit <suravee.suthikulpanit@amd.com> | 2018-06-13 13:43:10 -0500 |
|---|---|---|
| committer |   Thomas Gleixner <tglx@linutronix.de> | 2018-06-22 21:21:49 +0200 |
| commit | 964d978433a4b9aa1368ff71227ca0027dd1e32f (patch) | |
| tree | 4ec8e2677665c624544224831fe0aa9d50c49133 | |
| parent | Merge branch 'linus' into x86/urgent (diff) | |
| download | linux-dev-964d978433a4b9aa1368ff71227ca0027dd1e32f.tar.xz linux-dev-964d978433a4b9aa1368ff71227ca0027dd1e32f.zip | |
x86/CPU/AMD: Fix LLC ID bit-shift calculation
The current logic incorrectly calculates the LLC ID from the APIC ID.
Unless specified otherwise, the LLC ID should be calculated by removing
the Core and Thread ID bits from the least significant end of the APIC
ID. For more info, see "ApicId Enumeration Requirements" in any Fam17h
PPR document.
[ bp: Improve commit message. ]
Fixes: 68091ee7ac3c ("Calculate last level cache ID from number of sharing threads")
Signed-off-by: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
Signed-off-by: Borislav Petkov <bp@suse.de>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Link: http://lkml.kernel.org/r/1528915390-30533-1-git-send-email-suravee.suthikulpanit@amd.com
| -rw-r--r-- | arch/x86/kernel/cpu/cacheinfo.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/x86/kernel/cpu/cacheinfo.c b/arch/x86/kernel/cpu/cacheinfo.c index 38354c66df81..0c5fcbd998cf 100644 --- a/arch/x86/kernel/cpu/cacheinfo.c +++ b/arch/x86/kernel/cpu/cacheinfo.c @@ -671,7 +671,7 @@ void cacheinfo_amd_init_llc_id(struct cpuinfo_x86 *c, int cpu, u8 node_id) num_sharing_cache = ((eax >> 14) & 0xfff) + 1; if (num_sharing_cache) { - int bits = get_count_order(num_sharing_cache) - 1; + int bits = get_count_order(num_sharing_cache); per_cpu(cpu_llc_id, cpu) = c->apicid >> bits; } |