diff options
| author |   Likun Gao <Likun.Gao@amd.com> | 2020-03-06 17:01:22 +0800 |
|---|---|---|
| committer |   Alex Deucher <alexander.deucher@amd.com> | 2020-06-03 13:52:10 -0400 |
| commit | 9aa60213403b12f2ef393a62b52064a2211cc320 (patch) | |
| tree | b1ebcb557972befa3f01ce24e88daae1838581a7 | |
| parent | drm/amd/powerplay: make gfx ds can be configure for sienna_cichlid (diff) | |
drm/amd/powerplay: Enable SOCCLK ULV for sienna_cichlid
Enable FW DSTATE for sienna_cichlid.
Enable DF CSTATE for sienna_cichlid.
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| -rw-r--r-- | drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c b/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c index 49e157f2b39f..a91e6f753bea 100644 --- a/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c +++ b/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c @@ -272,6 +272,8 @@ sienna_cichlid_get_allowed_feature_mask(struct smu_context *smu, *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT) | FEATURE_MASK(FEATURE_DPM_FCLK_BIT) | FEATURE_MASK(FEATURE_DS_SOCCLK_BIT) + | FEATURE_MASK(FEATURE_FW_DSTATE_BIT) + | FEATURE_MASK(FEATURE_DF_CSTATE_BIT) | FEATURE_MASK(FEATURE_THERMAL_BIT); if (adev->pm.pp_feature & PP_SCLK_DPM_MASK) |