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authorJiaxin Yu <jiaxin.yu@mediatek.com>2019-09-27 18:31:57 +0800
committerMark Brown <broonie@kernel.org>2019-10-08 13:39:45 +0100
commit9e985503ee4b23d576c303a17dfe52cfc8f32727 (patch)
tree8022e05fe2233c43dd815cf98cbce7a246d5552b
parentdt-bindings: medaitek: mt8183: add property "resets" && "reset-names" (diff)
downloadlinux-dev-9e985503ee4b23d576c303a17dfe52cfc8f32727.tar.xz
linux-dev-9e985503ee4b23d576c303a17dfe52cfc8f32727.zip
ASoC: mt8183: fix audio playback slowly after playback during bootup
Before regmap_reinit_cache we must reset audio regs as default values. So we use reset controller unit(toprgu) to reset audio hw. Signed-off-by: Jiaxin Yu <jiaxin.yu@mediatek.com> Reviewed-by: Yingjoe Chen <yingjoe.chen@mediatek.com> Link: https://lore.kernel.org/r/1569580317-21181-5-git-send-email-jiaxin.yu@mediatek.com Signed-off-by: Mark Brown <broonie@kernel.org>
-rw-r--r--sound/soc/mediatek/mt8183/mt8183-afe-pcm.c15
1 files changed, 15 insertions, 0 deletions
diff --git a/sound/soc/mediatek/mt8183/mt8183-afe-pcm.c b/sound/soc/mediatek/mt8183/mt8183-afe-pcm.c
index 4a31106d3471..721632386a50 100644
--- a/sound/soc/mediatek/mt8183/mt8183-afe-pcm.c
+++ b/sound/soc/mediatek/mt8183/mt8183-afe-pcm.c
@@ -11,6 +11,7 @@
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/pm_runtime.h>
+#include <linux/reset.h>
#include "mt8183-afe-common.h"
#include "mt8183-afe-clk.h"
@@ -1089,6 +1090,7 @@ static int mt8183_afe_pcm_dev_probe(struct platform_device *pdev)
struct mtk_base_afe *afe;
struct mt8183_afe_private *afe_priv;
struct device *dev;
+ struct reset_control *rstc;
int i, irq_id, ret;
afe = devm_kzalloc(&pdev->dev, sizeof(*afe), GFP_KERNEL);
@@ -1126,6 +1128,19 @@ static int mt8183_afe_pcm_dev_probe(struct platform_device *pdev)
return ret;
}
+ rstc = devm_reset_control_get(dev, "audiosys");
+ if (IS_ERR(rstc)) {
+ ret = PTR_ERR(rstc);
+ dev_err(dev, "could not get audiosys reset:%d\n", ret);
+ return ret;
+ }
+
+ ret = reset_control_reset(rstc);
+ if (ret) {
+ dev_err(dev, "failed to trigger audio reset:%d\n", ret);
+ return ret;
+ }
+
/* enable clock for regcache get default value from hw */
afe_priv->pm_runtime_bypass_reg_ctl = true;
pm_runtime_get_sync(&pdev->dev);