diff options
| author |   Venkata Sandeep Dhanalakota <venkata.s.dhanalakota@intel.com> | 2020-11-05 17:18:42 -0800 |
|---|---|---|
| committer |   Chris Wilson <chris@chris-wilson.co.uk> | 2020-11-06 10:04:15 +0000 |
| commit | ad18fa0f5f052046cad96fee762b5c64f42dd86a (patch) | |
| tree | 928c8755b03326c3a166d5b9d3caa8831b1296f7 | |
| parent | drm/i915/gem: Pull phys pread/pwrite implementations to the backend (diff) | |
| download | linux-dev-ad18fa0f5f052046cad96fee762b5c64f42dd86a.tar.xz linux-dev-ad18fa0f5f052046cad96fee762b5c64f42dd86a.zip | |
drm/i915: Correctly set SFC capability for video engines
SFC capability of video engines is not set correctly because i915
is testing for incorrect bits.
Fixes: c5d3e39caa45 ("drm/i915: Engine discovery query")
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Signed-off-by: Venkata Sandeep Dhanalakota <venkata.s.dhanalakota@intel.com>
Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Cc: <stable@vger.kernel.org> # v5.3+
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Link: https://patchwork.freedesktop.org/patch/msgid/20201106011842.36203-1-daniele.ceraolospurio@intel.com
| -rw-r--r-- | drivers/gpu/drm/i915/gt/intel_engine_cs.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c index b80d7285db2f..9018582e7229 100644 --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c @@ -372,7 +372,8 @@ static void __setup_engine_capabilities(struct intel_engine_cs *engine) * instances. */ if ((INTEL_GEN(i915) >= 11 && - engine->gt->info.vdbox_sfc_access & engine->mask) || + (engine->gt->info.vdbox_sfc_access & + BIT(engine->instance))) || (INTEL_GEN(i915) >= 9 && engine->instance == 0)) engine->uabi_capabilities |= I915_VIDEO_AND_ENHANCE_CLASS_CAPABILITY_SFC; |