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| author |   Lucas Stach <l.stach@pengutronix.de> | 2019-04-15 15:59:22 +0200 |
|---|---|---|
| committer |   Shawn Guo <shawnguo@kernel.org> | 2019-04-22 09:26:05 +0800 |
| commit | ade5a57e304e2a880135549393970de03bde4a3a (patch) | |
| tree | 47c8e1bced6b7f0edcb6721ab0aff8ac1b415954 | |
| parent | arm64: dts: fsl: imx8mq-evk: link regulator to GPU domain (diff) | |
| download | linux-dev-ade5a57e304e2a880135549393970de03bde4a3a.tar.xz linux-dev-ade5a57e304e2a880135549393970de03bde4a3a.zip | |
arm64: dts: imx8mq: fix GPU clock frequency
v2 of "clk: imx: Refactor entire sccg pll clk" dropped the implicit
reparenting of the PLL output from the bypass clock to the real
PLL. The commit introducing the GPU node had only been tested against
v1 of this patch. Without an explicit reparent to the real PLL the
GPU is stuck at the bypass clock rate of 25MHz, serverly hampering
performance.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Abel Vesa <abel.vesa@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
| -rw-r--r-- | arch/arm64/boot/dts/freescale/imx8mq.dtsi | 8 |
1 files changed, 5 insertions, 3 deletions
diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi index 7c0b12ad7ccf..6d635ba0904c 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi @@ -827,13 +827,15 @@ assigned-clocks = <&clk IMX8MQ_CLK_GPU_CORE_SRC>, <&clk IMX8MQ_CLK_GPU_SHADER_SRC>, <&clk IMX8MQ_CLK_GPU_AXI>, - <&clk IMX8MQ_CLK_GPU_AHB>; + <&clk IMX8MQ_CLK_GPU_AHB>, + <&clk IMX8MQ_GPU_PLL_BYPASS>; assigned-clock-parents = <&clk IMX8MQ_GPU_PLL_OUT>, <&clk IMX8MQ_GPU_PLL_OUT>, <&clk IMX8MQ_GPU_PLL_OUT>, - <&clk IMX8MQ_GPU_PLL_OUT>; + <&clk IMX8MQ_GPU_PLL_OUT>, + <&clk IMX8MQ_GPU_PLL>; assigned-clock-rates = <800000000>, <800000000>, - <800000000>, <800000000>; + <800000000>, <800000000>, <0>; power-domains = <&pgc_gpu>; }; |