diff options
| author |   Martin Blumenstingl <martin.blumenstingl@googlemail.com> | 2020-06-20 18:10:08 +0200 |
|---|---|---|
| committer |   Kevin Hilman <khilman@baylibre.com> | 2020-07-13 11:56:23 -0700 |
| commit | aecc72b14d11327804f7ca1fc76ca88a22cc1136 (patch) | |
| tree | c445f777584e49a51b41ce9cf7022821338f4dfa | |
| parent | Linux 5.8-rc1 (diff) | |
| download | linux-dev-aecc72b14d11327804f7ca1fc76ca88a22cc1136.tar.xz linux-dev-aecc72b14d11327804f7ca1fc76ca88a22cc1136.zip | |
ARM: dts: meson8: add power domain controller
The Meson8 SoCs have a power domain controller which can turn on/off
various register areas (such as: Ethernet, VPU, etc.).
Add the main "pwrc" controller and configure the Ethernet power domain.
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
Link: https://lore.kernel.org/r/20200620161010.23171-2-martin.blumenstingl@googlemail.com
| -rw-r--r-- | arch/arm/boot/dts/meson8.dtsi | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/meson8.dtsi b/arch/arm/boot/dts/meson8.dtsi index eedb92526968..d09d19d4423a 100644 --- a/arch/arm/boot/dts/meson8.dtsi +++ b/arch/arm/boot/dts/meson8.dtsi @@ -6,6 +6,7 @@ #include <dt-bindings/clock/meson8-ddr-clkc.h> #include <dt-bindings/clock/meson8b-clkc.h> #include <dt-bindings/gpio/meson8-gpio.h> +#include <dt-bindings/power/meson8-power.h> #include <dt-bindings/reset/amlogic,meson8b-clkc-reset.h> #include <dt-bindings/reset/amlogic,meson8b-reset.h> #include "meson.dtsi" @@ -454,6 +455,8 @@ ðmac { clocks = <&clkc CLKID_ETH>; clock-names = "stmmaceth"; + + power-domains = <&pwrc PWRC_MESON8_ETHERNET_MEM_ID>; }; &gpio_intc { @@ -469,6 +472,16 @@ #clock-cells = <1>; #reset-cells = <1>; }; + + pwrc: power-controller { + compatible = "amlogic,meson8-pwrc"; + #power-domain-cells = <1>; + amlogic,ao-sysctrl = <&pmu>; + clocks = <&clkc CLKID_VPU>; + clock-names = "vpu"; + assigned-clocks = <&clkc CLKID_VPU>; + assigned-clock-rates = <364285714>; + }; }; &hwrng { |