diff options
| author |   Anton Blanchard <anton@samba.org> | 2015-10-29 11:43:54 +1100 |
|---|---|---|
| committer |   Michael Ellerman <mpe@ellerman.id.au> | 2015-12-01 13:52:24 +1100 |
| commit | af72ab646a6bee724f190820e8f56497a5b635f0 (patch) | |
| tree | af3168c4f8c75c8bfd71ecc4182af01d444dbdf1 | |
| parent | powerpc: Don't disable kernel FP/VMX/VSX MSR bits on context switch (diff) | |
| download | linux-dev-af72ab646a6bee724f190820e8f56497a5b635f0.tar.xz linux-dev-af72ab646a6bee724f190820e8f56497a5b635f0.zip | |
powerpc: Don't disable MSR bits in do_load_up_transact_*() functions
Similar to the non TM load_up_*() functions, don't disable the MSR
bits on the way out.
Signed-off-by: Anton Blanchard <anton@samba.org>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
| -rw-r--r-- | arch/powerpc/kernel/fpu.S | 4 | ||||
| -rw-r--r-- | arch/powerpc/kernel/vector.S | 4 |
2 files changed, 0 insertions, 8 deletions
diff --git a/arch/powerpc/kernel/fpu.S b/arch/powerpc/kernel/fpu.S index 9ad236e5d2c9..38eb79b8a034 100644 --- a/arch/powerpc/kernel/fpu.S +++ b/arch/powerpc/kernel/fpu.S @@ -73,10 +73,6 @@ END_FTR_SECTION_IFSET(CPU_FTR_VSX) MTFSF_L(fr0) REST_32FPVSRS(0, R4, R7) - /* FP/VSX off again */ - MTMSRD(r6) - SYNC - blr #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */ diff --git a/arch/powerpc/kernel/vector.S b/arch/powerpc/kernel/vector.S index f5c80d567d8d..1c5425966204 100644 --- a/arch/powerpc/kernel/vector.S +++ b/arch/powerpc/kernel/vector.S @@ -29,10 +29,6 @@ _GLOBAL(do_load_up_transact_altivec) addi r10,r3,THREAD_TRANSACT_VRSTATE REST_32VRS(0,r4,r10) - /* Disable VEC again. */ - MTMSRD(r6) - isync - blr #endif |