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| author |   Gregory CLEMENT <gregory.clement@bootlin.com> | 2020-11-25 11:32:02 +0100 |
|---|---|---|
| committer |   Marc Zyngier <maz@kernel.org> | 2020-12-11 14:47:49 +0000 |
| commit | b307ee828f61bc65d918e820a93b5c547a73dda3 (patch) | |
| tree | 7285e8cf869cd5235e5231360ead9225af431cc2 | |
| parent | dt-bindings: interrupt-controller: convert icpu intr bindings to json-schema (diff) | |
| download | linux-dev-b307ee828f61bc65d918e820a93b5c547a73dda3.tar.xz linux-dev-b307ee828f61bc65d918e820a93b5c547a73dda3.zip | |
dt-bindings: interrupt-controller: Add binding for few Microsemi interrupt controllers
Add the Device Tree binding documentation for the Microsemi Jaguar2,
Luton and Serval interrupt controller that is part of the ICPU. It is
connected directly to the MIPS core interrupt controller.
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20201125103206.136498-3-gregory.clement@bootlin.com
| -rw-r--r-- | Documentation/devicetree/bindings/interrupt-controller/mscc,ocelot-icpu-intr.yaml | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/interrupt-controller/mscc,ocelot-icpu-intr.yaml b/Documentation/devicetree/bindings/interrupt-controller/mscc,ocelot-icpu-intr.yaml index be82920f6798..27b798bfe29b 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/mscc,ocelot-icpu-intr.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/mscc,ocelot-icpu-intr.yaml @@ -21,7 +21,11 @@ properties: compatible: items: - enum: + - mscc,jaguar2-icpu-intr + - mscc,luton-icpu-intr - mscc,ocelot-icpu-intr + - mscc,serval-icpu-intr + '#interrupt-cells': const: 1 |