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| author |   Kevin Wang <kevin1.wang@amd.com> | 2019-07-19 16:06:29 +0800 |
|---|---|---|
| committer |   Alex Deucher <alexander.deucher@amd.com> | 2019-07-22 14:57:22 -0500 |
| commit | b629167d686787507f35a8bfb46b8b12f4f26eb7 (patch) | |
| tree | 033b927b0b6f69aa085251e7ccd83569378359be | |
| parent | drm/amd/powerplay: custom peak clock freq for navi10 (diff) | |
| download | linux-dev-b629167d686787507f35a8bfb46b8b12f4f26eb7.tar.xz linux-dev-b629167d686787507f35a8bfb46b8b12f4f26eb7.zip | |
drm/amd/powerplay: remove redundancy debug log in smu
remove redundacy debug log in smu.
eg:
[ 6897.969447] amdgpu: [powerplay] smu 11 clk dpm feature 1 is not enabled
[ 6897.969448] amdgpu: [powerplay] smu 11 clk dpm feature 1 is not enabled
[ 6897.969448] amdgpu: [powerplay] smu 11 clk dpm feature 1 is not enabled
[ 6899.024114] amdgpu: [powerplay] Unsupported SMU message: 38
[ 6899.024151] amdgpu: [powerplay] smu 11 clk dpm feature 1 is not enabled
[ 6899.024151] amdgpu: [powerplay] smu 11 clk dpm feature 1 is not enabled
[ 6899.024152] amdgpu: [powerplay] smu 11 clk dpm feature 1 is not enabled
[ 6900.078296] amdgpu: [powerplay] Unsupported SMU message: 38
[ 6900.078332] amdgpu: [powerplay] smu 11 clk dpm feature 1 is not enabled
[ 6900.078332] amdgpu: [powerplay] smu 11 clk dpm feature 1 is not enabled
[ 6900.078333] amdgpu: [powerplay] smu 11 clk dpm feature 1 is not enabled
[ 6901.133230] amdgpu: [powerplay] Unsupported SMU message: 38
Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| -rw-r--r-- | drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 1 | ||||
| -rw-r--r-- | drivers/gpu/drm/amd/powerplay/navi10_ppt.c | 6 | ||||
| -rw-r--r-- | drivers/gpu/drm/amd/powerplay/vega20_ppt.c | 6 |
3 files changed, 0 insertions, 13 deletions
diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c index d3cc90eb160c..0b1285ddc954 100644 --- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c +++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c @@ -262,7 +262,6 @@ bool smu_clk_dpm_is_enabled(struct smu_context *smu, enum smu_clk_type clk_type) } if(!smu_feature_is_enabled(smu, feature_id)) { - pr_warn("smu %d clk dpm feature %d is not enabled\n", clk_type, feature_id); return false; } diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c index b7b44ffe2670..c178062d00a3 100644 --- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c +++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c @@ -217,7 +217,6 @@ static int navi10_get_smu_msg_index(struct smu_context *smc, uint32_t index) mapping = navi10_message_map[index]; if (!(mapping.valid_mapping)) { - pr_warn("Unsupported SMU message: %d\n", index); return -EINVAL; } @@ -233,7 +232,6 @@ static int navi10_get_smu_clk_index(struct smu_context *smc, uint32_t index) mapping = navi10_clk_map[index]; if (!(mapping.valid_mapping)) { - pr_warn("Unsupported SMU clock: %d\n", index); return -EINVAL; } @@ -249,7 +247,6 @@ static int navi10_get_smu_feature_index(struct smu_context *smc, uint32_t index) mapping = navi10_feature_mask_map[index]; if (!(mapping.valid_mapping)) { - pr_warn("Unsupported SMU feature: %d\n", index); return -EINVAL; } @@ -265,7 +262,6 @@ static int navi10_get_smu_table_index(struct smu_context *smc, uint32_t index) mapping = navi10_table_map[index]; if (!(mapping.valid_mapping)) { - pr_warn("Unsupported SMU table: %d\n", index); return -EINVAL; } @@ -281,7 +277,6 @@ static int navi10_get_pwr_src_index(struct smu_context *smc, uint32_t index) mapping = navi10_pwr_src_map[index]; if (!(mapping.valid_mapping)) { - pr_warn("Unsupported power source: %d\n", index); return -EINVAL; } @@ -298,7 +293,6 @@ static int navi10_get_workload_type(struct smu_context *smu, enum PP_SMC_POWER_P mapping = navi10_workload_map[profile]; if (!(mapping.valid_mapping)) { - pr_warn("Unsupported workload: %d\n", (int)profile); return -EINVAL; } diff --git a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c index 080956ea0570..afcd33941f07 100644 --- a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c +++ b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c @@ -232,7 +232,6 @@ static int vega20_get_smu_table_index(struct smu_context *smc, uint32_t index) mapping = vega20_table_map[index]; if (!(mapping.valid_mapping)) { - pr_warn("Unsupported SMU table: %d\n", index); return -EINVAL; } @@ -248,7 +247,6 @@ static int vega20_get_pwr_src_index(struct smu_context *smc, uint32_t index) mapping = vega20_pwr_src_map[index]; if (!(mapping.valid_mapping)) { - pr_warn("Unsupported power source: %d\n", index); return -EINVAL; } @@ -264,7 +262,6 @@ static int vega20_get_smu_feature_index(struct smu_context *smc, uint32_t index) mapping = vega20_feature_mask_map[index]; if (!(mapping.valid_mapping)) { - pr_warn("Unsupported SMU feature: %d\n", index); return -EINVAL; } @@ -280,7 +277,6 @@ static int vega20_get_smu_clk_index(struct smu_context *smc, uint32_t index) mapping = vega20_clk_map[index]; if (!(mapping.valid_mapping)) { - pr_warn("Unsupported SMU clock: %d\n", index); return -EINVAL; } @@ -296,7 +292,6 @@ static int vega20_get_smu_msg_index(struct smu_context *smc, uint32_t index) mapping = vega20_message_map[index]; if (!(mapping.valid_mapping)) { - pr_warn("Unsupported SMU message: %d\n", index); return -EINVAL; } @@ -312,7 +307,6 @@ static int vega20_get_workload_type(struct smu_context *smu, enum PP_SMC_POWER_P mapping = vega20_workload_map[profile]; if (!(mapping.valid_mapping)) { - pr_warn("Unsupported SMU workload: %d\n", (int)profile); return -EINVAL; } |