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| author |   Andre Przywara <andre.przywara@arm.com> | 2020-08-28 14:05:54 +0100 |
|---|---|---|
| committer |   Sudeep Holla <sudeep.holla@arm.com> | 2020-09-07 10:54:08 +0100 |
| commit | b83ded8a31e314545727bd5ee852a1f65a6ad1e9 (patch) | |
| tree | 86bf25e6a089d25f5e37bca162829d669608754a | |
| parent | ARM: dts: arm: Fix SP805 clocks (diff) | |
| download | linux-dev-b83ded8a31e314545727bd5ee852a1f65a6ad1e9.tar.xz linux-dev-b83ded8a31e314545727bd5ee852a1f65a6ad1e9.zip | |
arm64: dts: arm: Fix SP805 clock-names
The SP805 binding sets the name for the actual watchdog clock to
"wdog_clk" (with an underscore).
Change the name in the DTs for ARM Ltd. platforms to match that. The
Linux and U-Boot driver use the *first* clock for this purpose anyway,
so it does not break anything.
Link: https://lore.kernel.org/r/20200828130602.42203-3-andre.przywara@arm.com
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
| -rw-r--r-- | arch/arm64/boot/dts/arm/juno-motherboard.dtsi | 2 | ||||
| -rw-r--r-- | arch/arm64/boot/dts/arm/rtsm_ve-motherboard.dtsi | 2 |
2 files changed, 2 insertions, 2 deletions
diff --git a/arch/arm64/boot/dts/arm/juno-motherboard.dtsi b/arch/arm64/boot/dts/arm/juno-motherboard.dtsi index eeee51f1251b..40d95c58b55e 100644 --- a/arch/arm64/boot/dts/arm/juno-motherboard.dtsi +++ b/arch/arm64/boot/dts/arm/juno-motherboard.dtsi @@ -251,7 +251,7 @@ reg = <0x0f0000 0x10000>; interrupts = <7>; clocks = <&mb_clk24mhz>, <&soc_smc50mhz>; - clock-names = "wdogclk", "apb_pclk"; + clock-names = "wdog_clk", "apb_pclk"; }; v2m_timer01: timer@110000 { diff --git a/arch/arm64/boot/dts/arm/rtsm_ve-motherboard.dtsi b/arch/arm64/boot/dts/arm/rtsm_ve-motherboard.dtsi index 001a0a3c7f66..4c4a381d2c75 100644 --- a/arch/arm64/boot/dts/arm/rtsm_ve-motherboard.dtsi +++ b/arch/arm64/boot/dts/arm/rtsm_ve-motherboard.dtsi @@ -195,7 +195,7 @@ reg = <0x0f0000 0x1000>; interrupts = <0>; clocks = <&v2m_refclk32khz>, <&v2m_clk24mhz>; - clock-names = "wdogclk", "apb_pclk"; + clock-names = "wdog_clk", "apb_pclk"; }; v2m_timer01: timer@110000 { |