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authorMaxime Ripard <maxime.ripard@bootlin.com>2018-11-22 11:18:09 +0100
committerMaxime Ripard <maxime.ripard@bootlin.com>2018-11-28 15:14:13 +0100
commitbb4d3ec9a7daa327608e69bb45704f76e2d9413c (patch)
treee8309506c77591b0b2bb8051f3155437123517db
parentARM: dts: sun7i: Change pinctrl nodes to avoid warning (diff)
ARM: dts: sun7i: Split the RTS and CTS pins out of the UART nodes
Some UART nodes on the A20 DTSI do not share the same pattern that we use everywhere else, with the RTS and CTS pins split away from the TX and RX pins. Make those pin groups consistent with the rest of our DT. Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com> Acked-by: Chen-Yu Tsai <wens@csie.org>
-rw-r--r--arch/arm/boot/dts/sun7i-a20-hummingbird.dts4
-rw-r--r--arch/arm/boot/dts/sun7i-a20-mk808c.dts2
-rw-r--r--arch/arm/boot/dts/sun7i-a20.dtsi14
3 files changed, 15 insertions, 5 deletions
diff --git a/arch/arm/boot/dts/sun7i-a20-hummingbird.dts b/arch/arm/boot/dts/sun7i-a20-hummingbird.dts
index 9ce59d49cf49..a1af7d6726e2 100644
--- a/arch/arm/boot/dts/sun7i-a20-hummingbird.dts
+++ b/arch/arm/boot/dts/sun7i-a20-hummingbird.dts
@@ -215,13 +215,13 @@
&uart2 {
pinctrl-names = "default";
- pinctrl-0 = <&uart2_pi_pins>;
+ pinctrl-0 = <&uart2_pi_pins>, <&uart2_cts_rts_pi_pins>;
status = "okay";
};
&uart3 {
pinctrl-names = "default";
- pinctrl-0 = <&uart3_pg_pins>;
+ pinctrl-0 = <&uart3_pg_pins>, <&uart3_cts_rts_pg_pins>;
status = "okay";
};
diff --git a/arch/arm/boot/dts/sun7i-a20-mk808c.dts b/arch/arm/boot/dts/sun7i-a20-mk808c.dts
index a8d15d01ac1a..b4143a91086b 100644
--- a/arch/arm/boot/dts/sun7i-a20-mk808c.dts
+++ b/arch/arm/boot/dts/sun7i-a20-mk808c.dts
@@ -173,7 +173,7 @@
&uart2 {
pinctrl-names = "default";
- pinctrl-0 = <&uart2_pi_pins>;
+ pinctrl-0 = <&uart2_pi_pins>, <&uart2_cts_rts_pi_pins>;
status = "okay";
};
diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi
index 75669fc51de5..bffd3a21bee3 100644
--- a/arch/arm/boot/dts/sun7i-a20.dtsi
+++ b/arch/arm/boot/dts/sun7i-a20.dtsi
@@ -935,12 +935,22 @@
};
uart2_pi_pins: uart2-pi-pins {
- pins = "PI16", "PI17", "PI18", "PI19";
+ pins = "PI18", "PI19";
+ function = "uart2";
+ };
+
+ uart2_cts_rts_pi_pins: uart2-cts-rts-pi-pins {
+ pins = "PI16", "PI17";
function = "uart2";
};
uart3_pg_pins: uart3-pg-pins {
- pins = "PG6", "PG7", "PG8", "PG9";
+ pins = "PG6", "PG7";
+ function = "uart3";
+ };
+
+ uart3_cts_rts_pg_pins: uart3-cts-rts-pg-pins {
+ pins = "PG8", "PG9";
function = "uart3";
};