diff options
| author |   Evan Quan <evan.quan@amd.com> | 2021-12-08 12:08:39 +0800 |
|---|---|---|
| committer |   Alex Deucher <alexander.deucher@amd.com> | 2022-02-07 18:01:16 -0500 |
| commit | bd42571168ed54d309480856fadea3eb99821253 (patch) | |
| tree | 15e65f1282d12c47647276db54112c87e15318ea | |
| parent | drm/amd/display: Cap pflip irqs per max otg number (diff) | |
drm/amd/pm: correct the way for retrieving enabled ppfeatures on Renoir
As other dGPU asics, Renoir should use smu_cmn_get_enabled_mask() for
that job.
Signed-off-by: Evan Quan <evan.quan@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| -rw-r--r-- | drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c b/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c index 2c1eff9fe4f2..ab9c1c156868 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c @@ -710,7 +710,8 @@ size_t smu_cmn_get_pp_feature_mask(struct smu_context *smu, size_t size = 0; int ret = 0, i; - if (!smu->is_apu) { + if (!smu->is_apu || + (smu->adev->asic_type == CHIP_RENOIR)) { ret = smu_cmn_get_enabled_mask(smu, feature_mask, 2); |