diff options
| author |   Paul Kocialkowski <contact@paulk.fr> | 2020-12-06 17:51:28 +0100 |
|---|---|---|
| committer |   Maxime Ripard <maxime@cerno.tech> | 2021-01-06 17:49:58 +0100 |
| commit | c20e9e7675137d92bca071305e79fcc10364ebf5 (patch) | |
| tree | 609097746bde4dd3a7ae17652daa5d7daa32ff6d | |
| parent | dt-bindings: irq: sun7i-nmi: Add binding documentation for the V3s NMI (diff) | |
| download | linux-dev-c20e9e7675137d92bca071305e79fcc10364ebf5.tar.xz linux-dev-c20e9e7675137d92bca071305e79fcc10364ebf5.zip | |
ARM: dts: sun8i-v3s: Add the V3s NMI IRQ controller
The V3s/V3 has a NMI interrupt controller, mainly used for the AXP209.
Its address follows the system controller block, which was previously
incorrectly described as spanning over 0x1000 address bytes.
Even though this is what the Allwinner documentation indicates,
precedence from other SoCs such as the R40 suggests that this is not
actually the case.
This reduces the system controller address span up to the NMI
controller and adds a node for the controller, with its dedicated
compatible.
While the interrupt number was found in Allwinner's documentation,
the address for the controller is specified in any Allwinner SDK
supporting sun8iw8 (V3/V3s) at:
drivers/power/axp_power/axp20/axp20-board.c
It was tested to work on a V3 board with an AXP209 connected to the
NMI interrupt line.
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
Link: https://lore.kernel.org/r/20201206165131.1041983-3-contact@paulk.fr
| -rw-r--r-- | arch/arm/boot/dts/sun8i-v3s.dtsi | 11 |
1 files changed, 10 insertions, 1 deletions
diff --git a/arch/arm/boot/dts/sun8i-v3s.dtsi b/arch/arm/boot/dts/sun8i-v3s.dtsi index f8f19d8fa795..b7b0e685e26b 100644 --- a/arch/arm/boot/dts/sun8i-v3s.dtsi +++ b/arch/arm/boot/dts/sun8i-v3s.dtsi @@ -157,12 +157,21 @@ syscon: system-control@1c00000 { compatible = "allwinner,sun8i-v3s-system-control", "allwinner,sun8i-h3-system-control"; - reg = <0x01c00000 0x1000>; + reg = <0x01c00000 0xd0>; #address-cells = <1>; #size-cells = <1>; ranges; }; + nmi_intc: interrupt-controller@1c000d0 { + compatible = "allwinner,sun8i-v3s-nmi", + "allwinner,sun9i-a80-nmi"; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x01c000d0 0x0c>; + interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; + }; + tcon0: lcd-controller@1c0c000 { compatible = "allwinner,sun8i-v3s-tcon"; reg = <0x01c0c000 0x1000>; |