diff options
| author |   Sakari Ailus <sakari.ailus@linux.intel.com> | 2020-06-25 14:13:55 +0200 |
|---|---|---|
| committer |   Mauro Carvalho Chehab <mchehab+huawei@kernel.org> | 2020-12-07 15:34:47 +0100 |
| commit | c3833a228cef7121cb7fc64d5ef71eedcc6f2f01 (patch) | |
| tree | 7312741116b1d6b6e9cca1ab2fc788a8e98b5479 | |
| parent | media: dt-bindings: schema indentation fixes (diff) | |
media: ccs-pll: Don't use div_u64 to divide a 32-bit number
pll->pll_op_clk_freq is a 32-bit number. It does not need div_u64 to
divide it.
Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
| -rw-r--r-- | drivers/media/i2c/ccs-pll.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/media/i2c/ccs-pll.c b/drivers/media/i2c/ccs-pll.c index 0d57bac1599a..1cfe6cf7e51c 100644 --- a/drivers/media/i2c/ccs-pll.c +++ b/drivers/media/i2c/ccs-pll.c @@ -445,7 +445,7 @@ int ccs_pll_calculate(struct device *dev, const struct ccs_pll_limits *limits, min_pre_pll_clk_div, max_pre_pll_clk_div); i = gcd(pll->pll_op_clk_freq_hz, pll->ext_clk_freq_hz); - mul = div_u64(pll->pll_op_clk_freq_hz, i); + mul = pll->pll_op_clk_freq_hz / i; div = pll->ext_clk_freq_hz / i; dev_dbg(dev, "mul %u / div %u\n", mul, div); |