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author | 2019-08-07 22:31:50 -0500 | |
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committer | 2020-04-28 16:20:28 -0400 | |
commit | c5efd80f48e481946ba201412c7f39b19b39a40b (patch) | |
tree | a1bfb46116e284377b1b2a5b5a533b3188d106bf | |
parent | drm/amdgpu: add UAPI to create secure commands (v3) (diff) | |
download | linux-dev-c5efd80f48e481946ba201412c7f39b19b39a40b.tar.xz linux-dev-c5efd80f48e481946ba201412c7f39b19b39a40b.zip |
drm/amdgpu: define the TMZ bit for the PTE
Define the TMZ (encryption) bit in the page table entry (PTE) for
Raven and newer asics.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
-rw-r--r-- | drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h index b13c14d6b820..fd61466dc226 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h @@ -54,6 +54,9 @@ struct amdgpu_bo_list_entry; #define AMDGPU_PTE_SYSTEM (1ULL << 1) #define AMDGPU_PTE_SNOOPED (1ULL << 2) +/* RV+ */ +#define AMDGPU_PTE_TMZ (1ULL << 3) + /* VI only */ #define AMDGPU_PTE_EXECUTABLE (1ULL << 4) |