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| author |   Sagar Kamble <sagar.a.kamble@intel.com> | 2015-04-12 11:28:14 +0530 |
|---|---|---|
| committer |   Daniel Vetter <daniel.vetter@ffwll.ch> | 2015-04-13 11:24:25 +0200 |
| commit | cb07bae0c47c5b66e8e1cc94988d8b48a415ec7d (patch) | |
| tree | 76cd49abd59b2441a028ac744507dd01d9288875 | |
| parent | drm/i915: Allocate connector state together with the connectors (diff) | |
| download | linux-dev-cb07bae0c47c5b66e8e1cc94988d8b48a415ec7d.tar.xz linux-dev-cb07bae0c47c5b66e8e1cc94988d8b48a415ec7d.zip | |
drm/i915: Disable Render power gating
When RC6 along with Render power gating is enabled, GPU hang
happens due to lack of synchronization between GTI and Render
power gating.
v2: Updated commit message and WA name (Damien)
Change-Id: If1614206341eb52a21eadae8c5ebb2655029b50c
Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Sagar Kamble <sagar.a.kamble@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
| -rw-r--r-- | drivers/gpu/drm/i915/intel_pm.c | 7 |
1 files changed, 5 insertions, 2 deletions
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index e04ef19673a9..fc7e0c7545fd 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -4346,9 +4346,12 @@ static void gen9_enable_rc6(struct drm_device *dev) GEN6_RC_CTL_EI_MODE(1) | rc6_mask); - /* 3b: Enable Coarse Power Gating only when RC6 is enabled */ + /* + * 3b: Enable Coarse Power Gating only when RC6 is enabled. + * WaDisableRenderPowerGating:skl,bxt - Render PG need to be disabled with RC6. + */ I915_WRITE(GEN9_PG_ENABLE, (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ? - (GEN9_RENDER_PG_ENABLE | GEN9_MEDIA_PG_ENABLE) : 0); + GEN9_MEDIA_PG_ENABLE : 0); intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |