diff options
| author |   William Zhang <william.zhang@broadcom.com> | 2022-08-01 12:44:45 -0700 |
|---|---|---|
| committer |   Florian Fainelli <f.fainelli@gmail.com> | 2022-08-15 09:35:51 -0700 |
| commit | d1475cdec17b30049c0dd69094c4ebf6e018e7c1 (patch) | |
| tree | 2c73a7d5ea622fb91cb1d661aaff5990f0c5ac66 | |
| parent | Linux 6.0-rc1 (diff) | |
| download | linux-dev-d1475cdec17b30049c0dd69094c4ebf6e018e7c1.tar.xz linux-dev-d1475cdec17b30049c0dd69094c4ebf6e018e7c1.zip | |
ARM: dts: bcmbca: bcm63178: fix timer node cpu mask flag
The cpu mask flag value should match the number of cpu cores in the
chip. Correct the value to three cpus for BCM63178 triple core SoC.
Fixes: fc85b7e64acb ("ARM: dts: add dts files for bcmbca soc 63178")
Signed-off-by: William Zhang <william.zhang@broadcom.com>
Link: https://lore.kernel.org/r/20220801194448.29363-1-william.zhang@broadcom.com
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
| -rw-r--r-- | arch/arm/boot/dts/bcm63178.dtsi | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/arch/arm/boot/dts/bcm63178.dtsi b/arch/arm/boot/dts/bcm63178.dtsi index 5463443f0762..14d2c5bd2c52 100644 --- a/arch/arm/boot/dts/bcm63178.dtsi +++ b/arch/arm/boot/dts/bcm63178.dtsi @@ -46,10 +46,10 @@ timer { compatible = "arm,armv7-timer"; - interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, - <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, - <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, - <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(3) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(3) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(3) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(3) | IRQ_TYPE_LEVEL_LOW)>; arm,cpu-registers-not-fw-configured; }; |