diff options
| author |   Zhong Kaihua <zhongkaihua@huawei.com> | 2017-08-07 22:51:56 +0800 |
|---|---|---|
| committer |   Stephen Boyd <sboyd@codeaurora.org> | 2017-11-14 09:48:59 -0800 |
| commit | d33fb1b9f0fcb67f2b9f8b1891465a088a9480f8 (patch) | |
| tree | 3cbf8228d5ff1de69e50ed66726e281e0ecabb86 | |
| parent | clk: hi6220: mark clock cs_atb_syspll as critical (diff) | |
| download | linux-dev-d33fb1b9f0fcb67f2b9f8b1891465a088a9480f8.tar.xz linux-dev-d33fb1b9f0fcb67f2b9f8b1891465a088a9480f8.zip | |
clk: hi3660: fix incorrect uart3 clock freqency
UART3 clock rate is doubled in previous commit.
This error is not detected until recently a mezzanine board which makes
real use of uart3 port (through LS connector of 96boards) was setup
and tested on hi3660-hikey960 board.
This patch changes clock source rate of clk_factor_uart3 to 100000000.
Signed-off-by: Zhong Kaihua <zhongkaihua@huawei.com>
Signed-off-by: Guodong Xu <guodong.xu@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
| -rw-r--r-- | drivers/clk/hisilicon/clk-hi3660.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/clk/hisilicon/clk-hi3660.c b/drivers/clk/hisilicon/clk-hi3660.c index a18258eb89cb..f40419959656 100644 --- a/drivers/clk/hisilicon/clk-hi3660.c +++ b/drivers/clk/hisilicon/clk-hi3660.c @@ -34,7 +34,7 @@ static const struct hisi_fixed_rate_clock hi3660_fixed_rate_clks[] = { /* crgctrl */ static const struct hisi_fixed_factor_clock hi3660_crg_fixed_factor_clks[] = { - { HI3660_FACTOR_UART3, "clk_factor_uart3", "iomcu_peri0", 1, 8, 0, }, + { HI3660_FACTOR_UART3, "clk_factor_uart3", "iomcu_peri0", 1, 16, 0, }, { HI3660_CLK_FACTOR_MMC, "clk_factor_mmc", "clkin_sys", 1, 6, 0, }, { HI3660_CLK_GATE_I2C0, "clk_gate_i2c0", "clk_i2c0_iomcu", 1, 4, 0, }, { HI3660_CLK_GATE_I2C1, "clk_gate_i2c1", "clk_i2c1_iomcu", 1, 4, 0, }, |